diff --git a/device/testing/device-sony-ps4/APKBUILD b/device/testing/device-sony-ps4/APKBUILD
new file mode 100644
index 0000000000000000000000000000000000000000..20258777b01bf9d501338ecd9a0427a02e3ad754
--- /dev/null
+++ b/device/testing/device-sony-ps4/APKBUILD
@@ -0,0 +1,38 @@
+pkgname=device-sony-ps4
+pkgdesc="Sony Playstation 4 Original"
+pkgver=1
+pkgrel=0
+url="https://postmarketos.org"
+license="MIT"
+arch="x86_64"
+options="!check !archcheck"
+depends="
+ linux-sony-ps4
+ postmarketos-base
+ grub-efi-x86
+ "
+makedepends="devicepkg-dev"
+source="
+ deviceinfo
+ modules-initfs
+ "
+subpackages="$pkgname-nonfree-firmware:nonfree_firmware"
+
+build() {
+ devicepkg_build $startdir $pkgname
+}
+
+package() {
+ devicepkg_package $startdir $pkgname
+}
+
+nonfree_firmware() {
+ pkgdesc="Wi-Fi and bluetooth firmware"
+ depends="linux-firmware-mrvl"
+ mkdir "$subpkgdir"
+}
+
+sha512sums="
+065faa7aed5acc1a8e15e1fe1e06929b57dc11030b7c842e7a46f7d4fae310ce3796a2d760a95222177c0d1d23f1e6cd982c3241a06e50c6d4961e69d3ce4450 deviceinfo
+24ed2457630757df9e69b3216b883c3032848b3cc692fd5cf0252baa6dc0dbea33e95b20767a9cb36e8461a8e79e65d50cc5ecd3a6801dc3e8e90951a34138aa modules-initfs
+"
diff --git a/device/testing/device-sony-ps4/deviceinfo b/device/testing/device-sony-ps4/deviceinfo
new file mode 100644
index 0000000000000000000000000000000000000000..a29b660d38d76c50b7c00fa6aea441ed5d97daf2
--- /dev/null
+++ b/device/testing/device-sony-ps4/deviceinfo
@@ -0,0 +1,24 @@
+# Reference: <https://postmarketos.org/deviceinfo>
+# Please use double quotes only. You can source this file in shell
+# scripts.
+
+deviceinfo_format_version="0"
+deviceinfo_name="Sony Playstation 4"
+deviceinfo_manufacturer="Sony"
+deviceinfo_codename="sony-ps4"
+deviceinfo_year="2013"
+deviceinfo_arch="x86_64"
+deviceinfo_gpu_accelerated="true"
+
+# Device related
+deviceinfo_chassis="desktop"
+deviceinfo_keyboard="false"
+deviceinfo_external_storage="true"
+deviceinfo_screen_width="1920"
+deviceinfo_screen_height="1080"
+deviceinfo_framebuffer_landscape="true"
+# Bootloader related
+deviceinfo_flash_method="none"
+deviceinfo_kernel_cmdline="panic=0 clocksource=tsc consoleblank=0 drm.debug=0 drm.edid_firmware=edid/my_edid.bin"
+deviceinfo_partition_type="gpt"
+deviceinfo_boot_filesystem="fat32"
diff --git a/device/testing/device-sony-ps4/modules-initfs b/device/testing/device-sony-ps4/modules-initfs
new file mode 100644
index 0000000000000000000000000000000000000000..af5d7063343f528369e704adef4a9497f4ad051d
--- /dev/null
+++ b/device/testing/device-sony-ps4/modules-initfs
@@ -0,0 +1 @@
+hid-steam
diff --git a/device/testing/linux-sony-ps4/0001-feat-very-basic-platform-support.patch b/device/testing/linux-sony-ps4/0001-feat-very-basic-platform-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..3b5579cdf04d7326a28d4ec61dde7f8609b48d56
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0001-feat-very-basic-platform-support.patch
@@ -0,0 +1,2211 @@
+From a39f0b4736da33e9bee30fa890232892e73a0000 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Sun, 19 Dec 2021 18:23:28 +0100
+Subject: [PATCH 01/22] feat: very basic platform support
+
+---
+ arch/x86/Kconfig | 10 +-
+ arch/x86/include/asm/ps4.h | 60 +++
+ arch/x86/include/asm/setup.h | 6 +
+ arch/x86/include/uapi/asm/bootparam.h | 1 +
+ arch/x86/kernel/amd_nb.c | 2 +
+ arch/x86/kernel/head64.c | 3 +
+ arch/x86/platform/Makefile | 1 +
+ arch/x86/platform/ps4/Makefile | 1 +
+ arch/x86/platform/ps4/calibrate.c | 116 +++++
+ arch/x86/platform/ps4/ps4.c | 74 ++++
+ drivers/Makefile | 1 +
+ drivers/iommu/amd/init.c | 4 +
+ drivers/pci/probe.c | 12 +
+ drivers/ps4/Makefile | 9 +
+ drivers/ps4/aeolia.h | 172 ++++++++
+ drivers/ps4/icc/i2c.c | 156 +++++++
+ drivers/ps4/ps4-apcie-icc.c | 602 ++++++++++++++++++++++++++
+ drivers/ps4/ps4-apcie-pwrbutton.c | 69 +++
+ drivers/ps4/ps4-apcie-uart.c | 67 +++
+ drivers/ps4/ps4-apcie.c | 560 ++++++++++++++++++++++++
+ include/linux/pci_ids.h | 26 ++
+ 21 files changed, 1951 insertions(+), 1 deletion(-)
+ create mode 100644 arch/x86/include/asm/ps4.h
+ create mode 100644 arch/x86/platform/ps4/Makefile
+ create mode 100644 arch/x86/platform/ps4/calibrate.c
+ create mode 100644 arch/x86/platform/ps4/ps4.c
+ create mode 100644 drivers/ps4/Makefile
+ create mode 100644 drivers/ps4/aeolia.h
+ create mode 100644 drivers/ps4/icc/i2c.c
+ create mode 100644 drivers/ps4/ps4-apcie-icc.c
+ create mode 100644 drivers/ps4/ps4-apcie-pwrbutton.c
+ create mode 100644 drivers/ps4/ps4-apcie-uart.c
+ create mode 100644 drivers/ps4/ps4-apcie.c
+
+diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
+index a08ce6360382..c510ff611adc 100644
+--- a/arch/x86/Kconfig
++++ b/arch/x86/Kconfig
+@@ -541,7 +541,15 @@ config X86_NUMACHIP
+ Adds support for Numascale NumaChip large-SMP systems. Needed to
+ enable more than ~168 cores.
+ If you don't have one of these, you should say N here.
+-
++
++config X86_PS4
++ bool "Sony PlayStation 4"
++ depends on X86_64
++ depends on X86_EXTENDED_PLATFORM
++ depends on PCI
++ help
++ Select to include support for the Sony PlayStation 4 game console.
++
+ config X86_VSMP
+ bool "ScaleMP vSMP"
+ select HYPERVISOR_GUEST
+diff --git a/arch/x86/include/asm/ps4.h b/arch/x86/include/asm/ps4.h
+new file mode 100644
+index 000000000000..60ee1c4f4f18
+--- /dev/null
++++ b/arch/x86/include/asm/ps4.h
+@@ -0,0 +1,60 @@
++/*
++ * ps4.h: Sony PS4 platform setup code
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; version 2
++ * of the License.
++ */
++#ifndef _ASM_X86_PS4_H
++#define _ASM_X86_PS4_H
++
++#ifdef CONFIG_X86_PS4
++
++#include <linux/irqdomain.h>
++
++#define PS4_DEFAULT_TSC_FREQ 1594000000
++
++#define EMC_TIMER_BASE 0xd0281000
++#define EMC_TIMER_VALUE 0x28
++
++extern unsigned long ps4_calibrate_tsc(void);
++
++/*
++ * The PS4 Aeolia southbridge device is a composite device containing some
++ * standard-ish, some not-so-standard, and some completely custom functions,
++ * all using special MSI handling. This function does the equivalent of
++ * pci_enable_msi_range and friends, for those devices. Only works after the
++ * Aeolia MSR routing function device (function 4) has been probed.
++ * Returns 1 or count, depending on IRQ allocation constraints, or negative on
++ * error. Assigned IRQ(s) start at dev->irq.
++ */
++extern int apcie_assign_irqs(struct pci_dev *dev, int nvec);
++extern void apcie_free_irqs(unsigned int virq, unsigned int nr_irqs);
++
++extern int apcie_status(void);
++extern int apcie_icc_cmd(u8 major, u16 minor, const void *data,
++ u16 length, void *reply, u16 reply_length);
++
++
++#else
++
++static inline int apcie_assign_irqs(struct pci_dev *dev, int nvec)
++{
++ return -ENODEV;
++}
++static inline void apcie_free_irqs(unsigned int virq, unsigned int nvec)
++{
++}
++static inline int apcie_status(void)
++{
++ return -ENODEV;
++}
++static inline int apcie_icc_cmd(u8 major, u16 minor, const void *data,
++ u16 length, void *reply, u16 reply_length)
++{
++ return -ENODEV;
++}
++
++#endif
++#endif
+diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h
+index a12458a7a8d4..074de91f3762 100644
+--- a/arch/x86/include/asm/setup.h
++++ b/arch/x86/include/asm/setup.h
+@@ -66,6 +66,12 @@ extern void x86_ce4100_early_setup(void);
+ static inline void x86_ce4100_early_setup(void) { }
+ #endif
+
++#ifdef CONFIG_X86_PS4
++extern void x86_ps4_early_setup(void);
++#else
++static inline void x86_ps4_early_setup(void) { }
++#endif
++
+ #ifndef _SETUP
+
+ #include <asm/espfix.h>
+diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h
+index b25d3f82c2f3..6666ca2f100c 100644
+--- a/arch/x86/include/uapi/asm/bootparam.h
++++ b/arch/x86/include/uapi/asm/bootparam.h
+@@ -265,6 +265,7 @@ enum x86_hardware_subarch {
+ X86_SUBARCH_XEN,
+ X86_SUBARCH_INTEL_MID,
+ X86_SUBARCH_CE4100,
++ X86_SUBARCH_PS4,
+ X86_NR_SUBARCHS,
+ };
+
+diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
+index c92c9c774c0e..d1fb4f09d727 100644
+--- a/arch/x86/kernel/amd_nb.c
++++ b/arch/x86/kernel/amd_nb.c
+@@ -54,6 +54,7 @@ static const struct pci_device_id amd_nb_misc_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M41H_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
+@@ -72,6 +73,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
++ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M41H_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
+ { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
+diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
+index 5036104d5470..ca800a2f28b3 100644
+--- a/arch/x86/kernel/head64.c
++++ b/arch/x86/kernel/head64.c
+@@ -520,6 +520,9 @@ void __init x86_64_start_reservations(char *real_mode_data)
+ case X86_SUBARCH_INTEL_MID:
+ x86_intel_mid_early_setup();
+ break;
++ case X86_SUBARCH_PS4:
++ x86_ps4_early_setup();
++ break;
+ default:
+ break;
+ }
+diff --git a/arch/x86/platform/Makefile b/arch/x86/platform/Makefile
+index 3ed03a2552d0..fd92ee69b37c 100644
+--- a/arch/x86/platform/Makefile
++++ b/arch/x86/platform/Makefile
+@@ -9,6 +9,7 @@ obj-y += intel/
+ obj-y += intel-mid/
+ obj-y += intel-quark/
+ obj-y += olpc/
++obj-y += ps4/
+ obj-y += scx200/
+ obj-y += ts5500/
+ obj-y += uv/
+diff --git a/arch/x86/platform/ps4/Makefile b/arch/x86/platform/ps4/Makefile
+new file mode 100644
+index 000000000000..4d5fcde3a080
+--- /dev/null
++++ b/arch/x86/platform/ps4/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_X86_PS4) += ps4.o calibrate.o
+diff --git a/arch/x86/platform/ps4/calibrate.c b/arch/x86/platform/ps4/calibrate.c
+new file mode 100644
+index 000000000000..232866816512
+--- /dev/null
++++ b/arch/x86/platform/ps4/calibrate.c
+@@ -0,0 +1,116 @@
++/*
++ * calibrate.c: Sony PS4 TSC/LAPIC calibration
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; version 2
++ * of the License.
++ */
++
++#define pr_fmt(fmt) "ps4: " fmt
++
++#include <linux/jiffies.h>
++#include <asm/io.h>
++#include <asm/msr.h>
++#include <asm/ps4.h>
++#include <asm/delay.h>
++#include <asm/apic.h>
++
++/* The PS4 southbridge (Aeolia) has an EMC timer that ticks at 32.768kHz,
++ * which seems to be an appropriate clock reference for calibration. Both TSC
++ * and the LAPIC timer are based on the core clock frequency and thus can be
++ * calibrated together. */
++static void __iomem *emc_timer = NULL;
++
++static __init inline u32 emctimer_read32(unsigned int reg)
++{
++ return ioread32(emc_timer + reg);
++}
++
++static __init inline void emctimer_write32(unsigned int reg, u32 val)
++{
++ iowrite32(val, emc_timer + reg);
++}
++
++static __init inline u32 emctimer_read(void)
++{
++ u32 t1, t2;
++ t1 = emctimer_read32(EMC_TIMER_VALUE);
++ while (1) {
++ t2 = emctimer_read32(EMC_TIMER_VALUE);
++ if (t1 == t2)
++ return t1;
++ t1 = t2;
++ }
++}
++
++static __init unsigned long ps4_measure_tsc_freq(void)
++{
++ unsigned long ret = 0;
++ u32 t1, t2;
++ u64 tsc1, tsc2;
++
++ // This is part of the Aeolia pcie device, but it's too early to
++ // do this in a driver.
++ emc_timer = ioremap(EMC_TIMER_BASE, 0x100);
++ if (!emc_timer)
++ goto fail;
++
++ // reset/start the timer
++ emctimer_write32(0x84, emctimer_read32(0x84) & (~0x01));
++ // udelay is not calibrated yet, so this is likely wildly off, but good
++ // enough to work.
++ udelay(300);
++ emctimer_write32(0x00, emctimer_read32(0x00) | 0x01);
++ emctimer_write32(0x84, emctimer_read32(0x84) | 0x01);
++
++ t1 = emctimer_read();
++ tsc1 = tsc2 = rdtsc();
++
++ while (emctimer_read() == t1) {
++ // 0.1s timeout should be enough
++ tsc2 = rdtsc();
++ if ((tsc2 - tsc1) > (PS4_DEFAULT_TSC_FREQ/10)) {
++ pr_warn("EMC timer is broken.\n");
++ goto fail;
++ }
++ }
++ pr_info("EMC timer started in %lld TSC ticks\n", tsc2 - tsc1);
++
++ // Wait for a tick boundary
++ t1 = emctimer_read();
++ while ((t2 = emctimer_read()) == t1);
++ tsc1 = rdtsc();
++
++ // Wait for 1024 ticks to elapse (31.25ms)
++ // We don't need to wait very long, as we are looking for transitions.
++ // At this value, a TSC uncertainty of ~50 ticks corresponds to 1ppm of
++ // clock accuracy.
++ while ((emctimer_read() - t2) < 1024);
++ tsc2 = rdtsc();
++
++ // TSC rate is 32 times the elapsed time
++ ret = (tsc2 - tsc1) * 32;
++
++ pr_info("Calibrated TSC frequency: %ld kHz\n", ret);
++fail:
++ if (emc_timer) {
++ iounmap(emc_timer);
++ emc_timer = NULL;
++ }
++ return ret;
++}
++
++unsigned long __init ps4_calibrate_tsc(void)
++{
++ unsigned long tsc_freq = ps4_measure_tsc_freq();
++
++ if (!tsc_freq) {
++ pr_warn("Unable to measure TSC frequency, assuming default.\n");
++ tsc_freq = PS4_DEFAULT_TSC_FREQ;
++ }
++
++ lapic_timer_period = (tsc_freq + 8 * HZ) / (16 * HZ);
++
++ return (tsc_freq + 500) / 1000;
++}
+diff --git a/arch/x86/platform/ps4/ps4.c b/arch/x86/platform/ps4/ps4.c
+new file mode 100644
+index 000000000000..8a3a11263724
+--- /dev/null
++++ b/arch/x86/platform/ps4/ps4.c
+@@ -0,0 +1,74 @@
++/*
++ * ps4.c: Sony PS4 platform setup code
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; version 2
++ * of the License.
++ */
++
++#define pr_fmt(fmt) "ps4: " fmt
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/scatterlist.h>
++#include <linux/irq.h>
++#include <linux/module.h>
++#include <linux/notifier.h>
++
++#include <asm/setup.h>
++#include <asm/mpspec_def.h>
++#include <asm/hw_irq.h>
++#include <asm/apic.h>
++#include <asm/io_apic.h>
++#include <asm/io.h>
++#include <asm/i8259.h>
++#include <asm/reboot.h>
++#include <asm/msr.h>
++#include <asm/ps4.h>
++
++static bool is_ps4;
++bool apcie_initialized;
++
++/*
++ * The RTC is part of the Aeolia PCI device and will be implemented there as
++ * an RTC class device; stub these out.
++ */
++static void dummy_get_wallclock(struct timespec64 *now)
++{
++ now->tv_sec = now->tv_nsec = 0;
++}
++static int dummy_set_wallclock(const struct timespec64 *now)
++{
++ return -ENODEV;
++}
++
++/*
++ * Provide a way for generic drivers to query for the availability of the
++ * PS4 apcie driver/device, which is a dependency for them.
++ */
++int apcie_status(void)
++{
++ if (!is_ps4)
++ return -ENODEV;
++ return apcie_initialized;
++}
++EXPORT_SYMBOL_GPL(apcie_status);
++
++void icc_reboot(void);
++
++/*
++ * PS4 specific x86_init function overrides and early setup calls.
++ */
++void __init x86_ps4_early_setup(void)
++{
++ pr_info("x86_ps4_early_setup: PS4 early setup\n");
++ is_ps4 = true;
++ x86_platform.calibrate_tsc = ps4_calibrate_tsc;
++ x86_platform.get_wallclock = dummy_get_wallclock;
++ x86_platform.set_wallclock = dummy_set_wallclock;
++
++ legacy_pic = &null_legacy_pic;
++ machine_ops.emergency_restart = icc_reboot;
++}
+diff --git a/drivers/Makefile b/drivers/Makefile
+index a110338c860c..6d866a189d6a 100644
+--- a/drivers/Makefile
++++ b/drivers/Makefile
+@@ -85,6 +85,7 @@ obj-$(CONFIG_SPI) += spi/
+ obj-$(CONFIG_SPMI) += spmi/
+ obj-$(CONFIG_HSI) += hsi/
+ obj-$(CONFIG_SLIMBUS) += slimbus/
++obj-$(CONFIG_X86_PS4) += ps4/
+ obj-y += net/
+ obj-$(CONFIG_ATM) += atm/
+ obj-$(CONFIG_FUSION) += message/
+diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
+index 50ea582be591..ea0e5dc8d88d 100644
+--- a/drivers/iommu/amd/init.c
++++ b/drivers/iommu/amd/init.c
+@@ -2603,6 +2603,7 @@ static void __init free_iommu_resources(void)
+ free_iommu_all();
+ }
+
++#ifndef CONFIG_X86_PS4 // TODO this should detect ps4-ness at runtime
+ /* SB IOAPIC is always on this device in AMD systems */
+ #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
+
+@@ -2654,6 +2655,7 @@ static bool __init check_ioapic_information(void)
+
+ return ret;
+ }
++#endif
+
+ static void __init free_dma_resources(void)
+ {
+@@ -2794,8 +2796,10 @@ static int __init early_amd_iommu_init(void)
+ if (!is_kdump_kernel() || amd_iommu_disabled)
+ disable_iommus();
+
++ #ifndef CONFIG_X86_PS4
+ if (amd_iommu_irq_remap)
+ amd_iommu_irq_remap = check_ioapic_information();
++ #endif
+
+ if (amd_iommu_irq_remap) {
+ /*
+diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
+index d9fc02a71baa..5fe5e84fab40 100644
+--- a/drivers/pci/probe.c
++++ b/drivers/pci/probe.c
+@@ -2600,6 +2600,9 @@ static int only_one_child(struct pci_bus *bus)
+ return 0;
+ }
+
++// It can be arbitrary (above 2). Freebsd uses 20, so use that too.
++#define AEOLIA_SLOT_NUM 20
++
+ /**
+ * pci_scan_slot - Scan a PCI slot on a bus for devices
+ * @bus: PCI bus to scan
+@@ -2616,9 +2619,18 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
+ unsigned fn, nr = 0;
+ struct pci_dev *dev;
+
++ u32 l;
++
+ if (only_one_child(bus) && (devfn > 0))
+ return 0; /* Already scanned the entire slot */
+
++ // skip phantom Aeolia devices that bleed through the PCI space
++ if (PCI_SLOT(devfn) != AEOLIA_SLOT_NUM &&
++ pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000) &&
++ (l & 0xffff) == PCI_VENDOR_ID_SONY) {
++ return 0;
++ }
++
+ dev = pci_scan_single_device(bus, devfn);
+ if (!dev)
+ return 0;
+diff --git a/drivers/ps4/Makefile b/drivers/ps4/Makefile
+new file mode 100644
+index 000000000000..4f7d50363f50
+--- /dev/null
++++ b/drivers/ps4/Makefile
+@@ -0,0 +1,9 @@
++# Aeolia PCI devices
++# LISTED IN INIT ORDER \o/ ... ._.
++# N.B. this driver must be init'd before pretty much everything, but actual dependants are:
++# drivers/net/ethernet/marvell/sky2 (implements ps4-gbe)
++obj-y += ps4-apcie.o \
++ ps4-apcie-uart.o \
++ ps4-apcie-icc.o \
++ ps4-apcie-pwrbutton.o \
++ icc/i2c.o \
+diff --git a/drivers/ps4/aeolia.h b/drivers/ps4/aeolia.h
+new file mode 100644
+index 000000000000..13df4b9a4fef
+--- /dev/null
++++ b/drivers/ps4/aeolia.h
+@@ -0,0 +1,172 @@
++#ifndef _AEOLIA_H
++#define _AEOLIA_H
++
++#include <linux/io.h>
++#include <linux/pci.h>
++#include <linux/i2c.h>
++
++enum aeolia_func_id {
++ AEOLIA_FUNC_ID_ACPI = 0,
++ AEOLIA_FUNC_ID_GBE,
++ AEOLIA_FUNC_ID_AHCI,
++ AEOLIA_FUNC_ID_SDHCI,
++ AEOLIA_FUNC_ID_PCIE,
++ AEOLIA_FUNC_ID_DMAC,
++ AEOLIA_FUNC_ID_MEM,
++ AEOLIA_FUNC_ID_XHCI,
++
++ AEOLIA_NUM_FUNCS
++};
++
++/* MSI registers for up to 31, but only 23 known. */
++#define APCIE_NUM_SUBFUNC 23
++
++/* Sub-functions, aka MSI vectors */
++enum apcie_subfunc {
++ APCIE_SUBFUNC_GLUE = 0,
++ APCIE_SUBFUNC_ICC = 3,
++ APCIE_SUBFUNC_HPET = 5,
++ APCIE_SUBFUNC_SFLASH = 11,
++ APCIE_SUBFUNC_RTC = 13,
++ APCIE_SUBFUNC_UART0 = 19,
++ APCIE_SUBFUNC_UART1 = 20,
++ APCIE_SUBFUNC_TWSI = 21,
++
++ APCIE_NUM_SUBFUNCS = 23
++};
++
++#define APCIE_NR_UARTS 2
++
++/* Relative to BAR2 */
++#define APCIE_RGN_RTC_BASE 0x0
++#define APCIE_RGN_RTC_SIZE 0x1000
++
++#define APCIE_RGN_CHIPID_BASE 0x1000
++#define APCIE_RGN_CHIPID_SIZE 0x1000
++
++#define APCIE_REG_CHIPID_0 0x1104
++#define APCIE_REG_CHIPID_1 0x1108
++#define APCIE_REG_CHIPREV 0x110c
++
++/* Relative to BAR4 */
++#define APCIE_RGN_UART_BASE 0x140000
++#define APCIE_RGN_UART_SIZE 0x1000
++
++#define APCIE_RGN_PCIE_BASE 0x1c8000
++#define APCIE_RGN_PCIE_SIZE 0x1000
++
++#define APCIE_RGN_ICC_BASE 0x184000
++#define APCIE_RGN_ICC_SIZE 0x1000
++
++#define APCIE_REG_BAR(x) (APCIE_RGN_PCIE_BASE + (x))
++#define APCIE_REG_BAR_MASK(func, bar) APCIE_REG_BAR(((func) * 0x30) + \
++ ((bar) << 3))
++#define APCIE_REG_BAR_ADDR(func, bar) APCIE_REG_BAR(((func) * 0x30) + \
++ ((bar) << 3) + 0x4)
++
++#define APCIE_REG_MSI(x) (APCIE_RGN_PCIE_BASE + 0x400 + (x))
++#define APCIE_REG_MSI_CONTROL APCIE_REG_MSI(0x0)
++#define APCIE_REG_MSI_MASK(func) APCIE_REG_MSI(0x4c + ((func) << 2))
++#define APCIE_REG_MSI_DATA_HI(func) APCIE_REG_MSI(0x8c + ((func) << 2))
++#define APCIE_REG_MSI_ADDR(func) APCIE_REG_MSI(0xac + ((func) << 2))
++/* This register has non-uniform structure per function, dealt with in code */
++#define APCIE_REG_MSI_DATA_LO(off) APCIE_REG_MSI(0x100 + (off))
++
++/* Not sure what the two individual bits do */
++#define APCIE_REG_MSI_CONTROL_ENABLE 0x05
++
++/* Enable for the entire function, 4 is special */
++#define APCIE_REG_MSI_MASK_FUNC 0x01000000
++#define APCIE_REG_MSI_MASK_FUNC4 0x80000000
++
++#define APCIE_REG_ICC(x) (APCIE_RGN_ICC_BASE + (x))
++#define APCIE_REG_ICC_DOORBELL APCIE_REG_ICC(0x804)
++#define APCIE_REG_ICC_STATUS APCIE_REG_ICC(0x814)
++#define APCIE_REG_ICC_IRQ_MASK APCIE_REG_ICC(0x824)
++
++/* Apply to both DOORBELL and STATUS */
++#define APCIE_ICC_SEND 0x01
++#define APCIE_ICC_ACK 0x02
++
++/* Relative to func6 BAR5 */
++#define APCIE_SPM_ICC_BASE 0x2c000
++#define APCIE_SPM_ICC_SIZE 0x1000
++
++/* Boot params passed from southbridge */
++#define APCIE_SPM_BP_BASE 0x2f000
++#define APCIE_SPM_BP_SIZE 0x20
++
++#define APCIE_SPM_ICC_REQUEST 0x0
++#define APCIE_SPM_ICC_REPLY 0x800
++
++#define ICC_REPLY 0x4000
++#define ICC_EVENT 0x8000
++
++#define ICC_MAGIC 0x42
++#define ICC_EVENT_MAGIC 0x24
++
++struct icc_message_hdr {
++ u8 magic;// not magic: it's ID of sender. 0x32=EAP,0x42=SoC(x86/fbsd)
++ u8 major;// service id (destination)
++ u16 minor;// message id (command)
++ u16 unknown;
++ u16 cookie; //normally monotonic xfer counter, can be set to special values
++ u16 length;
++ u16 checksum;
++} __packed;
++
++#define ICC_HDR_SIZE sizeof(struct icc_message_hdr)
++#define ICC_MIN_SIZE 0x20
++#define ICC_MAX_SIZE 0x7f0
++#define ICC_MIN_PAYLOAD (ICC_MIN_SIZE - ICC_HDR_SIZE)
++#define ICC_MAX_PAYLOAD (ICC_MAX_SIZE - ICC_HDR_SIZE)
++
++struct apcie_icc_dev {
++ phys_addr_t spm_base;
++ void __iomem *spm;
++
++ spinlock_t reply_lock;
++ bool reply_pending;
++
++ struct icc_message_hdr request;
++ struct icc_message_hdr reply;
++ u16 reply_extra_checksum;
++ void *reply_buffer;
++ int reply_length;
++ wait_queue_head_t wq;
++
++ struct i2c_adapter i2c;
++ struct input_dev *pwrbutton_dev;
++};
++
++struct apcie_dev {
++ struct pci_dev *pdev;
++ struct irq_domain *irqdomain;
++ void __iomem *bar0;
++ void __iomem *bar2;
++ void __iomem *bar4;
++
++ int nvec;
++ int serial_line[2];
++ struct apcie_icc_dev icc;
++};
++
++#define sc_err(...) dev_err(&sc->pdev->dev, __VA_ARGS__)
++#define sc_warn(...) dev_warn(&sc->pdev->dev, __VA_ARGS__)
++#define sc_notice(...) dev_notice(&sc->pdev->dev, __VA_ARGS__)
++#define sc_info(...) dev_info(&sc->pdev->dev, __VA_ARGS__)
++#define sc_dbg(...) dev_dbg(&sc->pdev->dev, __VA_ARGS__)
++
++static inline int apcie_irqnum(struct apcie_dev *sc, int index)
++{
++ if (sc->nvec > 1) {
++ return sc->pdev->irq + index;
++ } else {
++ return sc->pdev->irq;
++ }
++}
++
++int apcie_icc_cmd(u8 major, u16 minor, const void *data, u16 length,
++ void *reply, u16 reply_length);
++
++#endif
+diff --git a/drivers/ps4/icc/i2c.c b/drivers/ps4/icc/i2c.c
+new file mode 100644
+index 000000000000..647c26a5cdd4
+--- /dev/null
++++ b/drivers/ps4/icc/i2c.c
+@@ -0,0 +1,156 @@
++#include <linux/serial_8250.h>
++#include <linux/serial_core.h>
++#include <linux/serial_reg.h>
++
++#include "../aeolia.h"
++
++#define ICC_MAX_READ_DATA 0xff
++#define ICC_MAX_WRITE_DATA 0xf8
++
++/* This is actually multiple nested variable length structures, but since we
++ * currently only support one op per transaction, we hardcode it. */
++struct icc_i2c_msg {
++ /* Header */
++ u8 code;
++ u16 length;
++ u8 count;
++ struct {
++ u8 major;
++ u8 length;
++ u8 minor;
++ u8 count;
++ struct {
++ u8 length;
++ u8 slave_addr;
++ u8 reg_addr;
++ u8 data[ICC_MAX_WRITE_DATA];
++ } xfer;
++ } cmd;
++} __packed;
++
++static int icc_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
++ unsigned short flags,
++ char read_write, u8 command, int size,
++ union i2c_smbus_data *data)
++{
++ struct apcie_dev *sc = i2c_get_adapdata(adapter);
++ int ret;
++ struct icc_i2c_msg msg;
++ u8 resultbuf[8 + ICC_MAX_READ_DATA];
++
++ msg.code = 4; /* Don't really know what this is */
++ msg.count = 1;
++ msg.cmd.count = 1;
++ msg.cmd.xfer.slave_addr = addr << 1;
++ msg.cmd.xfer.reg_addr = command;
++ if (read_write == I2C_SMBUS_READ) {
++ msg.cmd.major = 1;
++ msg.cmd.minor = 1;
++ msg.cmd.length = 8;
++ msg.cmd.xfer.data[0] = 0; /* unknown */
++ } else {
++ msg.cmd.major = 2;
++ msg.cmd.minor = 2;
++ }
++
++ switch (size) {
++ case I2C_SMBUS_BYTE_DATA:
++ msg.cmd.xfer.length = 1;
++ if (read_write == I2C_SMBUS_WRITE) {
++ msg.cmd.length = 8;
++ msg.cmd.xfer.data[0] = data->byte;
++ }
++ break;
++ case I2C_SMBUS_WORD_DATA:
++ msg.cmd.xfer.length = 2;
++ if (read_write == I2C_SMBUS_WRITE) {
++ msg.cmd.length = 9;
++ msg.cmd.xfer.data[0] = data->word & 0xff;
++ msg.cmd.xfer.data[1] = data->word >> 8;
++ }
++ break;
++ case I2C_SMBUS_I2C_BLOCK_DATA:
++ msg.cmd.xfer.length = data->block[0];
++ if (read_write == I2C_SMBUS_WRITE) {
++ if (data->block[0] > ICC_MAX_WRITE_DATA) {
++ sc_err("icc-i2c: transaction too large: %d\n",
++ data->block[0]);
++ return -E2BIG;
++ }
++ msg.cmd.length = 7 + data->block[0];
++ memcpy(msg.cmd.xfer.data, &data->block[1],
++ data->block[0]);
++ }
++ break;
++ default:
++ sc_err("icc-i2c: unsupported transaction %d\n", size);
++ return -ENOTSUPP;
++ }
++
++ msg.length = msg.cmd.length + 4;
++ ret = apcie_icc_cmd(0x10, 0x0, &msg, msg.length, resultbuf,
++ sizeof(resultbuf));
++ if (ret < 2 || ret > sizeof(resultbuf)) {
++ sc_err("icc-i2c: icc command failed: %d\n", ret);
++ return -EIO;
++ }
++ if (resultbuf[0] != 0 || resultbuf[1] != 0) {
++ sc_err("icc-i2c: i2c command failed: %d, %d\n",
++ resultbuf[0], resultbuf[1]);
++ return -EIO;
++ }
++
++ if (read_write == I2C_SMBUS_READ)
++ switch (size) {
++ case I2C_SMBUS_BYTE_DATA:
++ data->byte = resultbuf[8];
++ break;
++ case I2C_SMBUS_WORD_DATA:
++ data->word = resultbuf[8] | (resultbuf[9] << 8);
++ break;
++ case I2C_SMBUS_I2C_BLOCK_DATA:
++ memcpy(&data->block[1], &resultbuf[8],
++ data->block[0]);
++ break;
++ }
++
++ return 0;
++}
++
++u32 icc_i2c_functionality(struct i2c_adapter *adap)
++{
++ return I2C_FUNC_SMBUS_BYTE_DATA |
++ I2C_FUNC_SMBUS_WORD_DATA |
++ I2C_FUNC_SMBUS_I2C_BLOCK;
++}
++
++static const struct i2c_algorithm icc_i2c_algo = {
++ .smbus_xfer = &icc_i2c_smbus_xfer,
++ .functionality = &icc_i2c_functionality,
++};
++
++
++int icc_i2c_init(struct apcie_dev *sc)
++{
++ struct i2c_adapter *i2c;
++ int ret;
++
++ i2c = &sc->icc.i2c;
++ i2c->owner = THIS_MODULE;
++ i2c->algo = &icc_i2c_algo;
++ i2c->algo_data = NULL;
++ i2c->dev.parent = &sc->pdev->dev;
++ strlcpy(i2c->name, "icc", sizeof(i2c->name));
++ i2c_set_adapdata(i2c, sc);
++ ret = i2c_add_adapter(i2c);
++ if (ret < 0) {
++ sc_err("failed to add i2c adapter\n");
++ return ret;
++ }
++ return 0;
++}
++
++void icc_i2c_remove(struct apcie_dev *sc)
++{
++ i2c_del_adapter(&sc->icc.i2c);
++}
+diff --git a/drivers/ps4/ps4-apcie-icc.c b/drivers/ps4/ps4-apcie-icc.c
+new file mode 100644
+index 000000000000..2ee9885d7a1c
+--- /dev/null
++++ b/drivers/ps4/ps4-apcie-icc.c
+@@ -0,0 +1,602 @@
++#define DEBUG
++
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/wait.h>
++#include <linux/pci.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/fs.h>
++#include <linux/uaccess.h>
++#include <asm/ps4.h>
++#include "aeolia.h"
++
++/* There should normally be only one Aeolia device in a system. This allows
++ * other kernel code in unrelated subsystems to issue icc requests without
++ * having to get a reference to the device. */
++static struct apcie_dev *icc_sc;
++DEFINE_MUTEX(icc_mutex);
++
++/* The ICC message passing interface seems to be potentially designed to
++ * support multiple outstanding requests at once, but the original PS4 OS never
++ * does this, so we don't either. */
++
++#define BUF_FULL 0x7f0
++#define BUF_EMPTY 0x7f4
++#define HDR(x) (offsetof(struct icc_message_hdr, x))
++#define REQUEST (sc->icc.spm + APCIE_SPM_ICC_REQUEST)
++#define REPLY (sc->icc.spm + APCIE_SPM_ICC_REPLY)
++
++/* Seconds. Yes, some ICC requests can be slow. */
++int icc_timeout = 15;
++
++int icc_i2c_init(struct apcie_dev *sc);
++void icc_i2c_remove(struct apcie_dev *sc);
++int icc_pwrbutton_init(struct apcie_dev *sc);
++void icc_pwrbutton_remove(struct apcie_dev *sc);
++void icc_pwrbutton_trigger(struct apcie_dev *sc, int state);
++
++#define ICC_MAJOR 'I'
++
++ struct icc_cmd {
++ u8 major;
++ u16 minor;
++ void __user *data;
++ u16 length;
++ void __user *reply;
++ u16 reply_length;
++ };
++
++#define ICC_IOCTL_CMD _IOWR(ICC_MAJOR, 1, struct icc_cmd)
++
++static u16 checksum(const void *p, int length)
++{
++ const u8 *pp = p;
++ u16 sum = 0;
++ while (length--)
++ sum += *pp++;
++ return sum;
++}
++
++static void dump_message(struct apcie_dev *sc, int offset)
++{
++ int len;
++ struct icc_message_hdr hdr;
++ memcpy_fromio(&hdr, sc->icc.spm + offset, ICC_HDR_SIZE);
++
++ sc_err("icc: hdr: [%02x] %02x:%04x unk %x #%d len %d cksum 0x%x\n",
++ hdr.magic, hdr.major, hdr.minor, hdr.unknown, hdr.cookie,
++ hdr.length, hdr.checksum);
++ len = min(hdr.length - ICC_HDR_SIZE, ICC_MAX_PAYLOAD);
++ if (len > 0) {
++ sc_err("icc: data:");
++ while (len--)
++ printk(" %02x", ioread8(sc->icc.spm + (offset++) +
++ ICC_HDR_SIZE));
++ printk("\n");
++ }
++}
++
++static void handle_event(struct apcie_dev *sc, struct icc_message_hdr *msg)
++{
++ switch ((msg->major << 16) | msg->minor) {
++ case 0x088010:
++ icc_pwrbutton_trigger(sc, 1);
++ break;
++ case 0x088011:
++ icc_pwrbutton_trigger(sc, 0);
++ break;
++ default:
++ sc_err("icc: event arrived, not yet supported.\n");
++ dump_message(sc, APCIE_SPM_ICC_REPLY);
++ break;
++ }
++}
++
++static void handle_message(struct apcie_dev *sc)
++{
++ u32 rep_empty, rep_full;
++ int off, copy_size;
++ struct icc_message_hdr msg;
++
++ rep_empty = ioread32(REPLY + BUF_EMPTY);
++ rep_full = ioread32(REPLY + BUF_FULL);
++
++ if (rep_empty != 0 || rep_full != 1) {
++ sc_err("icc: reply buffer in bad state (%d, %d)\n",
++ rep_empty, rep_full);
++ return;
++ }
++
++ memcpy_fromio(&msg, REPLY, ICC_HDR_SIZE);
++
++ if (msg.minor & ICC_EVENT) {
++ if (msg.magic != ICC_EVENT_MAGIC) {
++ sc_err("icc: event has bad magic\n");
++ dump_message(sc, APCIE_SPM_ICC_REPLY);
++ return;
++ }
++ handle_event(sc, &msg);
++ } else if (msg.minor & ICC_REPLY) {
++ if (msg.magic != ICC_MAGIC) {
++ sc_err("icc: reply has bad magic\n");
++ dump_message(sc, APCIE_SPM_ICC_REPLY);
++ return;
++ }
++ spin_lock(&sc->icc.reply_lock);
++ if (!sc->icc.reply_pending) {
++ spin_unlock(&sc->icc.reply_lock);
++ sc_err("icc: unexpected reply\n");
++ dump_message(sc, APCIE_SPM_ICC_REPLY);
++ return;
++ }
++ if (msg.cookie != sc->icc.request.cookie) {
++ spin_unlock(&sc->icc.reply_lock);
++ sc_err("icc: reply has bad cookie %d\n", msg.cookie);
++ dump_message(sc, APCIE_SPM_ICC_REPLY);
++ return;
++ }
++ if (msg.length < ICC_HDR_SIZE || msg.length > ICC_MAX_SIZE) {
++ spin_unlock(&sc->icc.reply_lock);
++ sc_err("icc: reply has bad length %d\n", msg.length);
++ dump_message(sc, APCIE_SPM_ICC_REPLY);
++ return;
++ }
++ off = ICC_HDR_SIZE;
++ copy_size = min(sc->icc.reply_length,
++ (int)(msg.length - off));
++ memcpy_fromio(sc->icc.reply_buffer, REPLY + off, copy_size);
++ off += copy_size;
++ sc->icc.reply_extra_checksum = 0;
++ while (off < msg.length)
++ sc->icc.reply_extra_checksum += ioread8(REPLY + off++);
++ sc->icc.reply_pending = false;
++ sc->icc.reply_length = copy_size;
++ sc->icc.reply = msg;
++ spin_unlock(&sc->icc.reply_lock);
++ wake_up(&sc->icc.wq);
++ } else {
++ sc_err("icc: unknown message arrived\n");
++ dump_message(sc, APCIE_SPM_ICC_REPLY);
++ }
++}
++
++static irqreturn_t icc_interrupt(int irq, void *arg)
++{
++ struct apcie_dev *sc = arg;
++ u32 status;
++ u32 ret = IRQ_NONE;
++
++ do {
++ status = ioread32(sc->bar4 + APCIE_REG_ICC_STATUS);
++
++ if (status & APCIE_ICC_ACK) {
++ iowrite32(APCIE_ICC_ACK,
++ sc->bar4 + APCIE_REG_ICC_STATUS);
++ ret = IRQ_HANDLED;
++ }
++
++ if (status & APCIE_ICC_SEND) {
++ iowrite32(APCIE_ICC_SEND,
++ sc->bar4 + APCIE_REG_ICC_STATUS);
++ handle_message(sc);
++ iowrite32(0, REPLY + BUF_FULL);
++ iowrite32(1, REPLY + BUF_EMPTY);
++ iowrite32(APCIE_ICC_ACK,
++ sc->bar4 + APCIE_REG_ICC_DOORBELL);
++ ret = IRQ_HANDLED;
++ }
++ } while (status);
++
++ return ret;
++}
++
++static int _apcie_icc_cmd(struct apcie_dev *sc, u8 major, u16 minor, const void *data,
++ u16 length, void *reply, u16 reply_length, bool intr)
++{
++ int ret;
++ u32 req_empty, req_full;
++ u16 rep_checksum;
++
++ if (length > ICC_MAX_PAYLOAD)
++ return -E2BIG;
++
++ sc->icc.request.magic = ICC_MAGIC;
++ sc->icc.request.major = major;
++ sc->icc.request.minor = minor;
++ sc->icc.request.cookie++;
++ sc->icc.request.length = ICC_HDR_SIZE + length;
++ sc->icc.request.checksum = 0;
++ if (sc->icc.request.length < ICC_MIN_SIZE)
++ sc->icc.request.length = ICC_MIN_SIZE;
++
++ sc->icc.request.checksum = checksum(&sc->icc.request, ICC_HDR_SIZE);
++ sc->icc.request.checksum += checksum(data, length);
++ sc->icc.reply_buffer = reply;
++ sc->icc.reply_length = reply_length;
++
++ req_empty = ioread32(REQUEST + BUF_EMPTY);
++ req_full = ioread32(REQUEST + BUF_FULL);
++
++ if (req_empty != 1 || req_full != 0) {
++ sc_err("icc: request buffer is busy: empty=%d full=%d\n",
++ req_empty, req_full);
++ return -EIO;
++ }
++
++ iowrite32(0, REQUEST + BUF_EMPTY);
++
++ memcpy_toio(REQUEST, &sc->icc.request, ICC_HDR_SIZE);
++ memcpy_toio(REQUEST + ICC_HDR_SIZE, data, length);
++ if (length < ICC_MIN_PAYLOAD)
++ memset_io(REQUEST + ICC_HDR_SIZE + length, 0,
++ ICC_MIN_PAYLOAD - length);
++
++ iowrite32(1, REQUEST + BUF_FULL);
++
++ spin_lock_irq(&sc->icc.reply_lock);
++ sc->icc.reply_pending = true;
++ spin_unlock_irq(&sc->icc.reply_lock);
++
++ iowrite32(APCIE_ICC_SEND, sc->bar4 + APCIE_REG_ICC_DOORBELL);
++
++ if (intr)
++ ret = wait_event_interruptible_timeout(sc->icc.wq,
++ !sc->icc.reply_pending, HZ * icc_timeout);
++ else
++ ret = wait_event_timeout(sc->icc.wq,
++ !sc->icc.reply_pending, HZ * icc_timeout);
++
++ spin_lock_irq(&sc->icc.reply_lock);
++ sc->icc.reply_buffer = NULL;
++ if (ret < 0 || sc->icc.reply_pending) { /* interrupted or timed out */
++ sc->icc.reply_pending = false;
++ spin_unlock_irq(&sc->icc.reply_lock);
++ sc_err("icc: interrupted or timeout: ret = %d\n", ret);
++ return ret < 0 ? -EINTR : -ETIMEDOUT;
++ }
++ spin_unlock_irq(&sc->icc.reply_lock);
++
++ rep_checksum = sc->icc.reply.checksum;
++ sc->icc.reply.checksum = 0;
++ rep_checksum -= checksum(&sc->icc.reply, ICC_HDR_SIZE);
++ rep_checksum -= checksum(reply, sc->icc.reply_length);
++ rep_checksum -= sc->icc.reply_extra_checksum;
++
++ if (rep_checksum) {
++ sc_err("icc: checksum mismatch (diff: %x)\n", rep_checksum);
++ return -EIO;
++ }
++
++ if (sc->icc.reply.major != major ) {
++ sc_err("icc: major mismatch\n");
++ return -EIO;
++ }
++ if (sc->icc.reply.minor != (minor | ICC_REPLY) ) {
++ sc_err("icc: minor mismatch\n");
++ return -EIO;
++ }
++
++ return sc->icc.reply.length - ICC_HDR_SIZE;
++}
++
++int apcie_icc_cmd(u8 major, u16 minor, const void *data, u16 length,
++ void *reply, u16 reply_length)
++{
++ int ret;
++
++ mutex_lock(&icc_mutex);
++ if (!icc_sc) {
++ pr_err("icc: not ready\n");
++ return -EAGAIN;
++ }
++ ret = _apcie_icc_cmd(icc_sc, major, minor, data, length, reply, reply_length,
++ false);
++ mutex_unlock(&icc_mutex);
++ return ret;
++}
++EXPORT_SYMBOL_GPL(apcie_icc_cmd);
++
++void resetUsbPort(void)
++{
++ u8 off = 0, on = 1;
++ u8 resp[20];
++ int ret;
++
++ //Turn OFF Usb
++ ret = apcie_icc_cmd(5, 0x10, &off, sizeof(off), resp, 20);
++ printk("Turn OFF USB: ret=%d, reply %02x %02x %02x %02x", ret, resp[0], resp[1], resp[2], resp[3]);
++ if(ret < 0)
++ {
++ printk("Turn off USB failed!");
++ return;
++ }
++
++ //Turn ON Usb
++ ret = apcie_icc_cmd(5, 0x10, &on, sizeof(on), resp, 20);
++ printk("Turn ON USB: ret=%d, reply %02x %02x %02x %02x", ret, resp[0], resp[1], resp[2], resp[3]);
++ if(ret < 0)
++ {
++ printk("Turn on USB failed");
++ return;
++ }
++}
++
++void resetBtWlan(void)
++{
++ u8 off = 2, on = 3;
++ u8 resp[20];
++ int ret;
++
++
++ /* Get bt/wlan status */
++// ret = apcie_icc_cmd(5, 1, NULL, 0, resp, 20);
++// printk("BT/WLAN status: ret=%d, reply %02x %02x %02x %02x", ret, resp[0], resp[1], resp[2], resp[3]);
++
++ /** Turn off is done from linux-loader actually, if you want you can remove it from linux-loader and done it here **/
++
++ //Turn OFF bt/wlan
++/* ret = apcie_icc_cmd(5, 0, &off, sizeof(off), resp, 20);
++ printk("Turn OFF BT/WLAN: ret=%d, reply %02x %02x %02x %02x", ret, resp[0], resp[1], resp[2], resp[3]);
++ if(ret < 0)
++ {
++ printk("Turn off bt/wlan failed!");
++ return;
++ }
++*/
++
++ //Turn ON bt/wlan
++ ret = apcie_icc_cmd(5, 0, &on, sizeof(on), resp, 20);
++ printk("Turn ON BT/WLAN: ret=%d, reply %02x %02x %02x %02x", ret, resp[0], resp[1], resp[2], resp[3]);
++ if(ret < 0)
++ {
++ printk("Turn on bt/wlan failed");
++ return;
++ }
++}
++
++void do_icc_init(void) {
++ u8 svc = 0x10;
++ u8 reply[0x30];
++ static const u8 led_config[] = {
++ 3, 1, 0, 0,
++ 0x10, 1, /* Blue: on */
++ 2, 0xff, 2, 1, 0x00,
++ 0x11, 1, /* White: off */
++ 2, 0x00, 2, 1, 0x00,
++ 0x02, 3, /* Orange: delay and pulse, loop forever */
++ 1, 0x00, 4, 1, 0xbf,
++ 2, 0xff, 5, 1, 0xff,
++ 2, 0x00, 5, 1, 0xff,
++ };
++ int ret;
++ // test: get FW version
++ ret = apcie_icc_cmd(2, 6, NULL, 0, reply, 0x30);
++ printk("ret=%d, reply %02x %02x %02x %02x %02x %02x %02x %02x\n", ret,
++ reply[0], reply[1], reply[2], reply[3],
++ reply[4], reply[5], reply[6], reply[7]);
++ ret = apcie_icc_cmd(1, 0, &svc, 1, reply, 0x30);
++ printk("ret=%d, reply %02x %02x %02x %02x %02x %02x %02x %02x\n", ret,
++ reply[0], reply[1], reply[2], reply[3],
++ reply[4], reply[5], reply[6], reply[7]);
++
++ /* Set the LED to something nice */
++ ret = apcie_icc_cmd(9, 0x20, led_config, ARRAY_SIZE(led_config), reply, 0x30);
++ printk("ret=%d, reply %02x %02x %02x %02x %02x %02x %02x %02x\n", ret,
++ reply[0], reply[1], reply[2], reply[3],
++ reply[4], reply[5], reply[6], reply[7]);
++}
++
++static void icc_shutdown(void)
++{
++ uint8_t command[] = {
++ 0, 0, 2, 0, 1, 0
++ };
++ if (apcie_status() != 1)
++ return;
++ apcie_icc_cmd(4, 1, command, sizeof(command), NULL, 0);
++ mdelay(3000);
++ WARN_ON(1);
++}
++
++void icc_reboot(void)
++{
++ uint8_t command[] = {
++ 0, 1, 2, 0, 1, 0
++ };
++ if (apcie_status() != 1)
++ return;
++ apcie_icc_cmd(4, 1, command, sizeof(command), NULL, 0);
++ mdelay(3000);
++ WARN_ON(1);
++}
++
++static void *ioctl_tmp_buf = NULL;
++
++ static long icc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++ {
++ int ret;
++ void __user *uap = (void __user *)arg;
++ switch (cmd) {
++ case ICC_IOCTL_CMD: {
++ struct icc_cmd cmd;
++ int reply_len;
++ ret = copy_from_user(&cmd, uap, sizeof(cmd));
++ if (ret) {
++ ret = -EFAULT;
++ break;
++ }
++ ret = copy_from_user(ioctl_tmp_buf, cmd.data, cmd.length);
++ if (ret) {
++ ret = -EFAULT;
++ break;
++ }
++ reply_len = apcie_icc_cmd(cmd.major, cmd.minor, ioctl_tmp_buf,
++ cmd.length, ioctl_tmp_buf, cmd.reply_length);
++ if (reply_len < 0) {
++ ret = reply_len;
++ break;
++ }
++ ret = copy_to_user(cmd.reply, ioctl_tmp_buf, cmd.reply_length);
++ if (ret) {
++ ret = -EFAULT;
++ break;
++ }
++ ret = reply_len;
++ } break;
++ default:
++ ret = -ENOENT;
++ break;
++ }
++ return ret;
++ }
++
++ static const struct file_operations icc_fops = {
++ .owner = THIS_MODULE,
++ .unlocked_ioctl = icc_ioctl,
++ };
++
++
++int apcie_icc_init(struct apcie_dev *sc)
++{
++ int ret;
++ unsigned int mem_devfn = PCI_DEVFN(PCI_SLOT(sc->pdev->devfn), AEOLIA_FUNC_ID_MEM);
++ struct pci_dev *mem_dev;
++ u32 req_empty, req_full;
++
++ /* ICC makes use of a segment of SPM memory, available via a different
++ * PCI function in Aeolia, so we need to get a handle to it. */
++ mem_dev = pci_get_slot(sc->pdev->bus, mem_devfn);
++ if (!mem_dev) {
++ sc_err("icc: could not get handle to mem device\n");
++ return -ENODEV;
++ }
++
++ if (!request_mem_region(pci_resource_start(sc->pdev, 4) +
++ APCIE_RGN_ICC_BASE, APCIE_RGN_ICC_SIZE,
++ "apcie.icc")) {
++ sc_err("icc: failed to request ICC register region\n");
++ return -EBUSY;
++ }
++
++ sc->icc.spm_base = pci_resource_start(mem_dev, 5) + APCIE_SPM_ICC_BASE;
++ if (!request_mem_region(sc->icc.spm_base, APCIE_SPM_ICC_SIZE,
++ "spm.icc")) {
++ sc_err("icc: failed to request ICC SPM region\n");
++ ret = -EBUSY;
++ goto release_icc;
++ }
++
++ sc->icc.spm = ioremap(sc->icc.spm_base, APCIE_SPM_ICC_SIZE);
++ if (!sc->icc.spm) {
++ sc_err("icc: failed to map ICC portion of SPM\n");
++ ret = -EIO;
++ goto release_spm;
++ }
++
++ spin_lock_init(&sc->icc.reply_lock);
++ init_waitqueue_head(&sc->icc.wq);
++
++ /* Clear flags */
++ iowrite32(APCIE_ICC_SEND | APCIE_ICC_ACK,
++ sc->bar4 + APCIE_REG_ICC_STATUS);
++
++ ret = request_irq(apcie_irqnum(sc, APCIE_SUBFUNC_ICC),
++ icc_interrupt, IRQF_SHARED, "icc", sc);
++ if (ret) {
++ sc_err("icc: could not request IRQ: %d\n", ret);
++ goto iounmap;
++ }
++
++ req_empty = ioread32(REQUEST + BUF_EMPTY);
++ req_full = ioread32(REQUEST + BUF_FULL);
++
++ if (req_empty != 1 || req_full != 0) {
++ sc_err("icc: request buffer is busy: empty=%d full=%d\n",
++ req_empty, req_full);
++ ret = -EIO;
++ goto free_irq;
++ }
++
++ mutex_lock(&icc_mutex);
++ icc_sc = sc;
++
++ /* Enable IRQs */
++ iowrite32(APCIE_ICC_SEND | APCIE_ICC_ACK,
++ sc->bar4 + APCIE_REG_ICC_IRQ_MASK);
++ mutex_unlock(&icc_mutex);
++
++ ret = icc_i2c_init(sc);
++ if (ret) {
++ sc_err("icc: i2c init failed: %d\n", ret);
++ goto unassign_global;
++ }
++
++ resetBtWlan();
++// resetUsbPort();
++
++ ret = icc_pwrbutton_init(sc);
++ /* Not fatal */
++ if (ret)
++ sc_err("icc: pwrbutton init failed: %d\n", ret);
++
++ do_icc_init();
++ pm_power_off = &icc_shutdown;
++
++ ioctl_tmp_buf = kzalloc(1 << 16, GFP_KERNEL);
++ if (!ioctl_tmp_buf) {
++ sc_err("icc: alloc ioctl_tmp_buf failed\n");
++ goto done;
++ }
++ ret = register_chrdev(ICC_MAJOR, "icc", &icc_fops);
++ if (ret) {
++ sc_err("icc: register_chrdev failed: %d\n", ret);
++ goto done;
++ }
++ done:
++
++ return 0;
++
++unassign_global:
++ mutex_lock(&icc_mutex);
++ iowrite32(0, sc->bar4 + APCIE_REG_ICC_IRQ_MASK);
++ icc_sc = NULL;
++ mutex_unlock(&icc_mutex);
++free_irq:
++ free_irq(apcie_irqnum(sc, APCIE_SUBFUNC_ICC), sc);
++iounmap:
++ iounmap(sc->icc.spm);
++release_spm:
++ release_mem_region(sc->icc.spm_base, APCIE_SPM_ICC_SIZE);
++release_icc:
++ release_mem_region(pci_resource_start(sc->pdev, 4) +
++ APCIE_RGN_ICC_BASE, APCIE_RGN_ICC_SIZE);
++ return ret;
++}
++
++void apcie_icc_remove(struct apcie_dev *sc)
++{
++ sc_err("apcie_icc_remove: shouldn't normally be called\n");
++ pm_power_off = NULL;
++ icc_pwrbutton_remove(sc);
++ icc_i2c_remove(sc);
++ mutex_lock(&icc_mutex);
++ iowrite32(0, sc->bar4 + APCIE_REG_ICC_IRQ_MASK);
++ icc_sc = NULL;
++ mutex_unlock(&icc_mutex);
++ free_irq(apcie_irqnum(sc, APCIE_SUBFUNC_ICC), sc);
++ iounmap(sc->icc.spm);
++ release_mem_region(sc->icc.spm_base, APCIE_SPM_ICC_SIZE);
++ release_mem_region(pci_resource_start(sc->pdev, 4) +
++ APCIE_RGN_ICC_BASE, APCIE_RGN_ICC_SIZE);
++}
++
++#ifdef CONFIG_PM
++void apcie_icc_suspend(struct apcie_dev *sc, pm_message_t state)
++{
++}
++
++void apcie_icc_resume(struct apcie_dev *sc)
++{
++}
++#endif
+diff --git a/drivers/ps4/ps4-apcie-pwrbutton.c b/drivers/ps4/ps4-apcie-pwrbutton.c
+new file mode 100644
+index 000000000000..d695221703b5
+--- /dev/null
++++ b/drivers/ps4/ps4-apcie-pwrbutton.c
+@@ -0,0 +1,69 @@
++#include <linux/input.h>
++#include "aeolia.h"
++
++void icc_pwrbutton_trigger(struct apcie_dev *sc, int state)
++{
++ if (sc->icc.pwrbutton_dev) {
++ input_report_key(sc->icc.pwrbutton_dev, KEY_POWER, state ? 1 : 0);
++ input_sync(sc->icc.pwrbutton_dev);
++ }
++}
++
++int icc_pwrbutton_init(struct apcie_dev *sc)
++{
++ int ret = 0;
++ u16 button;
++ struct input_dev *dev;
++
++ dev = input_allocate_device();
++ if (!dev) {
++ sc_err("%s: Not enough memory.\n", __func__);
++ return -ENOMEM;
++ }
++
++ set_bit(EV_KEY, dev->evbit);
++ set_bit(KEY_POWER, dev->keybit);
++
++ dev->name = "Power Button";
++ dev->id.bustype = BUS_HOST;
++
++ /* this makes the button look like an acpi power button
++ * no clue whether anyone relies on that though */
++ dev->id.product = 0x02;
++ dev->phys = "LNXPWRBN/button/input0";
++
++ dev->dev.parent = &sc->pdev->dev;
++ ret = input_register_device(dev);
++ if (ret) {
++ sc_err("%s: Failed to register device\n", __func__);
++ input_free_device(dev);
++ return ret;
++ }
++
++ sc->icc.pwrbutton_dev = dev;
++
++ // enable power button notifications
++ button = 0x100;
++ ret = apcie_icc_cmd(8, 1, &button, sizeof(button), NULL, 0);
++ if (ret < 0) {
++ sc_info("%s: Failed to enable power notifications (%d)\n",
++ __func__, ret);
++ }
++
++ // enable reset button notifications (?)
++ button = 0x102;
++ ret = apcie_icc_cmd(8, 1, &button, sizeof(button), NULL, 0);
++ if (ret < 0) {
++ sc_info("%s: Failed to enable reset notifications (%d)\n",
++ __func__, ret);
++ }
++
++ return 0;
++}
++
++void icc_pwrbutton_remove(struct apcie_dev *sc)
++{
++ if (sc->icc.pwrbutton_dev)
++ input_free_device(sc->icc.pwrbutton_dev);
++ sc->icc.pwrbutton_dev = NULL;
++}
+diff --git a/drivers/ps4/ps4-apcie-uart.c b/drivers/ps4/ps4-apcie-uart.c
+new file mode 100644
+index 000000000000..6dd6dc195735
+--- /dev/null
++++ b/drivers/ps4/ps4-apcie-uart.c
+@@ -0,0 +1,67 @@
++#include <linux/serial_8250.h>
++#include <linux/serial_core.h>
++#include <linux/serial_reg.h>
++
++#include "aeolia.h"
++
++void apcie_uart_remove(struct apcie_dev *sc);
++
++int apcie_uart_init(struct apcie_dev *sc)
++{
++ int i;
++ struct uart_8250_port uart;
++
++ for (i = 0; i < APCIE_NR_UARTS; i++) {
++ sc->serial_line[i] = -1;
++ }
++
++ for (i = 0; i < APCIE_NR_UARTS; i++) {
++ uint32_t off = APCIE_RGN_UART_BASE + (i << 12);
++ memset(&uart, 0, sizeof(uart));
++ uart.port.irq = apcie_irqnum(sc, APCIE_SUBFUNC_UART0 + i);
++ uart.port.uartclk = 58500000;
++ uart.port.flags = UPF_SHARE_IRQ;
++ uart.port.iotype = UPIO_MEM32;
++ uart.port.mapbase = pci_resource_start(sc->pdev, 4) + off;
++ uart.port.membase = sc->bar4 + off;
++ uart.port.regshift = 2;
++ uart.port.dev = &sc->pdev->dev;
++
++ sc->serial_line[i] = serial8250_register_8250_port(&uart);
++ if (sc->serial_line[i] < 0) {
++ sc_err("Failed to register serial port %d\n", i);
++ apcie_uart_remove(sc);
++ return -EIO;
++ }
++ }
++ return 0;
++}
++
++void apcie_uart_remove(struct apcie_dev *sc)
++{
++ int i;
++ for (i = 0; i < APCIE_NR_UARTS; i++) {
++ if (sc->serial_line[i] >= 0) {
++ serial8250_unregister_port(sc->serial_line[i]);
++ sc->serial_line[i] = -1;
++ }
++ }
++}
++
++#ifdef CONFIG_PM
++void apcie_uart_suspend(struct apcie_dev *sc, pm_message_t state)
++{
++ int i;
++ for (i = 0; i < APCIE_NR_UARTS; i++)
++ if (sc->serial_line[i] >= 0)
++ serial8250_suspend_port(sc->serial_line[i]);
++}
++
++void apcie_uart_resume(struct apcie_dev *sc)
++{
++ int i;
++ for (i = 0; i < APCIE_NR_UARTS; i++)
++ if (sc->serial_line[i] >= 0)
++ serial8250_resume_port(sc->serial_line[i]);
++}
++#endif
+diff --git a/drivers/ps4/ps4-apcie.c b/drivers/ps4/ps4-apcie.c
+new file mode 100644
+index 000000000000..d5e87d1ee74e
+--- /dev/null
++++ b/drivers/ps4/ps4-apcie.c
+@@ -0,0 +1,560 @@
++#define DEBUG
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/irq.h>
++#include <linux/irqchip.h>
++#include <linux/irqdomain.h>
++#include <linux/msi.h>
++#include <asm/apic.h>
++#include <asm/irqdomain.h>
++#include <asm/irq_remapping.h>
++
++#include <asm/msi.h>
++
++#include <asm/ps4.h>
++
++#include "aeolia.h"
++
++/* #define QEMU_HACK_NO_IOMMU */
++
++/* Number of implemented MSI registers per function */
++static const int subfuncs_per_func[AEOLIA_NUM_FUNCS] = {
++ 4, 4, 4, 4, 31, 2, 2, 4
++};
++
++static inline u32 glue_read32(struct apcie_dev *sc, u32 offset) {
++ return ioread32(sc->bar4 + offset);
++}
++
++static inline void glue_write32(struct apcie_dev *sc, u32 offset, u32 value) {
++ iowrite32(value, sc->bar4 + offset);
++}
++
++static inline void glue_set_region(struct apcie_dev *sc, u32 func, u32 bar,
++ u32 base, u32 mask) {
++ glue_write32(sc, APCIE_REG_BAR_MASK(func, bar), mask);
++ glue_write32(sc, APCIE_REG_BAR_ADDR(func, bar), base);
++}
++
++static inline void glue_set_mask(struct apcie_dev *sc, u32 offset, u32 mask) {
++ void __iomem *ptr = sc->bar4 + offset;
++ iowrite32(ioread32(ptr) | mask, ptr);
++}
++
++static inline void glue_clear_mask(struct apcie_dev *sc, u32 offset, u32 mask) {
++ void __iomem *ptr = sc->bar4 + offset;
++ iowrite32(ioread32(ptr) & ~mask, ptr);
++}
++
++static inline void glue_mask_and_set(struct apcie_dev *sc, u32 offset, u32 mask, u32 set) {
++ void __iomem *ptr = sc->bar4 + offset;
++ iowrite32((ioread32(ptr) & ~mask) | set, ptr);
++}
++
++static void apcie_config_msi(struct apcie_dev *sc, u32 func, u32 subfunc,
++ u32 addr, u32 data) {
++ u32 offset;
++
++ sc_dbg("apcie_config_msi: func: %u, subfunc: %u, addr %08x data: 0x%08x (%u)\n",
++ func, subfunc, addr, data, data);
++
++ glue_clear_mask(sc, APCIE_REG_MSI_CONTROL, APCIE_REG_MSI_CONTROL_ENABLE);
++ /* Unknown */
++ glue_write32(sc, APCIE_REG_MSI(0x8), 0xffffffff);
++ /* Unknown */
++ glue_write32(sc, APCIE_REG_MSI(0xc + (func << 2)), 0xB7FFFF00 + func * 16);
++ glue_write32(sc, APCIE_REG_MSI_ADDR(func), addr);
++ /* Unknown */
++ glue_write32(sc, APCIE_REG_MSI(0xcc + (func << 2)), 0);
++ glue_write32(sc, APCIE_REG_MSI_DATA_HI(func), data & 0xffe0);
++
++ if (func < 4) {
++ /* First 4 functions have 4 IRQs/subfuncs each */
++ offset = (func << 4) | (subfunc << 2);
++ } else if (func == 4) {
++ /* Function 4 gets 24 consecutive slots,
++ * then 7 more at the end. */
++ if (subfunc < 24)
++ offset = 0x40 + (subfunc << 2);
++ else
++ offset = 0xe0 + ((subfunc - 24) << 2);
++ } else {
++ offset = 0xa0 + ((func - 5) << 4) + (subfunc << 2);
++ }
++ glue_write32(sc, APCIE_REG_MSI_DATA_LO(offset), data & 0x1f);
++
++ if (func == AEOLIA_FUNC_ID_PCIE)
++ glue_set_mask(sc, APCIE_REG_MSI_MASK(func), APCIE_REG_MSI_MASK_FUNC4);
++ else
++ glue_set_mask(sc, APCIE_REG_MSI_MASK(func), APCIE_REG_MSI_MASK_FUNC);
++
++ glue_set_mask(sc, APCIE_REG_MSI_CONTROL, APCIE_REG_MSI_CONTROL_ENABLE);
++}
++
++static void apcie_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
++{
++ struct apcie_dev *sc = data->chip_data;
++ u32 func = data->hwirq >> 8;
++ u32 subfunc = data->hwirq & 0xff;
++
++ /* Linux likes to unconfigure MSIs like this, but since we share the
++ * address between subfunctions, we can't do that. The IRQ should be
++ * masked via apcie_msi_mask anyway, so just do nothing. */
++ if (!msg->address_lo) {
++ return;
++ }
++
++ sc_dbg("apcie_msi_write_msg(%08x, %08x) mask=0x%x irq=%d hwirq=0x%lx %p\n",
++ msg->address_lo, msg->data, data->mask, data->irq, data->hwirq, sc);
++
++ if (subfunc == 0xff) {
++ int i;
++ for (i = 0; i < subfuncs_per_func[func]; i++)
++ apcie_config_msi(sc, func, i, msg->address_lo, msg->data);
++ } else {
++ apcie_config_msi(sc, func, subfunc, msg->address_lo, msg->data);
++ }
++}
++
++static void apcie_msi_unmask(struct irq_data *data)
++{
++ struct apcie_dev *sc = data->chip_data;
++ u32 func = data->hwirq >> 8;
++
++ glue_set_mask(sc, APCIE_REG_MSI_MASK(func), data->mask);
++}
++
++static void apcie_msi_mask(struct irq_data *data)
++{
++ struct apcie_dev *sc = data->chip_data;
++ u32 func = data->hwirq >> 8;
++
++ glue_clear_mask(sc, APCIE_REG_MSI_MASK(func), data->mask);
++}
++
++static void apcie_msi_calc_mask(struct irq_data *data) {
++ u32 func = data->hwirq >> 8;
++ u32 subfunc = data->hwirq & 0xff;
++
++ if (subfunc == 0xff) {
++ data->mask = (1 << subfuncs_per_func[func]) - 1;
++ } else {
++ data->mask = 1 << subfunc;
++ }
++}
++
++static void apcie_irq_msi_compose_msg(struct irq_data *data,
++ struct msi_msg *msg)
++{
++ __irq_msi_compose_msg(irqd_cfg(data), msg, false);
++}
++
++
++static struct irq_chip apcie_msi_controller = {
++ .name = "Aeolia-MSI",
++ .irq_unmask = apcie_msi_unmask,
++ .irq_mask = apcie_msi_mask,
++ .irq_ack = irq_chip_ack_parent,
++ .irq_set_affinity = msi_domain_set_affinity,
++ .irq_retrigger = irq_chip_retrigger_hierarchy,
++ .irq_compose_msi_msg = apcie_irq_msi_compose_msg,
++ .irq_write_msi_msg = apcie_msi_write_msg,
++ .flags = IRQCHIP_SKIP_SET_WAKE,
++};
++
++static irq_hw_number_t apcie_msi_get_hwirq(struct msi_domain_info *info,
++ msi_alloc_info_t *arg)
++{
++ return arg->hwirq;
++}
++
++static int apcie_msi_init(struct irq_domain *domain,
++ struct msi_domain_info *info, unsigned int virq,
++ irq_hw_number_t hwirq, msi_alloc_info_t *arg)
++{
++ struct irq_data *data;
++ pr_devel("apcie_msi_init(%p, %p, %d, 0x%lx, %p)\n", domain, info, virq, hwirq, arg);
++
++ data = irq_domain_get_irq_data(domain, virq);
++ irq_domain_set_info(domain, virq, hwirq, info->chip, info->chip_data,
++ handle_edge_irq, NULL, "edge");
++ apcie_msi_calc_mask(data);
++ return 0;
++}
++
++static void apcie_msi_free(struct irq_domain *domain,
++ struct msi_domain_info *info, unsigned int virq)
++{
++ pr_devel("apcie_msi_free(%d)\n", virq);
++}
++
++int apcie_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
++ msi_alloc_info_t *arg)
++{
++ init_irq_alloc_info(arg, NULL);
++
++ arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
++ arg->flags |= MSI_FLAG_MULTI_PCI_MSI;
++
++ return 0;
++}
++
++static struct msi_domain_ops apcie_msi_domain_ops = {
++ .get_hwirq = apcie_msi_get_hwirq,
++ .msi_prepare = apcie_msi_prepare,
++ .msi_init = apcie_msi_init,
++ .msi_free = apcie_msi_free,
++};
++
++static struct msi_domain_info apcie_msi_domain_info = {
++ .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS,
++ .ops = &apcie_msi_domain_ops,
++ .chip = &apcie_msi_controller,
++ .handler = handle_edge_irq,
++ .handler_name = "edge"
++};
++
++static struct irq_domain *apcie_create_irq_domain(struct apcie_dev *sc)
++{
++ struct irq_domain *domain;
++ struct fwnode_handle *fn;
++
++ sc_dbg("apcie_create_irq_domain\n");
++ if (x86_vector_domain == NULL)
++ return NULL;
++
++ apcie_msi_domain_info.chip_data = (void *)sc;
++ apcie_msi_domain_info.flags |= MSI_FLAG_MULTI_PCI_MSI;
++ apcie_msi_controller.name = "IR-Aeolia-MSI";
++
++ fn = irq_domain_alloc_named_fwnode(apcie_msi_controller.name);
++ if (!fn)
++ return NULL;
++ domain = pci_msi_create_irq_domain(fn, &apcie_msi_domain_info,
++ x86_vector_domain);
++
++ if (!domain) {
++ irq_domain_free_fwnode(fn);
++ pr_warn("Failed to initialize IR-Aeolia-MSI irqdomain.\n");
++ } else {
++ domain->flags |= IRQ_DOMAIN_MSI_NOMASK_QUIRK;
++ }
++
++ return domain;
++}
++
++static int apcie_is_compatible_device(struct pci_dev *dev)
++{
++ if (!dev || dev->vendor != PCI_VENDOR_ID_SONY) {
++ return 0;
++ }
++ return (dev->device == PCI_DEVICE_ID_SONY_AEOLIA_PCIE ||
++ dev->device == PCI_DEVICE_ID_SONY_BELIZE_PCIE ||
++ dev->device == PCI_DEVICE_ID_SONY_BAIKAL_PCIE);
++}
++
++int apcie_assign_irqs(struct pci_dev *dev, int nvec)
++{
++ int ret;
++ unsigned int sc_devfn;
++ struct pci_dev *sc_dev;
++ struct apcie_dev *sc;
++ struct irq_alloc_info info;
++
++ sc_devfn = (dev->devfn & ~7) | AEOLIA_FUNC_ID_PCIE;
++ sc_dev = pci_get_slot(dev->bus, sc_devfn);
++
++ if (!apcie_is_compatible_device(sc_dev)) {
++ dev_err(&dev->dev, "apcie: this is not an Aeolia device\n");
++ ret = -ENODEV;
++ goto fail;
++ }
++ sc = pci_get_drvdata(sc_dev);
++ if (!sc) {
++ dev_err(&dev->dev, "apcie: not ready yet, cannot assign IRQs\n");
++ ret = -ENODEV;
++ goto fail;
++ }
++
++ init_irq_alloc_info(&info, NULL);
++ info.type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
++ /* IRQs "come from" function 4 as far as the IOMMU/system see */
++ //info.msi_dev = sc->pdev;
++ /* Our hwirq number is function << 8 plus subfunction.
++ * Subfunction is usually 0 and implicitly increments per hwirq,
++ * but can also be 0xff to indicate that this is a shared IRQ. */
++ //https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=3b9c1d377d67072d1d8a2373b4969103cca00dab
++ info.hwirq = PCI_FUNC(dev->devfn) << 8;
++
++ dev_dbg(&dev->dev, "apcie_assign_irqs(%d)\n", nvec);
++
++#ifndef QEMU_HACK_NO_IOMMU
++ info.flags = X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
++ if (!(apcie_msi_domain_info.flags & MSI_FLAG_MULTI_PCI_MSI)) {
++ nvec = 1;
++ info.hwirq |= 0xff; /* Shared IRQ for all subfunctions */
++ }
++#endif
++
++ ret = irq_domain_alloc_irqs(sc->irqdomain, nvec, NUMA_NO_NODE, &info);
++ if (ret >= 0) {
++ dev->irq = ret;
++ ret = nvec;
++ }
++
++fail:
++ dev_dbg(&dev->dev, "apcie_assign_irqs returning %d\n", ret);
++ if (sc_dev)
++ pci_dev_put(sc_dev);
++ return ret;
++}
++EXPORT_SYMBOL(apcie_assign_irqs);
++
++void apcie_free_irqs(unsigned int virq, unsigned int nr_irqs)
++{
++ irq_domain_free_irqs(virq, nr_irqs);
++}
++EXPORT_SYMBOL(apcie_free_irqs);
++
++static void apcie_glue_remove(struct apcie_dev *sc);
++
++static int apcie_glue_init(struct apcie_dev *sc)
++{
++ int i;
++
++ sc_info("apcie glue probe\n");
++
++ if (!request_mem_region(pci_resource_start(sc->pdev, 4) +
++ APCIE_RGN_PCIE_BASE, APCIE_RGN_PCIE_SIZE,
++ "apcie.glue")) {
++ sc_err("Failed to request pcie region\n");
++ return -EBUSY;
++
++ }
++
++ if (!request_mem_region(pci_resource_start(sc->pdev, 2) +
++ APCIE_RGN_CHIPID_BASE, APCIE_RGN_CHIPID_SIZE,
++ "apcie.chipid")) {
++ sc_err("Failed to request chipid region\n");
++ release_mem_region(pci_resource_start(sc->pdev, 4) +
++ APCIE_RGN_PCIE_BASE, APCIE_RGN_PCIE_SIZE);
++ return -EBUSY;
++ }
++
++ glue_set_region(sc, AEOLIA_FUNC_ID_PCIE, 2, 0xbf018000, 0x7fff);
++
++ sc_info("Aeolia chip revision: %08x:%08x:%08x\n",
++ ioread32(sc->bar2 + APCIE_REG_CHIPID_0),
++ ioread32(sc->bar2 + APCIE_REG_CHIPID_1),
++ ioread32(sc->bar2 + APCIE_REG_CHIPREV));
++
++ /* Mask all MSIs first, to avoid spurious IRQs */
++ for (i = 0; i < AEOLIA_NUM_FUNCS; i++) {
++ glue_write32(sc, APCIE_REG_MSI_MASK(i), 0);
++ glue_write32(sc, APCIE_REG_MSI_ADDR(i), 0);
++ glue_write32(sc, APCIE_REG_MSI_DATA_HI(i), 0);
++ }
++
++ for (i = 0; i < 0xfc; i += 4)
++ glue_write32(sc, APCIE_REG_MSI_DATA_LO(i), 0);
++
++ glue_set_region(sc, AEOLIA_FUNC_ID_GBE, 0, 0xbfa00000, 0x3fff);
++ glue_set_region(sc, AEOLIA_FUNC_ID_AHCI, 5, 0xbfa04000, 0xfff);
++ glue_set_region(sc, AEOLIA_FUNC_ID_SDHCI, 0, 0xbfa80000, 0xfff);
++ glue_set_region(sc, AEOLIA_FUNC_ID_SDHCI, 1, 0, 0);
++ glue_set_region(sc, AEOLIA_FUNC_ID_DMAC, 0, 0xbfa05000, 0xfff);
++ glue_set_region(sc, AEOLIA_FUNC_ID_DMAC, 1, 0, 0);
++ glue_set_region(sc, AEOLIA_FUNC_ID_DMAC, 2, 0xbfa06000, 0xfff);
++ glue_set_region(sc, AEOLIA_FUNC_ID_DMAC, 3, 0, 0);
++ glue_set_region(sc, AEOLIA_FUNC_ID_MEM, 2, 0xc0000000, 0x3fffffff);
++ glue_set_region(sc, AEOLIA_FUNC_ID_MEM, 3, 0, 0);
++ glue_set_region(sc, AEOLIA_FUNC_ID_XHCI, 0, 0xbf400000, 0x1fffff);
++ glue_set_region(sc, AEOLIA_FUNC_ID_XHCI, 1, 0, 0);
++ glue_set_region(sc, AEOLIA_FUNC_ID_XHCI, 2, 0xbf600000, 0x1fffff);
++ glue_set_region(sc, AEOLIA_FUNC_ID_XHCI, 3, 0, 0);
++ glue_set_region(sc, AEOLIA_FUNC_ID_XHCI, 4, 0xbf800000, 0x1fffff);
++ glue_set_region(sc, AEOLIA_FUNC_ID_XHCI, 5, 0, 0);
++
++ sc->irqdomain = apcie_create_irq_domain(sc);
++ if (!sc->irqdomain) {
++ sc_err("Failed to create IRQ domain");
++ apcie_glue_remove(sc);
++ return -EIO;
++ }
++ sc->nvec = apcie_assign_irqs(sc->pdev, APCIE_NUM_SUBFUNC);
++ if (sc->nvec <= 0) {
++ sc_err("Failed to assign IRQs");
++ apcie_glue_remove(sc);
++ return -EIO;
++ }
++ sc_dbg("dev->irq=%d\n", sc->pdev->irq);
++
++ return 0;
++}
++
++static void apcie_glue_remove(struct apcie_dev *sc) {
++ sc_info("apcie glue remove\n");
++
++ if (sc->nvec > 0) {
++ apcie_free_irqs(sc->pdev->irq, sc->nvec);
++ sc->nvec = 0;
++ }
++ if (sc->irqdomain) {
++ irq_domain_remove(sc->irqdomain);
++ sc->irqdomain = NULL;
++ }
++ release_mem_region(pci_resource_start(sc->pdev, 2) +
++ APCIE_RGN_CHIPID_BASE, APCIE_RGN_CHIPID_SIZE);
++ release_mem_region(pci_resource_start(sc->pdev, 4) +
++ APCIE_RGN_PCIE_BASE, APCIE_RGN_PCIE_SIZE);
++}
++
++#ifdef CONFIG_PM
++static int apcie_glue_suspend(struct apcie_dev *sc, pm_message_t state) {
++ return 0;
++}
++
++static int apcie_glue_resume(struct apcie_dev *sc) {
++ return 0;
++}
++#endif
++
++
++int apcie_uart_init(struct apcie_dev *sc);
++int apcie_icc_init(struct apcie_dev *sc);
++void apcie_uart_remove(struct apcie_dev *sc);
++void apcie_icc_remove(struct apcie_dev *sc);
++#ifdef CONFIG_PM
++void apcie_uart_suspend(struct apcie_dev *sc, pm_message_t state);
++void apcie_icc_suspend(struct apcie_dev *sc, pm_message_t state);
++void apcie_uart_resume(struct apcie_dev *sc);
++void apcie_icc_resume(struct apcie_dev *sc);
++#endif
++
++/* From arch/x86/platform/ps4/ps4.c */
++extern bool apcie_initialized;
++
++static int apcie_probe(struct pci_dev *dev, const struct pci_device_id *id) {
++ struct apcie_dev *sc;
++ int ret;
++
++ dev_dbg(&dev->dev, "apcie_probe()\n");
++
++ ret = pci_enable_device(dev);
++ if (ret) {
++ dev_err(&dev->dev,
++ "apcie_probe(): pci_enable_device failed: %d\n", ret);
++ return ret;
++ }
++
++ sc = kzalloc(sizeof(*sc), GFP_KERNEL);
++ if (!sc) {
++ dev_err(&dev->dev, "apcie_probe(): alloc sc failed\n");
++ ret = -ENOMEM;
++ goto disable_dev;
++ }
++ sc->pdev = dev;
++ pci_set_drvdata(dev, sc);
++
++ // eMMC ... unused?
++ sc->bar0 = pci_ioremap_bar(dev, 0);
++ // pervasive 0
++ sc->bar2 = pci_ioremap_bar(dev, 2);
++ // pervasive 1 - misc peripherals
++ sc->bar4 = pci_ioremap_bar(dev, 4);
++
++ if (!sc->bar0 || !sc->bar2 || !sc->bar4) {
++ sc_err("failed to map some BARs, bailing out\n");
++ ret = -EIO;
++ goto free_bars;
++ }
++
++ if ((ret = apcie_glue_init(sc)) < 0)
++ goto free_bars;
++ if ((ret = apcie_uart_init(sc)) < 0)
++ goto remove_glue;
++ if ((ret = apcie_icc_init(sc)) < 0)
++ goto remove_uart;
++
++ apcie_initialized = true;
++ return 0;
++
++remove_uart:
++ apcie_uart_remove(sc);
++remove_glue:
++ apcie_glue_remove(sc);
++free_bars:
++ if (sc->bar0)
++ iounmap(sc->bar0);
++ if (sc->bar2)
++ iounmap(sc->bar2);
++ if (sc->bar4)
++ iounmap(sc->bar4);
++ kfree(sc);
++disable_dev:
++ pci_disable_device(dev);
++ return ret;
++}
++
++static void apcie_remove(struct pci_dev *dev) {
++ struct apcie_dev *sc;
++ sc = pci_get_drvdata(dev);
++
++ apcie_icc_remove(sc);
++ apcie_uart_remove(sc);
++ apcie_glue_remove(sc);
++
++ if (sc->bar0)
++ iounmap(sc->bar0);
++ if (sc->bar2)
++ iounmap(sc->bar2);
++ if (sc->bar4)
++ iounmap(sc->bar4);
++ kfree(sc);
++ pci_disable_device(dev);
++}
++
++#ifdef CONFIG_PM
++static int apcie_suspend(struct pci_dev *dev, pm_message_t state) {
++ struct apcie_dev *sc;
++ sc = pci_get_drvdata(dev);
++
++ apcie_icc_suspend(sc, state);
++ apcie_uart_suspend(sc, state);
++ apcie_glue_suspend(sc, state);
++ return 0;
++}
++
++static int apcie_resume(struct pci_dev *dev) {
++ struct apcie_dev *sc;
++ sc = pci_get_drvdata(dev);
++
++ apcie_icc_resume(sc);
++ apcie_glue_resume(sc);
++ apcie_uart_resume(sc);
++ return 0;
++}
++#endif
++
++static const struct pci_device_id apcie_pci_tbl[] = {
++ { PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_AEOLIA_PCIE), },
++ { PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_BELIZE_PCIE), },
++ { PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_BAIKAL_PCIE), },
++ { }
++};
++MODULE_DEVICE_TABLE(pci, apcie_pci_tbl);
++
++static struct pci_driver apcie_driver = {
++ .name = "aeolia_pcie",
++ .id_table = apcie_pci_tbl,
++ .probe = apcie_probe,
++ .remove = apcie_remove,
++#ifdef CONFIG_PM
++ .suspend = apcie_suspend,
++ .resume = apcie_resume,
++#endif
++};
++module_pci_driver(apcie_driver);
+diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
+index 8a1e26473566..9c62f14fad84 100644
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -551,6 +551,8 @@
+ #define PCI_DEVICE_ID_AMD_16H_NB_F4 0x1534
+ #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583
+ #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584
++#define PCI_DEVICE_ID_AMD_16H_M41H_F3 0x1431
++#define PCI_DEVICE_ID_AMD_16H_M41H_F4 0x1432
+ #define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
+ #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb
+ #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493
+@@ -893,6 +895,30 @@
+ #define PCI_DEVICE_ID_TI_DRA72x 0xb501
+
+ #define PCI_VENDOR_ID_SONY 0x104d
++#define PCI_DEVICE_ID_SONY_AEOLIA_ACPI 0x908f
++#define PCI_DEVICE_ID_SONY_AEOLIA_GBE 0x909e
++#define PCI_DEVICE_ID_SONY_AEOLIA_AHCI 0x909f
++#define PCI_DEVICE_ID_SONY_AEOLIA_SDHCI 0x90a0
++#define PCI_DEVICE_ID_SONY_AEOLIA_PCIE 0x90a1
++#define PCI_DEVICE_ID_SONY_AEOLIA_DMAC 0x90a2
++#define PCI_DEVICE_ID_SONY_AEOLIA_MEM 0x90a3
++#define PCI_DEVICE_ID_SONY_AEOLIA_XHCI 0x90a4
++#define PCI_DEVICE_ID_SONY_BELIZE_ACPI 0x90c8
++#define PCI_DEVICE_ID_SONY_BELIZE_GBE 0x90c9
++#define PCI_DEVICE_ID_SONY_BELIZE_AHCI 0x90ca
++#define PCI_DEVICE_ID_SONY_BELIZE_SDHCI 0x90cb
++#define PCI_DEVICE_ID_SONY_BELIZE_PCIE 0x90cc
++#define PCI_DEVICE_ID_SONY_BELIZE_DMAC 0x90cd
++#define PCI_DEVICE_ID_SONY_BELIZE_MEM 0x90ce
++#define PCI_DEVICE_ID_SONY_BELIZE_XHCI 0x90cf
++#define PCI_DEVICE_ID_SONY_BAIKAL_ACPI 0x90d7
++#define PCI_DEVICE_ID_SONY_BAIKAL_GBE 0x90d8
++#define PCI_DEVICE_ID_SONY_BAIKAL_AHCI 0x90d9
++#define PCI_DEVICE_ID_SONY_BAIKAL_SDHCI 0x90da
++#define PCI_DEVICE_ID_SONY_BAIKAL_PCIE 0x90db
++#define PCI_DEVICE_ID_SONY_BAIKAL_DMAC 0x90dc
++#define PCI_DEVICE_ID_SONY_BAIKAL_MEM 0x90dd
++#define PCI_DEVICE_ID_SONY_BAIKAL_XHCI 0x90de
+
+ /* Winbond have two vendor IDs! See 0x10ad as well */
+ #define PCI_VENDOR_ID_WINBOND2 0x1050
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0002-feat-amdgpu-patches.patch b/device/testing/linux-sony-ps4/0002-feat-amdgpu-patches.patch
new file mode 100644
index 0000000000000000000000000000000000000000..48ac7021af33f92b7a9ad614478ef6416f9b4818
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0002-feat-amdgpu-patches.patch
@@ -0,0 +1,2770 @@
+From dc3a4684ee5dde8df325a4f94af3d2ca6a248736 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Mon, 20 Dec 2021 12:32:27 +0100
+Subject: [PATCH 02/22] feat: amdgpu patches
+
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile | 1 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +
+ .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 51 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 20 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 20 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 5 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +
+ drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 10 +-
+ .../gpu/drm/amd/amdgpu/atombios_encoders.c | 6 +-
+ drivers/gpu/drm/amd/amdgpu/cik.c | 321 ++++++++
+ drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 29 +-
+ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 44 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 667 ++++++++++++++-
+ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 19 +
+ drivers/gpu/drm/amd/amdgpu/ps4_bridge.c | 776 ++++++++++++++++++
+ .../gpu/drm/amd/amdkfd/cik_event_interrupt.c | 5 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 3 +
+ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 46 ++
+ .../drm/amd/amdkfd/kfd_device_queue_manager.c | 5 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 2 +
+ drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 2 +
+ .../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 2 +
+ drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +
+ .../drm/amd/include/asic_reg/gmc/gmc_7_1_d.h | 28 +
+ include/drm/amd_asic_type.h | 56 +-
+ include/drm/drm_pciids.h | 4 +
+ 28 files changed, 2086 insertions(+), 51 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/ps4_bridge.c
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 8d0748184a14..bc79dc5dfaac 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -237,6 +237,7 @@ amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o
+ amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
+ amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o
+ amdgpu-$(CONFIG_HMM_MIRROR) += amdgpu_mn.o
++amdgpu-$(CONFIG_X86_PS4) += ps4_bridge.o
+
+ include $(FULL_AMD_PATH)/pm/Makefile
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index d90da384d185..fc3d11bbd206 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -270,6 +270,9 @@ extern int amdgpu_num_kcq;
+ #define CIK_CURSOR_WIDTH 128
+ #define CIK_CURSOR_HEIGHT 128
+
++#define LVP_CURSOR_WIDTH 64
++#define LVP_CURSOR_HEIGHT 64
++
+ /* smasrt shift bias level limits */
+ #define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
+ #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+index c777aff164b7..edceba19b54a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+@@ -1516,6 +1516,31 @@ static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
+ .late_register = amdgpu_connector_late_register,
+ };
+
++#ifdef CONFIG_X86_PS4
++int ps4_bridge_get_modes(struct drm_connector *connector);
++int ps4_bridge_mode_valid(struct drm_connector *connector,
++ struct drm_display_mode *mode);
++enum drm_connector_status ps4_bridge_detect(struct drm_connector *connector,
++ bool force);
++
++
++static const struct drm_connector_helper_funcs amdgpu_ps4_dp_connector_helper_funcs = {
++ .get_modes = ps4_bridge_get_modes,
++ .mode_valid = ps4_bridge_mode_valid,
++ .best_encoder = amdgpu_connector_dvi_encoder,
++};
++
++static const struct drm_connector_funcs amdgpu_ps4_dp_connector_funcs = {
++ .dpms = drm_helper_connector_dpms,
++ .detect = ps4_bridge_detect,
++ .fill_modes = drm_helper_probe_single_connector_modes,
++ //.set_property = amdgpu_connector_set_property,
++ .destroy = amdgpu_connector_destroy,
++ .force = amdgpu_connector_dvi_force,
++ .late_register = amdgpu_connector_late_register,
++};
++#endif
++
+ static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
+ .dpms = drm_helper_connector_dpms,
+ .detect = amdgpu_connector_dp_detect,
+@@ -1547,6 +1572,7 @@ amdgpu_connector_add(struct amdgpu_device *adev,
+ struct i2c_adapter *ddc = NULL;
+ uint32_t subpixel_order = SubPixelNone;
+ bool shared_ddc = false;
++ bool is_ps4_bridge = false;
+ bool is_dp_bridge = false;
+ bool has_aux = false;
+
+@@ -1595,6 +1621,18 @@ amdgpu_connector_add(struct amdgpu_device *adev,
+ if (!amdgpu_connector)
+ return;
+
++ /* Liverpool (PS4) has an DP bridge which needs a special driver, and
++ * a fake HDMI port that doesn't really exist. */
++ if (adev->asic_type == CHIP_LIVERPOOL || adev->asic_type == CHIP_GLADIUS) {
++ if (connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
++ connector_type = DRM_MODE_CONNECTOR_HDMIA;
++ is_dp_bridge = true;
++ is_ps4_bridge = true;
++ } else {
++ return;
++ }
++ }
++
+ connector = &amdgpu_connector->base;
+
+ amdgpu_connector->connector_id = connector_id;
+@@ -1649,12 +1687,21 @@ amdgpu_connector_add(struct amdgpu_device *adev,
+ case DRM_MODE_CONNECTOR_HDMIA:
+ case DRM_MODE_CONNECTOR_HDMIB:
+ case DRM_MODE_CONNECTOR_DisplayPort:
+- drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
++ if(!is_ps4_bridge) {
++ drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
+ &amdgpu_connector_dp_funcs,
+ connector_type,
+ ddc);
+- drm_connector_helper_add(&amdgpu_connector->base,
++ drm_connector_helper_add(&amdgpu_connector->base,
+ &amdgpu_connector_dp_helper_funcs);
++ } else {
++ drm_connector_init(dev, &amdgpu_connector->base,
++ &amdgpu_ps4_dp_connector_funcs,
++ connector_type);
++
++ drm_connector_helper_add(&amdgpu_connector->base,
++ &amdgpu_ps4_dp_connector_helper_funcs);
++ }
+ drm_object_attach_property(&amdgpu_connector->base.base,
+ adev->mode_info.underscan_property,
+ UNDERSCAN_OFF);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 2f51789d9818..125233cf8287 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -106,6 +106,8 @@ const char *amdgpu_asic_name[] = {
+ "KAVERI",
+ "KABINI",
+ "HAWAII",
++ "LIVERPOOL",
++ "GLADIUS",
+ "MULLINS",
+ "TOPAZ",
+ "TONGA",
+@@ -1957,6 +1959,8 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
+ #ifdef CONFIG_DRM_AMDGPU_CIK
+ case CHIP_BONAIRE:
+ case CHIP_HAWAII:
++ case CHIP_GLADIUS:
++ case CHIP_LIVERPOOL:
+ case CHIP_KAVERI:
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
+@@ -2144,6 +2148,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
+ case CHIP_KAVERI:
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
++ case CHIP_LIVERPOOL:
++ case CHIP_GLADIUS:
+ if (adev->flags & AMD_IS_APU)
+ adev->family = AMDGPU_FAMILY_KV;
+ else
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+index 4df888c7e2ff..8efd8c40762b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+@@ -46,6 +46,10 @@
+ #include "amdgpu_fdinfo.h"
+ #include "amdgpu_amdkfd.h"
+
++#ifdef CONFIG_X86_PS4
++#include <asm/ps4.h>
++#endif
++
+ #include "amdgpu_ras.h"
+ #include "amdgpu_xgmi.h"
+ #include "amdgpu_reset.h"
+@@ -1759,6 +1763,12 @@ static const struct pci_device_id pciidlist[] = {
+ {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
+ {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
+ {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
++ /* Liverpool */
++ {0x1002, 0x9920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|AMD_IS_APU},
++ {0x1002, 0x9922, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|AMD_IS_APU},
++ {0x1002, 0x9923, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|AMD_IS_APU},
++ /* Gladius */
++ {0x1002, 0x9924, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_GLADIUS|AMD_IS_APU},
+ #endif
+ /* topaz */
+ {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
+@@ -2066,6 +2076,16 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
+ size = pci_resource_len(pdev, 0);
+ is_fw_fb = amdgpu_is_fw_framebuffer(base, size);
+
++ #ifdef CONFIG_X86_PS4
++ /* On the PS4 (Liverpool graphics) we have a hard dependency on the
++ * Aeolia driver to set up the HDMI encoder which is connected to it,
++ * so defer probe until it is ready. This test passes if this isn't
++ * a PS4 (returns -ENODEV).
++ */
++ if (apcie_status() == 0)
++ return -EPROBE_DEFER;
++ #endif
++
+ adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
+ if (IS_ERR(adev))
+ return PTR_ERR(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
+index af4ef84e27a7..619d4c771176 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
+@@ -32,6 +32,23 @@
+ #include "atom.h"
+ #include "atombios_encoders.h"
+
++#ifdef CONFIG_X86_PS4
++int
++ps4_bridge_register(struct drm_connector *connector,
++ struct drm_encoder *encoder);
++
++static void amdgpu_maybe_add_bridge(struct drm_connector *connector,
++ struct drm_encoder *encoder)
++{
++ struct drm_device *dev = connector->dev;
++ struct amdgpu_device *adev = dev->dev_private;
++
++ if (adev->asic_type == CHIP_LIVERPOOL || adev->asic_type == CHIP_GLADIUS) {
++ ps4_bridge_register(connector, encoder);
++ }
++}
++#endif
++
+ void
+ amdgpu_link_encoder_connector(struct drm_device *dev)
+ {
+@@ -49,6 +66,9 @@ amdgpu_link_encoder_connector(struct drm_device *dev)
+ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+ amdgpu_encoder = to_amdgpu_encoder(encoder);
+ if (amdgpu_encoder->devices & amdgpu_connector->devices) {
++ #ifdef CONFIG_X86_PS4
++ amdgpu_maybe_add_bridge(connector, encoder);
++ #endif
+ drm_connector_attach_encoder(connector, encoder);
+ if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+ amdgpu_atombios_encoder_init_backlight(amdgpu_encoder, connector);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+index c076a6b9a5a2..486c571768d8 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+@@ -385,7 +385,12 @@ int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
+ tmo_gfx = AMDGPU_IB_TEST_GFX_XGMI_TIMEOUT;
+ }
+
++ #ifdef CONFIG_X86_PS4
++ //TODO test if this is needed now
++ for (i = 0; i < 1 /*adev->num_rings*/; ++i) {
++ #else
+ for (i = 0; i < adev->num_rings; ++i) {
++ #endif
+ struct amdgpu_ring *ring = adev->rings[i];
+ long tmo;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+index 0ed0736d515a..b98296c851db 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+@@ -377,6 +377,8 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
+ case CHIP_KABINI:
+ case CHIP_HAWAII:
+ case CHIP_MULLINS:
++ case CHIP_LIVERPOOL:
++ case CHIP_GLADIUS:
+ return AMDGPU_FW_LOAD_DIRECT;
+ #endif
+ case CHIP_TOPAZ:
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+index 7d58bf410be0..412faeef0c96 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+@@ -536,6 +536,8 @@ static int amdgpu_vkms_hw_init(void *handle)
+ case CHIP_KAVERI:
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
++ case CHIP_LIVERPOOL:
++ case CHIP_GLADIUS:
+ dce_v8_0_disable_dce(adev);
+ break;
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+index f327becb022f..33987ecdc517 100644
+--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+@@ -257,12 +257,20 @@ static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector
+ amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
+ static const unsigned link_rates[3] = { 162000, 270000, 540000 };
+ unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
++ unsigned min_lane_num = 1;
+ unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
+ unsigned lane_num, i, max_pix_clock;
++ struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++ struct drm_device *dev = amdgpu_connector->base.dev;
++ struct amdgpu_device *adev = dev->dev_private;
++
++ /* Liverpool is always connected to an encoder that needs 4 lanes */
++ if (adev->asic_type == CHIP_LIVERPOOL)
++ min_lane_num = 4;
+
+ if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
+ ENCODER_OBJECT_ID_NUTMEG) {
+- for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
++ for (lane_num = min_lane_num; lane_num <= max_lane_num; lane_num <<= 1) {
+ max_pix_clock = (lane_num * 270000 * 8) / bpp;
+ if (max_pix_clock >= pix_clock) {
+ *dp_lanes = lane_num;
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+index 6134ed964027..5bd8a782feb5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+@@ -445,8 +445,12 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder)
+ struct amdgpu_connector *amdgpu_connector;
+ struct amdgpu_connector_atom_dig *dig_connector;
+
++ struct drm_device *dev = encoder->dev;
++ struct amdgpu_device *adev = dev->dev_private;
++
+ /* dp bridges are always DP */
+- if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
++ if ((amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) ||
++ (adev->asic_type == CHIP_LIVERPOOL) || (adev->asic_type == CHIP_GLADIUS))
+ return ATOM_ENCODER_MODE_DP;
+
+ /* DVO is always DVO */
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+index de6d10390ab2..353899a95424 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -788,6 +788,206 @@ static const u32 hawaii_mgcg_cgcg_init[] =
+ 0x3603, 0xff000ff0, 0x00000100
+ };
+
++static const u32 liverpool_golden_common_registers[] =
++{
++ 0x31dc, 0xffffffff, 0x00000800, /* SPI_RESOURCE_RESERVE_CU_0 */
++ 0x31dd, 0xffffffff, 0x00000800, /* SPI_RESOURCE_RESERVE_CU_1 */
++ 0x31e6, 0xffffffff, 0x00ffffbf, /* SPI_RESOURCE_RESERVE_EN_CU_0 */
++ 0x31e7, 0xffffffff, 0x00ffffaf, /* SPI_RESOURCE_RESERVE_EN_CU_1 */
++ 0x31e8, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_2 */
++ 0x31e9, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_3*/
++ 0x31ea, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_4 */
++ 0x31eb, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_5 */
++ 0x31ec, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_6 */
++ 0x31ed, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_7 */
++ 0x31ee, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_8 */
++ 0x31ef, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_9 */
++ 0xa0d4, 0xffffffff, 0x2a00161a, /* PA_SC_RASTER_CONFIG */
++ 0xa0d5, 0xffffffff, 0x00000000, /* PA_SC_RASTER_CONFIG_1 */
++ 0x1401, 0x00002000, 0x00002000, /* GARLIC_FLUSH_CNTL */
++};
++
++static const u32 liverpool_golden_registers[] =
++{
++ 0x3108, 0xffffffff, 0xfffffffc, /* RLC_CGTT_MGCG_OVERRIDE */
++ 0xc200, 0xffffffff, 0xe0000000, /* GRBM_GFX_INDEX */
++ /* These are all setting OFF_HYSTERESIS = 0x10 */
++ 0xf0a8, 0xffffffff, 0x00000100, /* CB_CGTT_SCLK_CTRL */
++ 0xf082, 0xffffffff, 0x00000100, /* CGTT_BCI_CLK_CTRL */
++ 0xf0b0, 0xffffffff, 0x00000100, /* CGTT_CP_CLK_CTRL */
++ 0xf0b2, 0xffffffff, 0x00000100, /* CGTT_CPC_CLK_CTRL */
++ 0xf0b1, 0xffffffff, 0x00000100, /* CGTT_CPF_CLK_CTRL */
++ 0x1579, 0xffffffff, 0x00600100, /* CGTT_DRM_CLK_CTRL0 */
++ 0xf0a0, 0xffffffff, 0x00000100, /* CGTT_GDS_CLK_CTRL */
++ 0xf085, 0xffffffff, 0x06000100, /* CGTT_IA_CLK_CTRL */
++ 0xf088, 0xffffffff, 0x00000100, /* CGTT_PA_CLK_CTRL */
++ 0xf086, 0xffffffff, 0x06000100, /* CGTT_WD_CLK_CTRL */
++ 0xf081, 0xffffffff, 0x00000100, /* CGTT_PC_CLK_CTRL */
++ 0xf0b8, 0xffffffff, 0x00000100, /* CGTT_RLC_CLK_CTRL */
++ 0xf089, 0xffffffff, 0x00000100, /* CGTT_SC_CLK_CTRL */
++ 0xf080, 0xffffffff, 0x00000100, /* CGTT_SPI_CLK_CTRL */
++ 0xf08c, 0xffffffff, 0x00000100, /* CGTT_SQ_CLK_CTRL */
++ 0xf08d, 0xffffffff, 0x00000100, /* CGTT_SQG_CLK_CTRL */
++ 0xf094, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL0 */
++ 0xf095, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL1 */
++ 0xf096, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL2 */
++ 0xf097, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL3 */
++ 0xf098, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL4 */
++ 0xf09f, 0xffffffff, 0x00000100, /* CGTT_TCI_CLK_CTRL */
++ 0xf09e, 0xffffffff, 0x00000100, /* CGTT_TCP_CLK_CTRL */
++ 0xf084, 0xffffffff, 0x06000100, /* CGTT_VGT_CLK_CTRL */
++ 0xf0a4, 0xffffffff, 0x00000100, /* DB_CGTT_CLK_CTRL_0 */
++ 0xf09d, 0xffffffff, 0x00000100, /* TA_CGTT_CTRL */
++ 0xf0ad, 0xffffffff, 0x00000100, /* TCA_CGTT_SCLK_CTRL */
++ 0xf0ac, 0xffffffff, 0x00000100, /* TCC_CGTT_SCLK_CTRL */
++ 0xf09c, 0xffffffff, 0x00000100, /* TD_CGTT_CTRL */
++ /* */
++ 0xc200, 0xffffffff, 0xe0000000, /* GRBM_GFX_INDEX */
++ 0xf008, 0xffffffff, 0x00010000, /* CGTS_CU0_SP0_CTRL_REG */
++ 0xf009, 0xffffffff, 0x00030002, /* CGTS_CU0_LDS_SQ_CTRL_REG */
++ 0xf00a, 0xffffffff, 0x00040007, /* CGTS_CU0_TA_SQC_CTRL_REG */
++ 0xf00b, 0xffffffff, 0x00060005, /* CGTS_CU0_SP1_CTRL_REG */
++ 0xf00c, 0xffffffff, 0x00090008, /* CGTS_CU0_TD_TCP_CTRL_REG */
++ 0xf00d, 0xffffffff, 0x00010000, /* CGTS_CU1_SP0_CTRL_REG */
++ 0xf00e, 0xffffffff, 0x00030002, /* CGTS_CU1_LDS_SQ_CTRL_REG */
++ 0xf00f, 0xffffffff, 0x00040007, /* CGTS_CU1_TA_CTRL_REG */
++ 0xf010, 0xffffffff, 0x00060005, /* CGTS_CU1_SP1_CTRL_REG */
++ 0xf011, 0xffffffff, 0x00090008, /* CGTS_CU1_TD_TCP_CTRL_REG */
++ 0xf012, 0xffffffff, 0x00010000, /* CGTS_CU2_SP0_CTRL_REG */
++ 0xf013, 0xffffffff, 0x00030002, /* CGTS_CU2_LDS_SQ_CTRL_REG */
++ 0xf014, 0xffffffff, 0x00040007, /* CGTS_CU2_TA_CTRL_REG */
++ 0xf015, 0xffffffff, 0x00060005, /* CGTS_CU2_SP1_CTRL_REG */
++ 0xf016, 0xffffffff, 0x00090008, /* CGTS_CU2_TD_TCP_CTRL_REG */
++ 0xf017, 0xffffffff, 0x00010000, /* CGTS_CU3_SP0_CTRL_REG */
++ 0xf018, 0xffffffff, 0x00030002, /* CGTS_CU3_LDS_SQ_CTRL_REG */
++ 0xf019, 0xffffffff, 0x00040007, /* CGTS_CU3_TA_SQC_CTRL_REG */
++ 0xf01a, 0xffffffff, 0x00060005, /* CGTS_CU3_SP1_CTRL_REG */
++ 0xf01b, 0xffffffff, 0x00090008, /* CGTS_CU3_TD_TCP_CTRL_REG */
++ 0xf01c, 0xffffffff, 0x00010000, /* CGTS_CU4_SP0_CTRL_REG */
++ 0xf01d, 0xffffffff, 0x00030002, /* CGTS_CU4_LDS_SQ_CTRL_REG */
++ 0xf01e, 0xffffffff, 0x00040007, /* CGTS_CU4_TA_CTRL_REG */
++ 0xf01f, 0xffffffff, 0x00060005, /* CGTS_CU4_SP1_CTRL_REG */
++ 0xf020, 0xffffffff, 0x00090008, /* CGTS_CU4_TD_TCP_CTRL_REG */
++ 0xf021, 0xffffffff, 0x00010000, /* CGTS_CU5_SP0_CTRL_REG */
++ 0xf022, 0xffffffff, 0x00030002, /* CGTS_CU5_LDS_SQ_CTRL_REG */
++ 0xf023, 0xffffffff, 0x00040007, /* CGTS_CU5_TA_CTRL_REG */
++ 0xf024, 0xffffffff, 0x00060005, /* CGTS_CU5_SP1_CTRL_REG */
++ 0xf025, 0xffffffff, 0x00090008, /* CGTS_CU5_TD_TCP_CTRL_REG */
++ 0xf026, 0xffffffff, 0x00010000, /* CGTS_CU6_SP0_CTRL_REG */
++ 0xf027, 0xffffffff, 0x00030002, /* CGTS_CU6_LDS_SQ_CTRL_REG */
++ 0xf028, 0xffffffff, 0x00040007, /* CGTS_CU6_TA_SQC_CTRL_REG */
++ 0xf029, 0xffffffff, 0x00060005, /* CGTS_CU6_SP1_CTRL_REG */
++ 0xf02a, 0xffffffff, 0x00090008, /* CGTS_CU6_TD_TCP_CTRL_REG */
++ 0xf02b, 0xffffffff, 0x00010000, /* CGTS_CU7_SP0_CTRL_REG */
++ 0xf02c, 0xffffffff, 0x00030002, /* CGTS_CU7_LDS_SQ_CTRL_REG */
++ 0xf02d, 0xffffffff, 0x00040007, /* CGTS_CU7_TA_SQC_CTRL_REG */
++ 0xf02e, 0xffffffff, 0x00060005, /* CGTS_CU7_SP1_CTRL_REG */
++ 0xf02f, 0xffffffff, 0x00090008, /* CGTS_CU7_TD_TCP_CTRL_REG */
++ 0xf030, 0xffffffff, 0x00010000, /* CGTS_CU8_SP0_CTRL_REG */
++ 0xf031, 0xffffffff, 0x00030002, /* CGTS_CU8_LDS_SQ_CTRL_REG */
++ 0xf032, 0xffffffff, 0x00040007, /* CGTS_CU8_TA_CTRL_REG */
++ 0xf033, 0xffffffff, 0x00060005, /* CGTS_CU8_SP1_CTRL_REG */
++ 0xf034, 0xffffffff, 0x00090008, /* CGTS_CU8_TD_TCP_CTRL_REG */
++ 0xf035, 0xffffffff, 0x00010000, /* CGTS_CU9_SP0_CTRL_REG */
++ 0xf036, 0xffffffff, 0x00030002, /* CGTS_CU9_LDS_SQ_CTRL_REG */
++ 0xf037, 0xffffffff, 0x00040007, /* CGTS_CU9_TA_CTRL_REG */
++ 0xf038, 0xffffffff, 0x00060005, /* CGTS_CU9_SP1_CTRL_REG */
++ 0xf039, 0xffffffff, 0x00090008, /* CGTS_CU9_TD_TCP_CTRL_REG */
++ 0xf000, 0xffffffff, 0x96940200, /* CGTS_SM_CTRL_REG */
++ 0x21c2, 0xffffffff, 0x00900100, /* CP_RB_WPTR_POLL_CNTL */
++ 0x3109, 0xffffffff, 0x0020003f, /* RLC_CGCG_CGLS_CTRL */
++ 0x2684, 0x00210000, 0x00018208, /* CB_HW_CONTROL */
++ 0xf000, 0xffff1fff, 0x96940200, /* CGTS_SM_CTRL_REG */
++ 0xf003, 0xffff0001, 0xff000000, /* CGTS_TCC_DISABLE */
++ 0xf004, 0xffff0000, 0xff000000, /* CGTS_USER_TCC_DISABLE */
++ 0x1579, 0xff607fff, 0xfc000100, /* CGTT_DRM_CLK_CTRL0 */
++ 0xf080, 0xfdfc0fff, 0x00000100, /* CGTT_SPI_CLK_CTRL */
++ 0x1bb6, 0x00010000, 0x00010000, /* CRTC_DOUBLE_BUFFER_CONTROL */
++ 0x260d, 0xf00fffff, 0x00004400, /* DB_DEBUG2 */
++ 0x16ec, 0x000000f0, 0x00000070, /* FBC_DEBUG_COMP */
++ 0x263e, 0x73773777, 0x12011003, /* GB_ADDR_CONFIG */
++ 0xbd2, 0x73773777, 0x12010001, /* HDP_ADDR_CONFIG */
++ 0x2285, 0xf000003f, 0x00000007, /* PA_CL_ENHANCE */
++ 0x22fc, 0x00000001, 0x00000001, /* PA_SC_ENHANCE */
++ 0x22c9, 0xffffffff, 0x00ffffff, /* PA_SC_FORCE_EOV_MAX_CNTS */
++ 0xc281, 0x0000ff0f, 0x00000000, /* PA_SC_LINE_STIPPLE_STATE */
++ 0xa293, 0x07ffffff, 0x06000000, /* PA_SC_MODE_CNTL_1 */
++ 0x30df, 0xffffffff, 0x00000b00, /* RLC_PG_DELAY_2 */
++ 0x136, 0x00000fff, 0x00000100, /* SCLK_CGTT_BLK_CTRL_REG */
++ 0xf9e, 0x00000001, 0x00000002, /* SEM_CHICKEN_BITS */
++ 0x31da, 0x00000008, 0x00000008, /* SPI_RESET_DEBUG */
++ 0x2300, 0x000000ff, 0x00000001, /* SQ_CONFIG */
++ 0x2542, 0x00010000, 0x00010000, /* TA_CNTL_AUX */
++ 0x2b03, 0xffffffff, 0x76325410, /* TCP_CHAN_STEER_LO */
++ 0x31dc, 0xffffffff, 0x00000800, /* SPI_RESOURCE_RESERVE_CU_0 */
++ 0x31dd, 0xffffffff, 0x00000800, /* SPI_RESOURCE_RESERVE_CU_1 */
++ 0x31e6, 0xffffffff, 0x00ffffbf, /* SPI_RESOURCE_RESERVE_EN_CU_0 */
++ 0x31e7, 0xffffffff, 0x00ffffaf, /* SPI_RESOURCE_RESERVE_EN_CU_1 */
++ 0x31e8, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_2 */
++ 0x31e9, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_3 */
++ 0x31ea, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_4 */
++ 0x31eb, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_5*/
++ 0x31ec, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_6 */
++ 0x31ed, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_7 */
++ 0x31ee, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_8 */
++ 0x31ef, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_9 */
++ 0xa0d4, 0xffffffff, 0x2a00161a, /* PA_SC_RASTER_CONFIG */
++ 0xa0d5, 0xffffffff, 0x00000000, /* PA_SC_RASTER_CONFIG_1 */
++ 0x1401, 0x00002000, 0x00002000, /* GARLIC_FLUSH_CNTL */
++ 0x535, 0xffffffff, 0x00000000, /* VM_CONTEXTS_DISABLE */
++};
++
++static const u32 gladius_golden_common_registers[] =
++{
++ mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
++ mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208, // 0x2684
++ mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
++ mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
++ mmDB_DEBUG2, 0xf00fffff, 0x00000400,
++ mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
++ mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
++ mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x2a00161a,
++ mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
++ mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0020003c, //0x0001003c,
++ 0xec9d, 0xffffffff, 0x0001003c,//mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
++ mmSQ_CONFIG, 0x07f80000, 0x07180000,
++ mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
++ mmTCC_CTRL, 0x00100000, 0xf31fff7f,
++ mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
++ mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
++ mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
++ mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
++ mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
++ mmFBC_MISC, 0x9f313fff, 0x14302008,
++ mmHDMI_CONTROL, 0x313f031f, 0x00000011,
++};
++
++static const u32 gladius_golden_registers[] =
++{
++ mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
++ mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x2a00161a,
++ mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
++ mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, //0x22011003,
++ mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
++ mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
++ mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
++ mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
++ 0x535, 0xffffffff, 0x00000000, /* VM_CONTEXTS_DISABLE */
++
++};
++
++static const u32 gladius_mgcg_cgcg_init[] =
++{
++ 0x0000313a, 0xffffffff, 0x00000003,
++ 0x00003079, 0xffffffff, 0x00020201,
++ 0x00003108, 0xffffffff, 0xfffffffd,
++ 0x0000c200, 0xffffffff, 0xe0000000,
++ 0x0000311d, 0xffffffff, 0xffffffff,
++ 0x0000311e, 0xffffffff, 0xffffffff,
++ 0x0000311f, 0xffffffff, 0x004000ff,
++ 0x0000313a, 0xffffffff, 0x00000001,
++};
++
+ static const u32 godavari_golden_registers[] =
+ {
+ 0x1579, 0xff607fff, 0xfc000100,
+@@ -900,6 +1100,34 @@ static void cik_init_golden_registers(struct amdgpu_device *adev)
+ hawaii_golden_spm_registers,
+ ARRAY_SIZE(hawaii_golden_spm_registers));
+ break;
++ case CHIP_LIVERPOOL:
++ // TODO (ps4patches): Why is this in comments?
++ /*amdgpu_device_program_register_sequence(adev,
++ liverpool_mgcg_cgcg_init,
++ ARRAY_SIZE(liverpool_mgcg_cgcg_init));*/
++ amdgpu_device_program_register_sequence(adev,
++ liverpool_golden_registers,
++ ARRAY_SIZE(liverpool_golden_registers));
++ amdgpu_device_program_register_sequence(adev,
++ liverpool_golden_common_registers,
++ ARRAY_SIZE(liverpool_golden_common_registers));
++ // TODO (ps4patches): no spm registers, try the bonaire ones?
++ break;
++ case CHIP_GLADIUS:
++ amdgpu_device_program_register_sequence(adev,
++ gladius_mgcg_cgcg_init,
++ ARRAY_SIZE(gladius_mgcg_cgcg_init));
++ amdgpu_device_program_register_sequence(adev,
++ gladius_golden_registers,
++ ARRAY_SIZE(gladius_golden_registers));
++ amdgpu_device_program_register_sequence(adev,
++ gladius_golden_common_registers,
++ ARRAY_SIZE(gladius_golden_common_registers));
++ // TODO (ps4patches): Why is this using the Hawaii golden spm registers, that seems wrong?
++ amdgpu_device_program_register_sequence(adev,
++ hawaii_golden_spm_registers,
++ ARRAY_SIZE(hawaii_golden_spm_registers));
++ break;
+ default:
+ break;
+ }
+@@ -2147,6 +2375,63 @@ static int cik_common_early_init(void *handle)
+ } else
+ adev->external_rev_id = adev->rev_id + 0xa1;
+ break;
++ case CHIP_LIVERPOOL:
++ adev->cg_flags =
++ AMD_CG_SUPPORT_GFX_MGCG |
++ AMD_CG_SUPPORT_GFX_MGLS |
++ /*AMD_CG_SUPPORT_GFX_CGCG |*/
++ AMD_CG_SUPPORT_GFX_CGLS |
++ AMD_CG_SUPPORT_GFX_CGTS |
++ AMD_CG_SUPPORT_GFX_CGTS_LS |
++ AMD_CG_SUPPORT_GFX_CP_LS |
++ AMD_CG_SUPPORT_SDMA_MGCG |
++ AMD_CG_SUPPORT_SDMA_LS |
++ AMD_CG_SUPPORT_BIF_LS |
++ AMD_CG_SUPPORT_VCE_MGCG |
++ AMD_CG_SUPPORT_UVD_MGCG |
++ AMD_CG_SUPPORT_HDP_LS |
++ AMD_CG_SUPPORT_HDP_MGCG;
++ adev->pg_flags =
++ /*AMD_PG_SUPPORT_GFX_PG |
++ AMD_PG_SUPPORT_GFX_SMG | */
++ /*AMD_PG_SUPPORT_UVD | */
++ /*AMD_PG_SUPPORT_VCE |
++ AMD_PG_SUPPORT_CP |
++ AMD_PG_SUPPORT_GDS |
++ AMD_PG_SUPPORT_RLC_SMU_HS |
++ AMD_PG_SUPPORT_SAMU |*/
++ 0;
++ adev->external_rev_id = adev->rev_id + 0x61;
++ break;
++
++ case CHIP_GLADIUS:
++ adev->cg_flags =
++ AMD_CG_SUPPORT_GFX_MGCG |
++ AMD_CG_SUPPORT_GFX_MGLS |
++ AMD_CG_SUPPORT_GFX_CGCG |
++ AMD_CG_SUPPORT_GFX_CGLS |
++ AMD_CG_SUPPORT_GFX_CGTS |
++ AMD_CG_SUPPORT_GFX_CGTS_LS |
++ AMD_CG_SUPPORT_GFX_CP_LS |
++ AMD_CG_SUPPORT_SDMA_MGCG |
++ AMD_CG_SUPPORT_SDMA_LS |
++ AMD_CG_SUPPORT_BIF_LS |
++ AMD_CG_SUPPORT_VCE_MGCG |
++ AMD_CG_SUPPORT_UVD_MGCG |
++ AMD_CG_SUPPORT_HDP_LS |
++ AMD_CG_SUPPORT_HDP_MGCG;
++ adev->pg_flags =
++ /*AMD_PG_SUPPORT_GFX_PG |
++ AMD_PG_SUPPORT_GFX_SMG | */
++ /*AMD_PG_SUPPORT_UVD | */
++ /*AMD_PG_SUPPORT_VCE |
++ AMD_PG_SUPPORT_CP |
++ AMD_PG_SUPPORT_GDS |
++ AMD_PG_SUPPORT_RLC_SMU_HS |
++ AMD_PG_SUPPORT_SAMU |*/
++ 0;
++ adev->external_rev_id = adev->rev_id + 0x71;
++ break;
+ default:
+ /* FIXME: not supported yet */
+ return -EINVAL;
+@@ -2329,6 +2614,42 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
+ amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
+ amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
+ break;
++ case CHIP_LIVERPOOL:
++ amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
++ amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
++ amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
++ //amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
++ if (adev->enable_virtual_display)
++ amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
++#if defined(CONFIG_DRM_AMD_DC)
++ else if (amdgpu_device_has_dc_support(adev))
++ amdgpu_device_ip_block_add(adev, &dm_ip_block);
++#endif
++ else
++ amdgpu_device_ip_block_add(adev, &dce_v8_1_ip_block);
++ amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block);
++ amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
++ /*amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block)*/;
++ /*amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block)*/;
++ break;
++ case CHIP_GLADIUS:
++ amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
++ amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
++ amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
++ //amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
++ if (adev->enable_virtual_display)
++ amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
++#if defined(CONFIG_DRM_AMD_DC)
++ else if (amdgpu_device_has_dc_support(adev))
++ amdgpu_device_ip_block_add(adev, &dm_ip_block);
++#endif
++ else
++ amdgpu_device_ip_block_add(adev, &dce_v8_1_ip_block);
++ amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block);
++ amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
++ /*amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block)*/;
++ /*amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block)*/;
++ break;
+ default:
+ /* FIXME: not supported yet */
+ return -EINVAL;
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+index c8ebd108548d..fd8228981558 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+@@ -66,6 +66,10 @@ MODULE_FIRMWARE("amdgpu/kabini_sdma.bin");
+ MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin");
+ MODULE_FIRMWARE("amdgpu/mullins_sdma.bin");
+ MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin");
++MODULE_FIRMWARE("amdgpu/liverpool_sdma.bin");
++MODULE_FIRMWARE("amdgpu/liverpool_sdma1.bin");
++MODULE_FIRMWARE("amdgpu/gladius_sdma.bin");
++MODULE_FIRMWARE("amdgpu/gladius_sdma1.bin");
+
+ u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
+
+@@ -129,6 +133,12 @@ static int cik_sdma_init_microcode(struct amdgpu_device *adev)
+ case CHIP_MULLINS:
+ chip_name = "mullins";
+ break;
++ case CHIP_LIVERPOOL:
++ chip_name = "liverpool";
++ break;
++ case CHIP_GLADIUS:
++ chip_name = "gladius";
++ break;
+ default: BUG();
+ }
+
+@@ -633,11 +643,20 @@ static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
+ if (r)
+ goto error_free_wb;
+
+- amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
+- amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
+- amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
+- amdgpu_ring_write(ring, 1); /* number of DWs to follow */
+- amdgpu_ring_write(ring, 0xDEADBEEF);
++ /* The SDMA_OPCODE_WRITE opcode is broken in the ring on Liverpool */
++ if (adev->asic_type == CHIP_LIVERPOOL) {
++ amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, SDMA_CONSTANT_FILL_EXTRA_SIZE(2)));
++ amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
++ amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
++ amdgpu_ring_write(ring, 0xDEADBEEF);
++ amdgpu_ring_write(ring, 4); /* number of bytes */
++ } else {
++ amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
++ amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
++ amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
++ amdgpu_ring_write(ring, 1); /* number of DWs to follow */
++ amdgpu_ring_write(ring, 0xDEADBEEF);
++ }
+ amdgpu_ring_commit(ring);
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+index b200b9e722d9..aaa6893d8e51 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+@@ -403,9 +403,11 @@ static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
+ switch (adev->asic_type) {
+ case CHIP_BONAIRE:
+ case CHIP_HAWAII:
++ case CHIP_GLADIUS:
+ num_crtc = 6;
+ break;
+ case CHIP_KAVERI:
++ case CHIP_LIVERPOOL:
+ num_crtc = 4;
+ break;
+ case CHIP_KABINI:
+@@ -1099,6 +1101,12 @@ static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
+ u32 num_heads = 0, lb_size;
+ int i;
+
++ if((adev->asic_type == CHIP_LIVERPOOL) ||
++ (adev->asic_type == CHIP_GLADIUS)) {
++ // FIXME PS4 (ps4patches): this stuff is broken
++ return;
++ }
++
+ amdgpu_display_update_priority(adev);
+
+ for (i = 0; i < adev->mode_info.num_crtc; i++) {
+@@ -1406,6 +1414,7 @@ static int dce_v8_0_audio_init(struct amdgpu_device *adev)
+ (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
+ adev->mode_info.audio.num_pins = 7;
+ else
++ /* (ps4patches) - Liverpool and Gladius use 3 streams so that is fine here */
+ adev->mode_info.audio.num_pins = 3;
+
+ for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
+@@ -1419,7 +1428,11 @@ static int dce_v8_0_audio_init(struct amdgpu_device *adev)
+ adev->mode_info.audio.pin[i].id = i;
+ /* disable audio. it will be set up later */
+ /* XXX remove once we switch to ip funcs */
+- dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
++ /* Liverpool pin 2 is S/PDIF and should always be available */
++ if (adev->asic_type == CHIP_LIVERPOOL || adev->asic_type == CHIP_GLADIUS)
++ dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], true);
++ else
++ dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
+ }
+
+ return 0;
+@@ -1995,7 +2008,9 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
+ }
+
+ /* Bytes per pixel may have changed */
+- dce_v8_0_bandwidth_update(adev);
++ if ((adev->asic_type != CHIP_LIVERPOOL) &&
++ (adev->asic_type != CHIP_GLADIUS))
++ dce_v8_0_bandwidth_update(adev);
+
+ return 0;
+ }
+@@ -2615,10 +2630,18 @@ static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
+ amdgpu_crtc->crtc_id = index;
+ adev->mode_info.crtcs[index] = amdgpu_crtc;
+
+- amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
+- amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
+- adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
+- adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
++ if ((adev->asic_type == CHIP_LIVERPOOL) || (adev->asic_type == CHIP_GLADIUS)) {
++ amdgpu_crtc->max_cursor_width = LVP_CURSOR_WIDTH;
++ amdgpu_crtc->max_cursor_height = LVP_CURSOR_HEIGHT;
++ adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
++ adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
++ }
++ else {
++ amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
++ amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
++ adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
++ adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
++ }
+
+ amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
+
+@@ -2645,10 +2668,12 @@ static int dce_v8_0_early_init(void *handle)
+ switch (adev->asic_type) {
+ case CHIP_BONAIRE:
+ case CHIP_HAWAII:
++ case CHIP_GLADIUS:
+ adev->mode_info.num_hpd = 6;
+ adev->mode_info.num_dig = 6;
+ break;
+ case CHIP_KAVERI:
++ case CHIP_LIVERPOOL:
+ adev->mode_info.num_hpd = 6;
+ adev->mode_info.num_dig = 7;
+ break;
+@@ -2768,7 +2793,12 @@ static int dce_v8_0_hw_init(void *handle)
+ dce_v8_0_hpd_init(adev);
+
+ for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
+- dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
++ // TODO (ps4patches): In original patches original disable was still here
++ // Maybe that is still needed
++ if (adev->asic_type == CHIP_LIVERPOOL || adev->asic_type == CHIP_GLADIUS)
++ dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], true);
++ else
++ dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
+ }
+
+ dce_v8_0_pageflip_interrupt_init(adev);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index 37b4a3db6360..d81187445ebe 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -90,6 +90,20 @@ MODULE_FIRMWARE("amdgpu/mullins_ce.bin");
+ MODULE_FIRMWARE("amdgpu/mullins_rlc.bin");
+ MODULE_FIRMWARE("amdgpu/mullins_mec.bin");
+
++MODULE_FIRMWARE("amdgpu/liverpool_pfp.bin");
++MODULE_FIRMWARE("amdgpu/liverpool_me.bin");
++MODULE_FIRMWARE("amdgpu/liverpool_ce.bin");
++MODULE_FIRMWARE("amdgpu/liverpool_rlc.bin");
++MODULE_FIRMWARE("amdgpu/liverpool_mec.bin");
++MODULE_FIRMWARE("amdgpu/liverpool_mec2.bin");
++
++MODULE_FIRMWARE("amdgpu/gladius_pfp.bin");
++MODULE_FIRMWARE("amdgpu/gladius_me.bin");
++MODULE_FIRMWARE("amdgpu/gladius_ce.bin");
++MODULE_FIRMWARE("amdgpu/gladius_rlc.bin");
++MODULE_FIRMWARE("amdgpu/gladius_mec.bin");
++MODULE_FIRMWARE("amdgpu/gladius_mec2.bin");
++
+ static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
+ {
+ {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
+@@ -882,6 +896,423 @@ static const u32 kalindi_rlc_save_restore_register_list[] =
+ (0x0e00 << 16) | (0x9600 >> 2),
+ };
+
++static const u32 liverpool_rlc_save_restore_register_list[] =
++{
++ (0x0600 << 16) | (0x98f4 >> 2),
++ 0x00000000,
++ (0x0680 << 16) | (0x98f4 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x98f8 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x9900 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xc260 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x90e8 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x3c000 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x3c00c >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8c1c >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x9700 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xcd20 >> 2),
++ 0x00000000,
++ (0x1e00 << 16) | (0xcd20 >> 2),
++ 0x00000000,
++ (0x4e00 << 16) | (0xcd20 >> 2),
++ 0x00000000,
++ (0x5e00 << 16) | (0xcd20 >> 2),
++ 0x00000000,
++ (0x6e00 << 16) | (0xcd20 >> 2),
++ 0x00000000,
++ (0x7e00 << 16) | (0xcd20 >> 2),
++ 0x00000000,
++ (0x8e00 << 16) | (0xcd20 >> 2),
++ 0x00000000,
++ (0x9e00 << 16) | (0xcd20 >> 2),
++ 0x00000000,
++ (0xae00 << 16) | (0xcd20 >> 2),
++ 0x00000000,
++ (0xbe00 << 16) | (0xcd20 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0x89bc >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0x89bc >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8900 >> 2),
++ 0x00000000,
++ 0x3,
++ (0x0e00 << 16) | (0x9834 >> 2),
++ 0x00000000,
++ (0x0000 << 16) | (0x30f00 >> 2),
++ 0x00000000,
++ (0x0001 << 16) | (0x30f00 >> 2),
++ 0x00000000,
++ (0x0002 << 16) | (0x30f00 >> 2),
++ 0x00000000,
++ (0x0003 << 16) | (0x30f00 >> 2),
++ 0x00000000,
++ (0x0080 << 16) | (0x30f00 >> 2),
++ 0x00000000,
++ (0x0081 << 16) | (0x30f00 >> 2),
++ 0x00000000,
++ (0x0082 << 16) | (0x30f00 >> 2),
++ 0x00000000,
++ (0x0083 << 16) | (0x30f00 >> 2),
++ 0x00000000,
++ (0x0000 << 16) | (0x30f04 >> 2),
++ 0x00000000,
++ (0x0001 << 16) | (0x30f04 >> 2),
++ 0x00000000,
++ (0x0002 << 16) | (0x30f04 >> 2),
++ 0x00000000,
++ (0x0003 << 16) | (0x30f04 >> 2),
++ 0x00000000,
++ (0x0080 << 16) | (0x30f04 >> 2),
++ 0x00000000,
++ (0x0081 << 16) | (0x30f04 >> 2),
++ 0x00000000,
++ (0x0082 << 16) | (0x30f04 >> 2),
++ 0x00000000,
++ (0x0083 << 16) | (0x30f04 >> 2),
++ 0x00000000,
++ (0x0000 << 16) | (0x30f08 >> 2),
++ 0x00000000,
++ (0x0001 << 16) | (0x30f08 >> 2),
++ 0x00000000,
++ (0x0002 << 16) | (0x30f08 >> 2),
++ 0x00000000,
++ (0x0003 << 16) | (0x30f08 >> 2),
++ 0x00000000,
++ (0x0080 << 16) | (0x30f08 >> 2),
++ 0x00000000,
++ (0x0081 << 16) | (0x30f08 >> 2),
++ 0x00000000,
++ (0x0082 << 16) | (0x30f08 >> 2),
++ 0x00000000,
++ (0x0083 << 16) | (0x30f08 >> 2),
++ 0x00000000,
++ (0x0000 << 16) | (0x30f0c >> 2),
++ 0x00000000,
++ (0x0001 << 16) | (0x30f0c >> 2),
++ 0x00000000,
++ (0x0002 << 16) | (0x30f0c >> 2),
++ 0x00000000,
++ (0x0003 << 16) | (0x30f0c >> 2),
++ 0x00000000,
++ (0x0080 << 16) | (0x30f0c >> 2),
++ 0x00000000,
++ (0x0081 << 16) | (0x30f0c >> 2),
++ 0x00000000,
++ (0x0082 << 16) | (0x30f0c >> 2),
++ 0x00000000,
++ (0x0083 << 16) | (0x30f0c >> 2),
++ 0x00000000,
++ (0x0600 << 16) | (0x9b7c >> 2),
++ 0x00000000,
++ (0x0680 << 16) | (0x9b7c >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8a14 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8a18 >> 2),
++ 0x00000000,
++ (0x0600 << 16) | (0x30a00 >> 2),
++ 0x00000000,
++ (0x0680 << 16) | (0x30a00 >> 2),
++ 0x00000000,
++ (0x1600 << 16) | (0x30a00 >> 2),
++ 0x00000000,
++ (0x1680 << 16) | (0x30a00 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8bf0 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8bcc >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8b24 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x30a04 >> 2),
++ 0x00000000,
++ (0x1e00 << 16) | (0x30a04 >> 2),
++ 0x00000000,
++ (0x0600 << 16) | (0x30a10 >> 2),
++ 0x00000000,
++ (0x0680 << 16) | (0x30a10 >> 2),
++ 0x00000000,
++ (0x1600 << 16) | (0x30a10 >> 2),
++ 0x00000000,
++ (0x1680 << 16) | (0x30a10 >> 2),
++ 0x00000000,
++ (0x0600 << 16) | (0x30a14 >> 2),
++ 0x00000000,
++ (0x0680 << 16) | (0x30a14 >> 2),
++ 0x00000000,
++ (0x1600 << 16) | (0x30a14 >> 2),
++ 0x00000000,
++ (0x1680 << 16) | (0x30a14 >> 2),
++ 0x00000000,
++ (0x0600 << 16) | (0x30a18 >> 2),
++ 0x00000000,
++ (0x0680 << 16) | (0x30a18 >> 2),
++ 0x00000000,
++ (0x1600 << 16) | (0x30a18 >> 2),
++ 0x00000000,
++ (0x1680 << 16) | (0x30a18 >> 2),
++ 0x00000000,
++ (0x0600 << 16) | (0x30a2c >> 2),
++ 0x00000000,
++ (0x0680 << 16) | (0x30a2c >> 2),
++ 0x00000000,
++ (0x1600 << 16) | (0x30a2c >> 2),
++ 0x00000000,
++ (0x1680 << 16) | (0x30a2c >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xc700 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xc704 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xc708 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xc768 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc770 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc770 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc774 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc774 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc778 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc778 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc77c >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc77c >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc780 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc780 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc784 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc784 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc788 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc788 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc78c >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc78c >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc790 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc790 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc794 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc794 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc798 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc798 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc79c >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc79c >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc7a0 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc7a0 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc7a4 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc7a4 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc7a8 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc7a8 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc7ac >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc7ac >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc7b0 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc7b0 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc7b4 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc7b4 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc7b8 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc7b8 >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0xc7bc >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0xc7bc >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x9100 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x3c010 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x92a8 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x92ac >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x92b0 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x92b4 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x92b8 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x92bc >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x92c0 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x92c4 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x92c8 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x92cc >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x92d0 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8c00 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8c04 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8c20 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8c38 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8c3c >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xae00 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x9604 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac08 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac0c >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac10 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac14 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac58 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac68 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac6c >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac70 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac74 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac78 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac7c >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac80 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac84 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac88 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xac8c >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x970c >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x9714 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x9718 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x971c >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x31068 >> 2),
++ 0x00000000,
++ (0x1e00 << 16) | (0x31068 >> 2),
++ 0x00000000,
++ (0x4e00 << 16) | (0x31068 >> 2),
++ 0x00000000,
++ (0x5e00 << 16) | (0x31068 >> 2),
++ 0x00000000,
++ (0x6e00 << 16) | (0x31068 >> 2),
++ 0x00000000,
++ (0x7e00 << 16) | (0x31068 >> 2),
++ 0x00000000,
++ (0x8e00 << 16) | (0x31068 >> 2),
++ 0x00000000,
++ (0x9e00 << 16) | (0x31068 >> 2),
++ 0x00000000,
++ (0xae00 << 16) | (0x31068 >> 2),
++ 0x00000000,
++ (0xbe00 << 16) | (0x31068 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xcd10 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0xcd14 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x88b0 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x88b4 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x88b8 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x88bc >> 2),
++ 0x00000000,
++ (0x0400 << 16) | (0x89c0 >> 2),
++ 0x00000000,
++ (0x0480 << 16) | (0x89c0 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x88c4 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x89d0 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x88d0 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x88d4 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x88d8 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8980 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8988 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x89b0 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x89b8 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x89a0 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x88c8 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x88cc >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x89b4 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x3e1fc >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x3c210 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x3c214 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x3c218 >> 2),
++ 0x00000000,
++ (0x0e00 << 16) | (0x8904 >> 2),
++ 0x00000000,
++ 1,
++ (0x0e00 << 16) | (0x8c34 >> 2),
++};
++
++// TODO (ps4patches): No Gladius save/restore list?
++
+ static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
+ static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
+ static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
+@@ -923,6 +1354,12 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
+ case CHIP_MULLINS:
+ chip_name = "mullins";
+ break;
++ case CHIP_LIVERPOOL:
++ chip_name = "liverpool";
++ break;
++ case CHIP_GLADIUS:
++ chip_name = "gladius";
++ break;
+ default: BUG();
+ }
+
+@@ -958,14 +1395,20 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
+ if (err)
+ goto out;
+
+- if (adev->asic_type == CHIP_KAVERI) {
++ if ((adev->asic_type == CHIP_KAVERI) ||
++ (adev->asic_type == CHIP_LIVERPOOL) ||
++ (adev->asic_type == CHIP_GLADIUS)) {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
+ err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
+- if (err)
++ {
++ pr_err("gfx7: Failed to open firmware \"%s\"\n", fw_name);
+ goto out;
++ }
+ err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
+- if (err)
++ {
++ pr_err("gfx7: Failed to validate ucode firmware \"%s\"\n", fw_name);
+ goto out;
++ }
+ }
+
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
+@@ -1218,6 +1661,151 @@ static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
+ if (reg_offset != 7)
+ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
+ break;
++
++ case CHIP_LIVERPOOL:
++ case CHIP_GLADIUS:
++ tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
++ tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
++ tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
++ tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
++ tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ TILE_SPLIT(split_equal_to_row_size));
++ tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
++ tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
++ tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ TILE_SPLIT(split_equal_to_row_size));
++ tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
++ tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
++ tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
++ tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
++ tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++ tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
++ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
++ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
++
++ macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_4_BANK));
++ macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_2_BANK));
++ macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ NUM_BANKS(ADDR_SURF_16_BANK));
++ macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_8_BANK));
++ macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_4_BANK));
++ macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
++ NUM_BANKS(ADDR_SURF_2_BANK));
++
++ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
++ WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
++ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
++ if (reg_offset != 7)
++ WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
++ break;
+ case CHIP_HAWAII:
+ tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+@@ -1660,6 +2248,17 @@ gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
+ *rconf |= 0x0;
+ *rconf1 |= 0x0;
+ break;
++ case CHIP_LIVERPOOL:
++ *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
++ RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
++ PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
++ SE_YSEL(2);
++ *rconf1 |= 0x0;
++ break;
++ case CHIP_GLADIUS:
++ *rconf |= 0x2a00161a;
++ *rconf1 |= 0x0000002e;
++ break;
+ default:
+ DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
+ break;
+@@ -2742,7 +3341,9 @@ static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
+ WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
+ WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
+
+- if (adev->asic_type == CHIP_KAVERI) {
++ if ((adev->asic_type == CHIP_KAVERI) ||
++ (adev->asic_type == CHIP_LIVERPOOL) ||
++ (adev->asic_type == CHIP_GLADIUS)) {
+ const struct gfx_firmware_header_v1_0 *mec2_hdr;
+
+ if (!adev->gfx.mec2_fw)
+@@ -3307,6 +3908,15 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
+ adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
+ adev->gfx.rlc.reg_list_size =
+ (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
++ } else if (adev->asic_type == CHIP_LIVERPOOL) {
++ adev->gfx.rlc.reg_list = liverpool_rlc_save_restore_register_list;
++ adev->gfx.rlc.reg_list_size =
++ (u32)ARRAY_SIZE(liverpool_rlc_save_restore_register_list);
++ } else if (adev->asic_type == CHIP_GLADIUS) {
++ adev->gfx.rlc.reg_list =
++ liverpool_rlc_save_restore_register_list;
++ adev->gfx.rlc.reg_list_size = (u32)ARRAY_SIZE(
++ liverpool_rlc_save_restore_register_list);
+ } else {
+ adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
+ adev->gfx.rlc.reg_list_size =
+@@ -4031,6 +4641,14 @@ static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
+ buffer[count++] = cpu_to_le32(0x3a00161a);
+ buffer[count++] = cpu_to_le32(0x0000002e);
+ break;
++ case CHIP_LIVERPOOL:
++ buffer[count++] = cpu_to_le32(0x2a00161a);
++ buffer[count++] = cpu_to_le32(0x00000000);
++ break;
++ case CHIP_GLADIUS:
++ buffer[count++] = cpu_to_le32(0x2a00161a);
++ buffer[count++] = cpu_to_le32(0x0000002e);
++ break;
+ default:
+ buffer[count++] = cpu_to_le32(0x00000000);
+ buffer[count++] = cpu_to_le32(0x00000000);
+@@ -4330,6 +4948,41 @@ static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
+ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
+ gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
+ break;
++ case CHIP_LIVERPOOL:
++ adev->gfx.config.max_shader_engines = 2; // Verified
++ adev->gfx.config.max_tile_pipes = 8; // Verified
++ adev->gfx.config.max_cu_per_sh = 9; // Probably OK
++ adev->gfx.config.max_sh_per_se = 1; // Verified
++ adev->gfx.config.max_backends_per_se = 1; // Probably OK?
++ adev->gfx.config.max_texture_channel_caches = 4; // ??
++ adev->gfx.config.max_gprs = 256;
++ adev->gfx.config.max_gs_threads = 32; // ??
++ adev->gfx.config.max_hw_contexts = 8;
++
++ adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
++ adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
++ adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
++ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
++ gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
++ break;
++
++ case CHIP_GLADIUS:
++ adev->gfx.config.max_shader_engines = 4; // Verified
++ adev->gfx.config.max_tile_pipes = 8; // Verified
++ adev->gfx.config.max_cu_per_sh = 9; // Probably OK
++ adev->gfx.config.max_sh_per_se = 1; // Verified
++ adev->gfx.config.max_backends_per_se = 2; // Probably OK?
++ adev->gfx.config.max_texture_channel_caches = 8; // ??
++ adev->gfx.config.max_gprs = 256;
++ adev->gfx.config.max_gs_threads = 32; // ??
++ adev->gfx.config.max_hw_contexts = 8;
++
++ adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
++ adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
++ adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
++ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
++ gb_addr_config = 0x10000000; //0x22011003; //0x12011003;
++ break;
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
+ default:
+@@ -4455,6 +5108,8 @@ static int gfx_v7_0_sw_init(void *handle)
+
+ switch (adev->asic_type) {
+ case CHIP_KAVERI:
++ case CHIP_LIVERPOOL:
++ case CHIP_GLADIUS:
+ adev->gfx.mec.num_mec = 2;
+ break;
+ case CHIP_BONAIRE:
+@@ -5166,7 +5821,9 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
+ unsigned disable_masks[4 * 2];
+ u32 ao_cu_num;
+
+- if (adev->flags & AMD_IS_APU)
++ if ((adev->flags & AMD_IS_APU) &&
++ (adev->asic_type != CHIP_LIVERPOOL) &&
++ (adev->asic_type != CHIP_GLADIUS))
+ ao_cu_num = 2;
+ else
+ ao_cu_num = adev->gfx.config.max_cu_per_sh;
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+index 63c47f61d0df..752b66d7d0df 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+@@ -150,6 +150,8 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
+ case CHIP_KAVERI:
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
++ case CHIP_LIVERPOOL:
++ case CHIP_GLADIUS:
+ return 0;
+ default: BUG();
+ }
+@@ -402,6 +404,10 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
+ adev->gmc.gart_size = 256ULL << 20;
+ break;
+ #ifdef CONFIG_DRM_AMDGPU_CIK
++ case CHIP_LIVERPOOL:
++ case CHIP_GLADIUS:
++ adev->gmc.gart_size = 512ULL << 20;
++ break;
+ case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
+ case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */
+ case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */
+@@ -688,6 +694,19 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
+ table_addr >> 12);
+ }
+
++ if (adev->asic_type == CHIP_LIVERPOOL || adev->asic_type == CHIP_GLADIUS) {
++ for (i = 2; i < 8; i++) {
++ WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR + i, 0);
++ WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR + i,
++ adev->vm_manager.max_pfn - 1);
++ }
++ for (i = 0; i < 8; i++) {
++ WREG32(mmVM_CONTEXT8_PAGE_TABLE_START_ADDR + i, 0);
++ WREG32(mmVM_CONTEXT8_PAGE_TABLE_END_ADDR + i,
++ adev->vm_manager.max_pfn - 1);
++ }
++ }
++
+ /* enable context1-15 */
+ WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
+ (u32)(adev->dummy_page_addr >> 12));
+diff --git a/drivers/gpu/drm/amd/amdgpu/ps4_bridge.c b/drivers/gpu/drm/amd/amdgpu/ps4_bridge.c
+new file mode 100644
+index 000000000000..86af15c134c4
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/ps4_bridge.c
+@@ -0,0 +1,776 @@
++/*
++ * Panasonic MN86471A DP->HDMI bridge driver (via PS4 Aeolia ICC interface)
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <asm/ps4.h>
++
++#include <drm/drm_crtc.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/drm_atomic_helper.h>
++#include <drm/drm_edid.h>
++
++#include <drm/drm_bridge.h>
++#include <drm/drm_encoder.h>
++
++#include <linux/i2c.h>
++#include <linux/i2c-algo-bit.h>
++
++
++#include "amdgpu.h"
++#include "amdgpu_mode.h"
++#include "atombios_dp.h"
++#include "ObjectID.h"
++
++#define CMD_READ 1, 1
++#define CMD_WRITE 2, 2
++#define CMD_MASK 2, 3
++#define CMD_DELAY 3, 1
++#define CMD_WAIT_SET 3, 2
++#define CMD_WAIT_CLEAR 3, 3
++
++#define TSYSCTRL 0x7005
++#define TSYSCTRL_HDMI BIT(7)
++
++#define TSRST 0x7006
++#define TSRST_AVCSRST BIT(0)
++#define TSRST_ENCSRST BIT(1)
++#define TSRST_FIFOSRST BIT(2)
++#define TSRST_CCSRST BIT(3)
++#define TSRST_HDCPSRST BIT(4)
++#define TSRST_AUDSRST BIT(6)
++#define TSRST_VIFSRST BIT(7)
++
++#define TMONREG 0x7008
++#define TMONREG_HPD BIT(3)
++
++#define TDPCMODE 0x7009
++
++
++#define UPDCTRL 0x7011
++#define UPDCTRL_ALLUPD BIT(7)
++#define UPDCTRL_AVIIUPD BIT(6)
++#define UPDCTRL_AUDIUPD BIT(5)
++#define UPDCTRL_CLKUPD BIT(4)
++#define UPDCTRL_HVSIUPD BIT(3)
++#define UPDCTRL_VIFUPD BIT(2)
++#define UPDCTRL_AUDUPD BIT(1)
++#define UPDCTRL_CSCUPD BIT(0)
++
++
++#define VINCNT 0x7040
++#define VINCNT_VIF_FILEN BIT(6)
++
++#define VMUTECNT 0x705f
++#define VMUTECNT_CCVMUTE BIT(7)
++#define VMUTECNT_DUMON BIT(6)
++#define VMUTECNT_LINEWIDTH_80 (0<<4)
++#define VMUTECNT_LINEWIDTH_90 (1<<4)
++#define VMUTECNT_LINEWIDTH_180 (2<<4)
++#define VMUTECNT_LINEWIDTH_360 (3<<4)
++#define VMUTECNT_VMUTE_MUTE_ASYNC 1
++#define VMUTECNT_VMUTE_MUTE_NORMAL 2
++#define VMUTECNT_VMUTE_MUTE_RAMPA 4
++#define VMUTECNT_VMUTE_MUTE_RAMPB 8
++#define VMUTECNT_VMUTE_MUTE_COLORBAR_RGB 10
++#define VMUTECNT_VMUTE_MUTE_TOGGLE 12
++#define VMUTECNT_VMUTE_MUTE_COLORBAR_YCBCR 14
++
++#define CSCMOD 0x70c0
++#define C420SET 0x70c2
++#define OUTWSET 0x70c3
++
++#define PKTENA 0x7202
++
++#define INFENA 0x7203
++#define INFENA_AVIEN BIT(6)
++
++#define AKESTA 0x7a84
++#define AKESTA_BUSY BIT(0)
++
++#define AKESRST 0x7a88
++
++#define HDCPEN 0x7a8b
++#define HDCPEN_NONE 0x00
++#define HDCPEN_ENC_EN 0x03
++#define HDCPEN_ENC_DIS 0x05
++
++#define PCI_DEVICE_ID_CUH_11XX 0x9920
++#define PCI_DEVICE_ID_CUH_12XX 0x9922
++#define PCI_DEVICE_ID_CUH_2XXX 0x9923
++#define PCI_DEVICE_ID_CUH_7XXX 0x9924
++
++struct edid *drm_get_edid(struct drm_connector *connector,
++ struct i2c_adapter *adapter);
++
++struct i2c_cmd_hdr {
++ u8 major;
++ u8 length;
++ u8 minor;
++ u8 count;
++} __packed;
++
++struct i2c_cmdqueue {
++ struct {
++ u8 code;
++ u16 length;
++ u8 count;
++ u8 cmdbuf[0x7ec];
++ } __packed req;
++ struct {
++ u8 res1, res2;
++ u8 unk1, unk2;
++ u8 count;
++ u8 databuf[0x7eb];
++ } __packed reply;
++
++ u8 *p;
++ struct i2c_cmd_hdr *cmd;
++};
++
++struct ps4_bridge {
++ struct drm_connector *connector;
++ struct drm_encoder *encoder;
++ struct drm_bridge bridge;
++ struct i2c_cmdqueue cq;
++ struct mutex mutex;
++
++ int mode;
++};
++
++/* this should really be taken care of by the connector, but that is currently
++ * contained/owned by radeon_connector so just use a global for now */
++static struct ps4_bridge g_bridge = {
++ .mutex = __MUTEX_INITIALIZER(g_bridge.mutex)
++};
++
++static void cq_init(struct i2c_cmdqueue *q, u8 code)
++{
++ q->req.code = code;
++ q->req.count = 0;
++ q->p = q->req.cmdbuf;
++ q->cmd = NULL;
++}
++
++static void cq_cmd(struct i2c_cmdqueue *q, u8 major, u8 minor)
++{
++ if (!q->cmd || q->cmd->major != major || q->cmd->minor != minor) {
++ if (q->cmd)
++ q->cmd->length = q->p - (u8 *)q->cmd;
++ q->cmd = (struct i2c_cmd_hdr *)q->p;
++ q->cmd->major = major;
++ q->cmd->minor = minor;
++ q->cmd->length = 0;
++ q->cmd->count = 1;
++ q->req.count += 1;
++ q->p += sizeof(*q->cmd);
++ } else {
++ q->cmd->count += 1;
++ }
++}
++
++static int cq_exec(struct i2c_cmdqueue *q)
++{
++ int res;
++
++ if (!q->cmd)
++ return 0;
++
++ q->cmd->length = q->p - (u8 *)q->cmd;
++ q->req.length = q->p - (u8 *)&q->req;
++
++ res = apcie_icc_cmd(0x10, 0, &q->req, q->req.length,
++ &q->reply, sizeof(q->reply));
++
++ if (res < 5) {
++ DRM_ERROR("icc i2c commandqueue failed: %d\n", res);
++ return -EIO;
++ }
++ if (q->reply.res1 != 0 || q->reply.res2) {
++ DRM_ERROR("icc i2c commandqueue failed: %d, %d\n",
++ q->reply.res1, q->reply.res2);
++ return -EIO;
++ }
++
++ return res;
++}
++
++static void cq_read(struct i2c_cmdqueue *q, u16 addr, u8 count)
++{
++ cq_cmd(q, CMD_READ);
++ *q->p++ = count;
++ *q->p++ = addr >> 8;
++ *q->p++ = addr & 0xff;
++ *q->p++ = 0;
++}
++
++static void cq_writereg(struct i2c_cmdqueue *q, u16 addr, u8 data)
++{
++ cq_cmd(q, CMD_WRITE);
++ *q->p++ = 1;
++ *q->p++ = addr >> 8;
++ *q->p++ = addr & 0xff;
++ *q->p++ = data;
++}
++
++#if 0
++static void cq_write(struct i2c_cmdqueue *q, u16 addr, u8 *data, u8 count)
++{
++ cq_cmd(q, CMD_WRITE);
++ *q->p++ = count;
++ *q->p++ = addr >> 8;
++ *q->p++ = addr & 0xff;
++ while (count--)
++ *q->p++ = *data++;
++}
++#endif
++
++static void cq_mask(struct i2c_cmdqueue *q, u16 addr, u8 value, u8 mask)
++{
++ cq_cmd(q, CMD_MASK);
++ *q->p++ = 1;
++ *q->p++ = addr >> 8;
++ *q->p++ = addr & 0xff;
++ *q->p++ = value;
++ *q->p++ = mask;
++}
++
++#if 1
++static void cq_delay(struct i2c_cmdqueue *q, u16 time)
++{
++ cq_cmd(q, CMD_DELAY);
++ *q->p++ = 0;
++ *q->p++ = time & 0xff;
++ *q->p++ = time>>8;
++ *q->p++ = 0;
++}
++#endif
++
++static void cq_wait_set(struct i2c_cmdqueue *q, u16 addr, u8 mask)
++{
++ cq_cmd(q, CMD_WAIT_SET);
++ *q->p++ = 0;
++ *q->p++ = addr >> 8;
++ *q->p++ = addr & 0xff;
++ *q->p++ = mask;
++}
++
++static void cq_wait_clear(struct i2c_cmdqueue *q, u16 addr, u8 mask)
++{
++ cq_cmd(q, CMD_WAIT_CLEAR);
++ *q->p++ = 0;
++ *q->p++ = addr >> 8;
++ *q->p++ = addr & 0xff;
++ *q->p++ = mask;
++}
++
++static inline struct ps4_bridge *
++ bridge_to_ps4_bridge(struct drm_bridge *bridge)
++{
++ return container_of(bridge, struct ps4_bridge, bridge);
++}
++
++void ps4_bridge_mode_set(struct drm_bridge *bridge,
++ const struct drm_display_mode *mode,
++ const struct drm_display_mode *adjusted_mode)
++{
++ struct ps4_bridge *mn_bridge = bridge_to_ps4_bridge(bridge);
++
++ /* This gets called before pre_enable/enable, so we just stash
++ * the vic ID for later */
++ mn_bridge->mode = drm_match_cea_mode(adjusted_mode);
++ DRM_DEBUG_KMS("vic mode: %d\n", mn_bridge->mode);
++ if (!mn_bridge->mode) {
++ DRM_ERROR("attempted to set non-CEA mode\n");
++ }
++}
++
++static void ps4_bridge_pre_enable(struct drm_bridge *bridge)
++{
++ struct ps4_bridge *mn_bridge = bridge_to_ps4_bridge(bridge);
++ DRM_DEBUG_KMS("ps4_bridge_pre_enable\n");
++ DRM_DEBUG("Enable ps4_bridge_pre_enable\n");
++ mutex_lock(&mn_bridge->mutex);
++ cq_init(&mn_bridge->cq, 4);
++
++#if 0
++ /* No idea. DP stuff probably. This borks for some reason. Meh. */
++ cq_writereg(&mn_bridge->cq, 0x7657,0xff);
++ cq_writereg(&mn_bridge->cq, 0x76a5,0x80);
++ cq_writereg(&mn_bridge->cq, 0x76a6,0x04);
++ cq_writereg(&mn_bridge->cq, 0x7601,0x0a);
++ cq_writereg(&mn_bridge->cq, 0x7602,0x84);
++ cq_writereg(&mn_bridge->cq, 0x7603,0x00);
++ cq_writereg(&mn_bridge->cq, 0x76a8,0x09);
++ cq_writereg(&mn_bridge->cq, 0x76ae,0xd1);
++ cq_writereg(&mn_bridge->cq, 0x76af,0x50);
++ cq_writereg(&mn_bridge->cq, 0x76b0,0x70);
++ cq_writereg(&mn_bridge->cq, 0x76b1,0xb0);
++ cq_writereg(&mn_bridge->cq, 0x76b2,0xf0);
++ cq_writereg(&mn_bridge->cq, 0x76db,0x00);
++ cq_writereg(&mn_bridge->cq, 0x76dc,0x64);
++ cq_writereg(&mn_bridge->cq, 0x76dd,0x22);
++ cq_writereg(&mn_bridge->cq, 0x76e4,0x00);
++ cq_writereg(&mn_bridge->cq, 0x76e6,0x1e); /* 0 for (DP?) scramble off */
++ cq_writereg(&mn_bridge->cq, 0x7670,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7671,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7672,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7673,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7668,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7669,0xff);
++ cq_writereg(&mn_bridge->cq, 0x766a,0xff);
++ cq_writereg(&mn_bridge->cq, 0x766b,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7655,0x04);
++ cq_writereg(&mn_bridge->cq, 0x7007,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7098,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7099,0x00);
++ cq_writereg(&mn_bridge->cq, 0x709a,0x0f);
++ cq_writereg(&mn_bridge->cq, 0x709b,0x00);
++ cq_writereg(&mn_bridge->cq, 0x709c,0x50);
++ cq_writereg(&mn_bridge->cq, 0x709d,0x00);
++ cq_writereg(&mn_bridge->cq, 0x709e,0x00);
++ cq_writereg(&mn_bridge->cq, 0x709f,0xd0);
++ cq_writereg(&mn_bridge->cq, 0x7a9c,0x2e);
++ cq_writereg(&mn_bridge->cq, 0x7021,0x04);
++ cq_writereg(&mn_bridge->cq, 0x7028,0x00);
++ cq_writereg(&mn_bridge->cq, 0x7030,0xa3);
++ cq_writereg(&mn_bridge->cq, 0x7016,0x04);
++#endif
++
++ /* Disable InfoFrames */
++ cq_writereg(&mn_bridge->cq, INFENA, 0x00);
++ /* Reset HDCP */
++ cq_writereg(&mn_bridge->cq, TSRST, TSRST_ENCSRST | TSRST_HDCPSRST);
++ /* Disable HDCP flag */
++ cq_writereg(&mn_bridge->cq, TSRST, HDCPEN_ENC_DIS);
++ /* HDCP AKE reset */
++ cq_writereg(&mn_bridge->cq, AKESRST, 0xff);
++ /* Wait AKE busy */
++ cq_wait_clear(&mn_bridge->cq, AKESTA, AKESTA_BUSY);
++
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("failed to run pre-enable sequence");
++ }
++ mutex_unlock(&mn_bridge->mutex);
++}
++
++static void ps4_bridge_enable(struct drm_bridge *bridge)
++{
++ struct ps4_bridge *mn_bridge = bridge_to_ps4_bridge(bridge);
++ struct drm_connector *connector = mn_bridge->connector;
++ struct drm_device *dev = connector->dev;
++ struct pci_dev *pdev = to_pci_dev(dev->dev);
++ u8 dp[3];
++
++ DRM_DEBUG("Enable PS4_BRIDGE_ENABLE\n");
++ if (!mn_bridge->mode) {
++ DRM_ERROR("mode not available\n");
++ return;
++ }
++
++ if(pdev->vendor != PCI_VENDOR_ID_ATI) {
++ DRM_ERROR("Invalid vendor: %04x", pdev->vendor);
++ return;
++ }
++
++ DRM_DEBUG_KMS("ps4_bridge_enable (mode: %d)\n", mn_bridge->mode);
++
++ /* Here come the dragons */
++
++ if(pdev->device == PCI_DEVICE_ID_CUH_11XX)
++ {
++ /* Panasonic MN86471A */
++ mutex_lock(&mn_bridge->mutex);
++ cq_init(&mn_bridge->cq, 4);
++
++ /* Read DisplayPort status (?) */
++ cq_read(&mn_bridge->cq, 0x76e1, 3);
++ if (cq_exec(&mn_bridge->cq) < 11) {
++ mutex_unlock(&mn_bridge->mutex);
++ DRM_ERROR("could not read DP status");
++ return;
++ }
++ memcpy(dp, &mn_bridge->cq.reply.databuf[3], 3);
++
++ cq_init(&mn_bridge->cq, 4);
++
++ /* Wait for DP lane status */
++ cq_wait_set(&mn_bridge->cq, 0x761e, 0x77);
++ cq_wait_set(&mn_bridge->cq, 0x761f, 0x77);
++ /* Wait for ?? */
++ cq_wait_set(&mn_bridge->cq, 0x7669, 0x01);
++ cq_writereg(&mn_bridge->cq, 0x76d9, (dp[0] & 0x1f) | (dp[0] << 5));
++ cq_writereg(&mn_bridge->cq, 0x76da, (dp[1] & 0x7c) | ((dp[0] >> 3) & 3) | ((dp[1] << 5) & 0x80));
++ cq_writereg(&mn_bridge->cq, 0x76db, 0x80 | ((dp[1] >> 3) & 0xf));
++ cq_writereg(&mn_bridge->cq, 0x76e4, 0x01);
++ cq_writereg(&mn_bridge->cq, TSYSCTRL, TSYSCTRL_HDMI);
++ cq_writereg(&mn_bridge->cq, VINCNT, VINCNT_VIF_FILEN);
++ cq_writereg(&mn_bridge->cq, 0x7071, 0);
++ cq_writereg(&mn_bridge->cq, 0x7062, mn_bridge->mode);
++ cq_writereg(&mn_bridge->cq, 0x765a, 0);
++ cq_writereg(&mn_bridge->cq, 0x7062, mn_bridge->mode | 0x80);
++ cq_writereg(&mn_bridge->cq, 0x7215, 0x28); /* aspect */
++ cq_writereg(&mn_bridge->cq, 0x7217, mn_bridge->mode);
++ cq_writereg(&mn_bridge->cq, 0x7218, 0);
++ cq_writereg(&mn_bridge->cq, CSCMOD, 0xdc);
++ cq_writereg(&mn_bridge->cq, C420SET, 0xaa);
++ cq_writereg(&mn_bridge->cq, TDPCMODE, 0x4a);
++ cq_writereg(&mn_bridge->cq, OUTWSET, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x70c4, 0x08);
++ cq_writereg(&mn_bridge->cq, 0x70c5, 0x08);
++ cq_writereg(&mn_bridge->cq, 0x7096, 0xff);
++ cq_writereg(&mn_bridge->cq, 0x7027, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7020, 0x20);
++ cq_writereg(&mn_bridge->cq, 0x700b, 0x01);
++ cq_writereg(&mn_bridge->cq, PKTENA, 0x20);
++ cq_writereg(&mn_bridge->cq, 0x7096, 0xff);
++ cq_writereg(&mn_bridge->cq, INFENA, INFENA_AVIEN);
++ cq_writereg(&mn_bridge->cq, UPDCTRL, UPDCTRL_ALLUPD | UPDCTRL_AVIIUPD |
++ UPDCTRL_CLKUPD | UPDCTRL_VIFUPD |
++ UPDCTRL_CSCUPD);
++ cq_wait_set(&mn_bridge->cq, 0x7096, 0x80);
++
++ cq_mask(&mn_bridge->cq, 0x7216, 0x00, 0x80);
++ cq_writereg(&mn_bridge->cq, 0x7218, 0x00);
++
++ cq_writereg(&mn_bridge->cq, 0x7096, 0xff);
++ cq_writereg(&mn_bridge->cq, VMUTECNT, VMUTECNT_LINEWIDTH_90 | VMUTECNT_VMUTE_MUTE_NORMAL);
++ cq_writereg(&mn_bridge->cq, 0x7016, 0x04);
++ cq_writereg(&mn_bridge->cq, 0x7a88, 0xff);
++ cq_writereg(&mn_bridge->cq, 0x7a83, 0x88);
++ cq_writereg(&mn_bridge->cq, 0x7204, 0x40);
++
++ cq_wait_set(&mn_bridge->cq, 0x7096, 0x80);
++
++ cq_writereg(&mn_bridge->cq, 0x7006, 0x02);
++ cq_writereg(&mn_bridge->cq, 0x7020, 0x21);
++ cq_writereg(&mn_bridge->cq, 0x7a8b, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7020, 0x21);
++
++ cq_writereg(&mn_bridge->cq, VMUTECNT, VMUTECNT_LINEWIDTH_90);
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("Failed to configure ps4-bridge (MN86471A) mode\n");
++ }
++ #if 1
++ // preinit
++ cq_init(&mn_bridge->cq, 4);
++ cq_writereg(&mn_bridge->cq,0x70b3, 0x00);
++ cq_writereg(&mn_bridge->cq,0x70b7, 0x0b);
++ cq_writereg(&mn_bridge->cq,0x70a8, 0x24);
++
++ cq_mask(&mn_bridge->cq,0x70b9, 0x06, 0x06);
++ cq_mask(&mn_bridge->cq,0x70b6, 0x02, 0x0f);
++ cq_mask(&mn_bridge->cq,0x70ba, 0x40, 0x70);
++ cq_mask(&mn_bridge->cq,0x70b2, 0x20, 0xe0);
++ cq_mask(&mn_bridge->cq,0x7257, 0x00, 0xff);
++ cq_mask(&mn_bridge->cq,0x70b0, 0x01, 0x21);
++ cq_mask(&mn_bridge->cq,0x70ba, 0x00, 0x88);
++ cq_mask(&mn_bridge->cq,0x70b9, 0x01, 0x01);
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("failed to run enable MN86471A hdmi audio seq. 0");
++ }
++
++ cq_init(&mn_bridge->cq, 4);
++ cq_writereg(&mn_bridge->cq,0x7ed8, 0x01);
++
++ cq_mask(&mn_bridge->cq,0x70b4, 0x00, 0x3e);
++ cq_mask(&mn_bridge->cq,0x70b5, 0x79, 0xff);
++ cq_mask(&mn_bridge->cq,0x70ab, 0x00, 0xff);
++ cq_mask(&mn_bridge->cq,0x70b6, 0x02, 0x3f);
++ cq_mask(&mn_bridge->cq,0x70b7, 0x0b, 0x0f);
++ cq_mask(&mn_bridge->cq,0x70ac, 0x00, 0xff);
++ cq_mask(&mn_bridge->cq,0x70bd, 0x00, 0xff);
++
++ cq_writereg(&mn_bridge->cq, 0x7204, 0x10);
++ cq_writereg(&mn_bridge->cq,0x7011, 0xa2);
++
++ cq_wait_set(&mn_bridge->cq,0x7096, 0x80);
++ cq_writereg(&mn_bridge->cq,0x7096, 0xff);
++
++ cq_mask(&mn_bridge->cq,0x7203, 0x10, 0x10);
++ cq_writereg(&mn_bridge->cq,0x70b1, 0xc0);
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("failed to run enable hdmi MN86471A audio seq. 1");
++ }
++ #endif
++ mutex_unlock(&mn_bridge->mutex);
++ }
++ else
++ {
++ /* Panasonic MN864729 */
++ mutex_lock(&mn_bridge->mutex);
++ cq_init(&mn_bridge->cq, 4);
++ cq_mask(&mn_bridge->cq, 0x6005, 0x01, 0x01);
++ cq_writereg(&mn_bridge->cq, 0x6a03, 0x47);
++
++ /* Wait for DP lane status */
++ cq_wait_set(&mn_bridge->cq, 0x60f8, 0xff);
++ cq_wait_set(&mn_bridge->cq, 0x60f9, 0x01);
++ cq_writereg(&mn_bridge->cq, 0x6a01, 0x4d);
++ cq_wait_set(&mn_bridge->cq, 0x60f9, 0x1a);
++
++ cq_mask(&mn_bridge->cq, 0x1e00, 0x00, 0x21);
++ cq_mask(&mn_bridge->cq, 0x1e02, 0x00, 0x70);
++ // 03 08 01 01 00 2c 01 00
++ cq_delay(&mn_bridge->cq, 0x012c);
++ cq_writereg(&mn_bridge->cq, 0x6020, 0x00);
++ cq_delay(&mn_bridge->cq, 0x0032);
++ cq_writereg(&mn_bridge->cq, 0x7402, 0x1c);
++ cq_writereg(&mn_bridge->cq, 0x6020, 0x04);
++ cq_writereg(&mn_bridge->cq, TSYSCTRL, TSYSCTRL_HDMI);
++ cq_writereg(&mn_bridge->cq, 0x10c7, 0x38);
++ cq_writereg(&mn_bridge->cq, 0x1e02, 0x88);
++ cq_writereg(&mn_bridge->cq, 0x1e00, 0x66);
++ cq_writereg(&mn_bridge->cq, 0x100c, 0x01);
++ cq_writereg(&mn_bridge->cq, TSYSCTRL, TSYSCTRL_HDMI);
++
++ cq_writereg(&mn_bridge->cq, 0x7009, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7040, 0x42);
++ cq_writereg(&mn_bridge->cq, 0x7225, 0x28);
++ cq_writereg(&mn_bridge->cq, 0x7227, mn_bridge->mode);
++ cq_writereg(&mn_bridge->cq, 0x7228, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7070, mn_bridge->mode);
++ cq_writereg(&mn_bridge->cq, 0x7071, mn_bridge->mode | 0x80);
++ cq_writereg(&mn_bridge->cq, 0x7072, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7073, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7074, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7075, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x70c4, 0x0a);
++ cq_writereg(&mn_bridge->cq, 0x70c5, 0x0a);
++ cq_writereg(&mn_bridge->cq, 0x70c2, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x70fe, 0x12);
++ cq_writereg(&mn_bridge->cq, 0x70c3, 0x10);
++
++ if(pdev->device == PCI_DEVICE_ID_CUH_12XX) {
++ /* newer ps4 phats need here 0x03 idk why. */
++ cq_writereg(&mn_bridge->cq, 0x10c5, 0x03);
++ } else {
++ cq_writereg(&mn_bridge->cq, 0x10c5, 0x00);
++ }
++
++ cq_writereg(&mn_bridge->cq, 0x10f6, 0xff);
++ cq_writereg(&mn_bridge->cq, 0x7202, 0x20);
++ cq_writereg(&mn_bridge->cq, 0x7203, 0x60);
++ cq_writereg(&mn_bridge->cq, 0x7011, 0xd5);
++ //cq_writereg(&mn_bridge->cq, 0x7a00, 0x0e);
++
++ cq_wait_set(&mn_bridge->cq, 0x10f6, 0x80);
++ cq_mask(&mn_bridge->cq, 0x7226, 0x00, 0x80);
++ cq_mask(&mn_bridge->cq, 0x7228, 0x00, 0xFF);
++ cq_delay(&mn_bridge->cq, 0x012c);
++ cq_writereg(&mn_bridge->cq, 0x7204, 0x40);
++ cq_wait_clear(&mn_bridge->cq, 0x7204, 0x40);
++ cq_writereg(&mn_bridge->cq, 0x7a8b, 0x05);
++ cq_mask(&mn_bridge->cq, 0x1e02, 0x70, 0x70);
++ cq_mask(&mn_bridge->cq, 0x1034, 0x02, 0x02);
++ cq_mask(&mn_bridge->cq, 0x1e00, 0x01, 0x01);
++ cq_writereg(&mn_bridge->cq, VMUTECNT, VMUTECNT_LINEWIDTH_90);
++ cq_writereg(&mn_bridge->cq, HDCPEN, 0x00);
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("Failed to configure ps4-bridge (MN864729) mode\n");
++ }
++ #if 1
++ // AUDIO preinit
++ cq_init(&mn_bridge->cq, 4);
++ cq_writereg(&mn_bridge->cq,0x70aa, 0x00);
++ cq_writereg(&mn_bridge->cq,0x70af, 0x07);
++ cq_writereg(&mn_bridge->cq,0x70a9, 0x5a);
++
++ cq_mask(&mn_bridge->cq,0x70af, 0x06, 0x06);
++ cq_mask(&mn_bridge->cq,0x70af, 0x02, 0x0f);
++ cq_mask(&mn_bridge->cq,0x70b3, 0x02, 0x0f);
++ cq_mask(&mn_bridge->cq,0x70ae, 0x80, 0xe0);
++ cq_mask(&mn_bridge->cq,0x70ae, 0x01, 0x07);
++ cq_mask(&mn_bridge->cq,0x70ac, 0x01, 0x21);
++ cq_mask(&mn_bridge->cq,0x70ab, 0x80, 0x88);
++ cq_mask(&mn_bridge->cq,0x70a9, 0x01, 0x01);
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("failed to run enable hdmi audio seq. 0");
++ }
++
++ cq_init(&mn_bridge->cq, 4);
++ cq_writereg(&mn_bridge->cq,0x70b0, 0x01);
++ cq_mask(&mn_bridge->cq,0x70b0, 0x00, 0xff);
++ cq_mask(&mn_bridge->cq,0x70b1, 0x79, 0xff);
++ cq_mask(&mn_bridge->cq,0x70b2, 0x00, 0xff);
++ cq_mask(&mn_bridge->cq,0x70b3, 0x02, 0xff);
++ cq_mask(&mn_bridge->cq,0x70b4, 0x0b, 0x0f);
++ cq_mask(&mn_bridge->cq,0x70b5, 0x00, 0xff);
++ cq_mask(&mn_bridge->cq,0x70b6, 0x00, 0xff);
++ cq_writereg(&mn_bridge->cq,0x10f6, 0xff);
++ cq_writereg(&mn_bridge->cq,0x7011, 0xa2);
++ cq_wait_set(&mn_bridge->cq,0x10f6, 0xa2);
++ cq_mask(&mn_bridge->cq,0x7267, 0x00, 0xff);
++ cq_writereg(&mn_bridge->cq,0x7204, 0x10);
++ cq_wait_clear(&mn_bridge->cq,0x7204, 0x10);
++ cq_writereg(&mn_bridge->cq,0x10f6, 0xff);
++ cq_mask(&mn_bridge->cq,0x7203, 0x10, 0x10);
++ cq_writereg(&mn_bridge->cq,0x70a8, 0xc0);
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("failed to run enable hdmi audio seq. 1");
++ }
++ #endif
++ mutex_unlock(&mn_bridge->mutex);
++ }
++
++}
++
++static void ps4_bridge_disable(struct drm_bridge *bridge)
++{
++ struct ps4_bridge *mn_bridge = bridge_to_ps4_bridge(bridge);
++ DRM_DEBUG_KMS("ps4_bridge_disable\n");
++
++ mutex_lock(&mn_bridge->mutex);
++ cq_init(&mn_bridge->cq, 4);
++ cq_writereg(&mn_bridge->cq, VMUTECNT, VMUTECNT_LINEWIDTH_90 | VMUTECNT_VMUTE_MUTE_NORMAL);
++ cq_writereg(&mn_bridge->cq, INFENA, 0x00);
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("Failed to disable bridge\n");
++ }
++ mutex_unlock(&mn_bridge->mutex);
++}
++
++static void ps4_bridge_post_disable(struct drm_bridge *bridge)
++{
++ /* struct ps4_bridge *mn_bridge = bridge_to_mn864729(bridge); */
++ DRM_DEBUG_KMS("ps4_bridge_post_disable\n");
++}
++
++/* Hardcoded modes, since we don't really know how to do custom modes yet.
++ * Other CEA modes *should* work (and are allowed if externally added) */
++
++// TODO (ps4patches): Apparently the vrefresh option is calculated on the fly now
++// Check if this actually works.
++
++/* 1 - 640x480@60Hz */
++static const struct drm_display_mode mode_480p = {
++ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
++ 752, 800, 0, 480, 490, 492, 525, 0,
++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3
++};
++/* 4 - 1280x720@60Hz */
++static const struct drm_display_mode mode_720p = {
++ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
++ 1430, 1650, 0, 720, 725, 730, 750, 0,
++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9
++};
++/* 16 - 1920x1080@60Hz */
++static const struct drm_display_mode mode_1080p = {
++ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
++ 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9
++};
++
++int ps4_bridge_get_modes(struct drm_connector *connector)
++{
++ struct drm_device *dev = connector->dev;
++ struct drm_display_mode *newmode;
++ DRM_DEBUG_KMS("ps4_bridge_get_modes\n");
++
++ newmode = drm_mode_duplicate(dev, &mode_1080p);
++ drm_mode_probed_add(connector, newmode);
++
++ //newmode = drm_mode_duplicate(dev, &mode_720p);
++ //drm_mode_probed_add(connector, newmode);
++ //newmode = drm_mode_duplicate(dev, &mode_480p);
++ //drm_mode_probed_add(connector, newmode);
++
++ drm_connector_update_edid_property(connector, NULL);
++
++ return 0;
++}
++
++enum drm_connector_status ps4_bridge_detect(struct drm_connector *connector,
++ bool force)
++{
++ struct ps4_bridge *mn_bridge = &g_bridge;
++ u8 reg;
++
++ struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
++ struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
++
++ amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
++ amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
++
++ mutex_lock(&mn_bridge->mutex);
++ cq_init(&mn_bridge->cq, 4);
++ cq_read(&mn_bridge->cq, TMONREG, 1);
++ if (cq_exec(&mn_bridge->cq) < 9) {
++ mutex_unlock(&mn_bridge->mutex);
++ DRM_ERROR("could not read TMONREG");
++ return connector_status_disconnected;
++ }
++ reg = mn_bridge->cq.reply.databuf[3];
++ mutex_unlock(&mn_bridge->mutex);
++
++ DRM_DEBUG_KMS("TMONREG=0x%02x\n", reg);
++
++ if (reg & TMONREG_HPD)
++ return connector_status_connected;
++ else
++ return connector_status_disconnected;
++}
++
++int ps4_bridge_mode_valid(struct drm_connector *connector,
++ struct drm_display_mode *mode)
++{
++ int vic = drm_match_cea_mode(mode);
++
++ /* Allow anything that we can match up to a VIC (CEA modes) */
++ if (!vic || (vic != 16 && vic != 4)) {
++ return MODE_BAD;
++ }
++
++ return MODE_OK;
++}
++
++static int ps4_bridge_attach(struct drm_bridge *bridge,
++ enum drm_bridge_attach_flags flags)
++{
++ // TODO (ps4patches): Why is this in comments?
++ /* struct ps4_bridge *mn_bridge = bridge_to_ps4_bridge(bridge); */
++
++ return 0;
++}
++
++static struct drm_bridge_funcs ps4_bridge_funcs = {
++ .pre_enable = ps4_bridge_pre_enable,
++ .enable = ps4_bridge_enable,
++ .disable = ps4_bridge_disable,
++ .post_disable = ps4_bridge_post_disable,
++ .attach = ps4_bridge_attach,
++ .mode_set = ps4_bridge_mode_set,
++};
++
++int ps4_bridge_register(struct drm_connector *connector,
++ struct drm_encoder *encoder)
++{
++ int ret;
++ struct ps4_bridge *mn_bridge = &g_bridge;
++
++ mn_bridge->encoder = encoder;
++ mn_bridge->connector = connector;
++ mn_bridge->bridge.funcs = &ps4_bridge_funcs;
++ ret = drm_bridge_attach(mn_bridge->encoder, &mn_bridge->bridge, NULL, 0);
++ if (ret) {
++ DRM_ERROR("Failed to initialize bridge with drm\n");
++ return -EINVAL;
++ }
++
++ //encoder->bridge = &mn_bridge->bridge;
++ // TODO (ps4patches): This seems to be the new way of adding bridges
++ drm_bridge_add(&mn_bridge->bridge);
++
++ return 0;
++}
+diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
+index f6233019f042..d7d510c76e4f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
++++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
+@@ -38,12 +38,13 @@ static bool cik_event_interrupt_isr(struct kfd_dev *dev,
+ uint16_t pasid;
+ bool ret;
+
+- /* This workaround is due to HW/FW limitation on Hawaii that
++ /* This workaround is due to HW/FW limitation on Hawaii and Liverpool that
+ * VMID and PASID are not written into ih_ring_entry
+ */
+ if ((ihre->source_id == CIK_INTSRC_GFX_PAGE_INV_FAULT ||
+ ihre->source_id == CIK_INTSRC_GFX_MEM_PROT_FAULT) &&
+- dev->device_info->asic_family == CHIP_HAWAII) {
++ ((dev->device_info->asic_family == CHIP_HAWAII) ||
++ (dev->device_info->asic_family == CHIP_LIVERPOOL)) {
+ struct cik_ih_ring_entry *tmp_ihre =
+ (struct cik_ih_ring_entry *)patched_ihre;
+
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+index e574aa32a111..5aa872cbef5e 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+@@ -1349,6 +1349,9 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
+ num_of_cache_types = ARRAY_SIZE(kaveri_cache_info);
+ break;
+ case CHIP_HAWAII:
++ case CHIP_LIVERPOOL:
++ case CHIP_GLADIUS:
++ // TODO (ps4patches): Is the Hawaii cache info really fine here?
+ pcache_info = hawaii_cache_info;
+ num_of_cache_types = ARRAY_SIZE(hawaii_cache_info);
+ break;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+index 660eb7097cfc..f40f9e4f3134 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+@@ -62,6 +62,8 @@ static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
+ #endif
+ #ifdef CONFIG_DRM_AMDGPU_CIK
+ [CHIP_HAWAII] = &gfx_v7_kfd2kgd,
++ [CHIP_GLADIUS] = &gfx_v7_kfd2kgd,
++ [CHIP_LIVERPOOL] = &gfx_v7_kfd2kgd,
+ #endif
+ [CHIP_TONGA] = &gfx_v8_kfd2kgd,
+ [CHIP_FIJI] = &gfx_v8_kfd2kgd,
+@@ -168,6 +170,47 @@ static const struct kfd_device_info hawaii_device_info = {
+ .num_sdma_queues_per_engine = 2,
+ };
+
++// TODO (ps4patches): asic_name was hawaii in original patches, check if liverpool as name is ok
++static const struct kfd_device_info liverpool_device_info = {
++ .asic_family = CHIP_LIVERPOOL,
++ .asic_name = "liverpool",
++ .gfx_target_version = 70001,
++ .max_pasid_bits = 16,
++ /* max num of queues for KV.TODO should be a dynamic value */
++ .max_no_of_hqd = 24,
++ .doorbell_size = 4,
++ .ih_ring_entry_size = 4 * sizeof(uint32_t),
++ .event_interrupt_class = &event_interrupt_class_cik,
++ .num_of_watch_points = 4,
++ .mqd_size_aligned = MQD_SIZE_ALIGNED,
++ .supports_cwsr = false,
++ .needs_iommu_device = true,
++ .needs_pci_atomics = false,
++ .num_sdma_engines = 2,
++ .num_xgmi_sdma_engines = 0,
++ .num_sdma_queues_per_engine = 2,
++};
++
++static const struct kfd_device_info gladius_device_info = {
++ .asic_family = CHIP_GLADIUS,
++ .asic_name = "gladius",
++ .gfx_target_version = 70001,
++ .max_pasid_bits = 16,
++ /* max num of queues for KV.TODO should be a dynamic value */
++ .max_no_of_hqd = 24,
++ .doorbell_size = 4,
++ .ih_ring_entry_size = 4 * sizeof(uint32_t),
++ .event_interrupt_class = &event_interrupt_class_cik,
++ .num_of_watch_points = 4,
++ .mqd_size_aligned = MQD_SIZE_ALIGNED,
++ .supports_cwsr = false,
++ .needs_iommu_device = true,
++ .needs_pci_atomics = false,
++ .num_sdma_engines = 2,
++ .num_xgmi_sdma_engines = 0,
++ .num_sdma_queues_per_engine = 2,
++};
++
+ static const struct kfd_device_info tonga_device_info = {
+ .asic_family = CHIP_TONGA,
+ .asic_name = "tonga",
+@@ -661,6 +704,9 @@ static const struct kfd_device_info *kfd_supported_devices[][2] = {
+ #endif
+ [CHIP_RAVEN] = {&raven_device_info, NULL},
+ [CHIP_HAWAII] = {&hawaii_device_info, NULL},
++ [CHIP_LIVERPOOL] = {&liverpool_device_info, NULL},
++ // TODO (ps4patches): This seems to be needed for the new kernel but this might break spectacularly
++ [CHIP_GLADIUS] = {&gladius_device_info, NULL},
+ [CHIP_TONGA] = {&tonga_device_info, NULL},
+ [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info},
+ [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info},
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index 442857f3bde7..d88513d0aca0 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -307,7 +307,8 @@ static void deallocate_vmid(struct device_queue_manager *dqm,
+ struct queue *q)
+ {
+ /* On GFX v7, CP doesn't flush TC at dequeue */
+- if (q->device->device_info->asic_family == CHIP_HAWAII)
++ if ((q->device->device_info->asic_family == CHIP_HAWAII) ||
++ (q->device->device_info->asic_family == CHIP_LIVERPOOL))
+ if (flush_texture_cache_nocpsch(q->device, qpd))
+ pr_err("Failed to flush TC\n");
+
+@@ -1929,6 +1930,8 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
+ device_queue_manager_init_cik(&dqm->asic_ops);
+ break;
+
++ case CHIP_LIVERPOOL:
++ case CHIP_GLADIUS:
+ case CHIP_HAWAII:
+ device_queue_manager_init_cik_hawaii(&dqm->asic_ops);
+ break;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+index 2e86692def19..5db8e9656f5f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+@@ -397,6 +397,8 @@ int kfd_init_apertures(struct kfd_process *process)
+ switch (dev->device_info->asic_family) {
+ case CHIP_KAVERI:
+ case CHIP_HAWAII:
++ case CHIP_GLADIUS:
++ case CHIP_LIVERPOOL:
+ case CHIP_CARRIZO:
+ case CHIP_TONGA:
+ case CHIP_FIJI:
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+index a2b77d1df854..37dcb8dbc9e2 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+@@ -91,6 +91,8 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_dev *dev,
+ kq->pq_gpu_addr = kq->pq->gpu_addr;
+
+ /* For CIK family asics, kq->eop_mem is not needed */
++ // TODO (ps4patches): Liverpool and Gladius were specifically added here before,
++ // this seems to be unneeded here now.
+ if (dev->device_info->asic_family > CHIP_MULLINS) {
+ retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, &kq->eop_mem);
+ if (retval != 0)
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+index e547f1f8c49f..e5b3a425b92e 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+@@ -226,6 +226,8 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
+ switch (dqm->dev->device_info->asic_family) {
+ case CHIP_KAVERI:
+ case CHIP_HAWAII:
++ case CHIP_LIVERPOOL:
++ case CHIP_GLADIUS:
+ /* PM4 packet structures on CIK are the same as on VI */
+ case CHIP_CARRIZO:
+ case CHIP_TONGA:
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+index 98cca5f2b27f..cf39e72ace7f 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+@@ -1395,6 +1395,8 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
+ switch (dev->gpu->device_info->asic_family) {
+ case CHIP_KAVERI:
+ case CHIP_HAWAII:
++ case CHIP_LIVERPOOL:
++ case CHIP_GLADIUS:
+ case CHIP_TONGA:
+ dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_PRE_1_0 <<
+ HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h
+index 9da033dc1a34..3ac8b09a1852 100644
+--- a/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h
++++ b/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_d.h
+@@ -589,8 +589,24 @@
+ #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513
+ #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514
+ #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515
++#define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR 0x516
++#define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR 0x517
++#define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR 0x518
++#define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR 0x519
++#define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR 0x51a
++#define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR 0x51b
++#define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR 0x51c
++#define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR 0x51d
+ #define mmVM_INVALIDATE_REQUEST 0x51e
+ #define mmVM_INVALIDATE_RESPONSE 0x51f
++#define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR 0x524
++#define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR 0x525
++#define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR 0x526
++#define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR 0x527
++#define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR 0x528
++#define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR 0x529
++#define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR 0x52a
++#define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR 0x52b
+ #define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c
+ #define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d
+ #define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e
+@@ -620,8 +636,20 @@
+ #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556
+ #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557
+ #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558
++#define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR 0x559
++#define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR 0x55a
++#define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR 0x55b
++#define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR 0x55c
++#define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR 0x55d
++#define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR 0x55e
+ #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f
+ #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560
++#define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR 0x561
++#define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR 0x562
++#define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR 0x563
++#define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR 0x564
++#define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR 0x565
++#define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR 0x566
+ #define mmVM_DEBUG 0x56f
+ #define mmVM_L2_CG 0x570
+ #define mmVM_L2_BANK_SELECT_MASKA 0x572
+diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
+index 0f66a0d9f06d..24ffc40e76dc 100644
+--- a/include/drm/amd_asic_type.h
++++ b/include/drm/amd_asic_type.h
+@@ -35,33 +35,35 @@ enum amd_asic_type {
+ CHIP_KAVERI, /* 6 */
+ CHIP_KABINI, /* 7 */
+ CHIP_HAWAII, /* 8 */
+- CHIP_MULLINS, /* 9 */
+- CHIP_TOPAZ, /* 10 */
+- CHIP_TONGA, /* 11 */
+- CHIP_FIJI, /* 12 */
+- CHIP_CARRIZO, /* 13 */
+- CHIP_STONEY, /* 14 */
+- CHIP_POLARIS10, /* 15 */
+- CHIP_POLARIS11, /* 16 */
+- CHIP_POLARIS12, /* 17 */
+- CHIP_VEGAM, /* 18 */
+- CHIP_VEGA10, /* 19 */
+- CHIP_VEGA12, /* 20 */
+- CHIP_VEGA20, /* 21 */
+- CHIP_RAVEN, /* 22 */
+- CHIP_ARCTURUS, /* 23 */
+- CHIP_RENOIR, /* 24 */
+- CHIP_ALDEBARAN, /* 25 */
+- CHIP_NAVI10, /* 26 */
+- CHIP_CYAN_SKILLFISH, /* 27 */
+- CHIP_NAVI14, /* 28 */
+- CHIP_NAVI12, /* 29 */
+- CHIP_SIENNA_CICHLID, /* 30 */
+- CHIP_NAVY_FLOUNDER, /* 31 */
+- CHIP_VANGOGH, /* 32 */
+- CHIP_DIMGREY_CAVEFISH, /* 33 */
+- CHIP_BEIGE_GOBY, /* 34 */
+- CHIP_YELLOW_CARP, /* 35 */
++ CHIP_LIVERPOOL, /* 9 */
++ CHIP_GLADIUS, /* 10 */
++ CHIP_MULLINS, /* 11 */
++ CHIP_TOPAZ, /* 12 */
++ CHIP_TONGA, /* 13 */
++ CHIP_FIJI, /* 15 */
++ CHIP_CARRIZO, /* 16 */
++ CHIP_STONEY, /* 17 */
++ CHIP_POLARIS10, /* 18 */
++ CHIP_POLARIS11, /* 19 */
++ CHIP_POLARIS12, /* 20 */
++ CHIP_VEGAM, /* 21 */
++ CHIP_VEGA10, /* 22 */
++ CHIP_VEGA12, /* 23 */
++ CHIP_VEGA20, /* 24 */
++ CHIP_RAVEN, /* 25 */
++ CHIP_ARCTURUS, /* 26 */
++ CHIP_RENOIR, /* 27 */
++ CHIP_ALDEBARAN, /* 28 */
++ CHIP_NAVI10, /* 29 */
++ CHIP_CYAN_SKILLFISH, /* 30 */
++ CHIP_NAVI14, /* 31 */
++ CHIP_NAVI12, /* 32 */
++ CHIP_SIENNA_CICHLID, /* 33 */
++ CHIP_NAVY_FLOUNDER, /* 34 */
++ CHIP_VANGOGH, /* 35 */
++ CHIP_DIMGREY_CAVEFISH, /* 36 */
++ CHIP_BEIGE_GOBY, /* 38 */
++ CHIP_YELLOW_CARP, /* 39 */
+ CHIP_LAST,
+ };
+
+diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
+index b7e899ce44f0..858f9e7667d0 100644
+--- a/include/drm/drm_pciids.h
++++ b/include/drm/drm_pciids.h
+@@ -281,6 +281,10 @@
+ {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x9920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x9922, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x9923, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x9924, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_GLADIUS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0003-feat-radeon-patches.patch b/device/testing/linux-sony-ps4/0003-feat-radeon-patches.patch
new file mode 100644
index 0000000000000000000000000000000000000000..1c94b34f2320ff50155280b26f4f66cc88440a80
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0003-feat-radeon-patches.patch
@@ -0,0 +1,2129 @@
+From 246294ab578bb46cdcba26ebca73246089e2043b Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Mon, 20 Dec 2021 13:59:32 +0100
+Subject: [PATCH 03/22] feat: radeon patches
+
+---
+ drivers/gpu/drm/radeon/Makefile | 2 +
+ drivers/gpu/drm/radeon/atombios_encoders.c | 3 +-
+ drivers/gpu/drm/radeon/cik.c | 714 ++++++++++++++++++-
+ drivers/gpu/drm/radeon/cik_sdma.c | 51 +-
+ drivers/gpu/drm/radeon/cikd.h | 24 +
+ drivers/gpu/drm/radeon/ps4_bridge.c | 758 +++++++++++++++++++++
+ drivers/gpu/drm/radeon/radeon.h | 3 +-
+ drivers/gpu/drm/radeon/radeon_asic.c | 19 +-
+ drivers/gpu/drm/radeon/radeon_audio.c | 10 +-
+ drivers/gpu/drm/radeon/radeon_connectors.c | 57 +-
+ drivers/gpu/drm/radeon/radeon_device.c | 1 +
+ drivers/gpu/drm/radeon/radeon_display.c | 2 +-
+ drivers/gpu/drm/radeon/radeon_drv.c | 15 +
+ drivers/gpu/drm/radeon/radeon_encoders.c | 19 +
+ drivers/gpu/drm/radeon/radeon_family.h | 1 +
+ drivers/gpu/drm/radeon/radeon_ib.c | 9 +-
+ drivers/gpu/drm/radeon/radeon_pm.c | 1 +
+ drivers/gpu/drm/radeon/radeon_ucode.h | 3 +
+ drivers/gpu/drm/radeon/radeon_uvd.c | 1 +
+ drivers/gpu/drm/radeon/radeon_vce.c | 1 +
+ 20 files changed, 1663 insertions(+), 31 deletions(-)
+ create mode 100644 drivers/gpu/drm/radeon/ps4_bridge.c
+
+diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
+index 3d502f1bbfcb..9735ac7a69fa 100644
+--- a/drivers/gpu/drm/radeon/Makefile
++++ b/drivers/gpu/drm/radeon/Makefile
+@@ -53,6 +53,8 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
+
+ radeon-$(CONFIG_MMU_NOTIFIER) += radeon_mn.o
+
++radeon-$(CONFIG_X86_PS4) += ps4_bridge.o
++
+ # add async DMA block
+ radeon-y += \
+ r600_dma.o \
+diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
+index 2b4491137217..12f2f35be471 100644
+--- a/drivers/gpu/drm/radeon/atombios_encoders.c
++++ b/drivers/gpu/drm/radeon/atombios_encoders.c
+@@ -691,7 +691,8 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
+ if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
+ return ATOM_ENCODER_MODE_DP_MST;
+ /* dp bridges are always DP */
+- if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
++ if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE ||
++ (rdev->family == CHIP_LIVERPOOL))
+ return ATOM_ENCODER_MODE_DP;
+
+ /* DVO is always DVO */
+diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
+index 81b4de7be9f2..f6ca400c006f 100644
+--- a/drivers/gpu/drm/radeon/cik.c
++++ b/drivers/gpu/drm/radeon/cik.c
+@@ -122,6 +122,13 @@ MODULE_FIRMWARE("radeon/MULLINS_mec.bin");
+ MODULE_FIRMWARE("radeon/MULLINS_rlc.bin");
+ MODULE_FIRMWARE("radeon/MULLINS_sdma.bin");
+
++MODULE_FIRMWARE("radeon/LIVERPOOL_pfp.bin");
++MODULE_FIRMWARE("radeon/LIVERPOOL_me.bin");
++MODULE_FIRMWARE("radeon/LIVERPOOL_ce.bin");
++MODULE_FIRMWARE("radeon/LIVERPOOL_mec.bin");
++MODULE_FIRMWARE("radeon/LIVERPOOL_rlc.bin");
++MODULE_FIRMWARE("radeon/LIVERPOOL_sdma.bin");
++
+ MODULE_FIRMWARE("radeon/mullins_pfp.bin");
+ MODULE_FIRMWARE("radeon/mullins_me.bin");
+ MODULE_FIRMWARE("radeon/mullins_ce.bin");
+@@ -1031,6 +1038,421 @@ static const u32 kalindi_rlc_save_restore_register_list[] =
+ (0x0e00 << 16) | (0x9600 >> 2),
+ };
+
++static const u32 liverpool_rlc_save_restore_register_li
++{
++ (0x0600 << 16) | 0x263d,
++ 0x00000000,
++ (0x0680 << 16) | 0x263d,
++ 0x00000000,
++ (0x0e00 << 16) | 0x263e,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2640,
++ 0x00000000,
++ (0x0e00 << 16) | 0x3098,
++ 0x00000000,
++ (0x0e00 << 16) | 0x243a,
++ 0x00000000,
++ (0x0e00 << 16) | 0xf000,
++ 0x00000000,
++ (0x0e00 << 16) | 0xf003,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2307,
++ 0x00000000,
++ (0x0e00 << 16) | 0x25c0,
++ 0x00000000,
++ (0x0e00 << 16) | 0x3348,
++ 0x00000000,
++ (0x1e00 << 16) | 0x3348,
++ 0x00000000,
++ (0x4e00 << 16) | 0x3348,
++ 0x00000000,
++ (0x5e00 << 16) | 0x3348,
++ 0x00000000,
++ (0x6e00 << 16) | 0x3348,
++ 0x00000000,
++ (0x7e00 << 16) | 0x3348,
++ 0x00000000,
++ (0x8e00 << 16) | 0x3348,
++ 0x00000000,
++ (0x9e00 << 16) | 0x3348,
++ 0x00000000,
++ (0xae00 << 16) | 0x3348,
++ 0x00000000,
++ (0xbe00 << 16) | 0x3348,
++ 0x00000000,
++ (0x0400 << 16) | 0x226f,
++ 0x00000000,
++ (0x0480 << 16) | 0x226f,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2240,
++ 0x00000000,
++ 0x3,
++ (0x0e00 << 16) | 0x260d,
++ 0x00000000,
++ (0x0000 << 16) | 0xc3c0,
++ 0x00000000,
++ (0x0001 << 16) | 0xc3c0,
++ 0x00000000,
++ (0x0002 << 16) | 0xc3c0,
++ 0x00000000,
++ (0x0003 << 16) | 0xc3c0,
++ 0x00000000,
++ (0x0080 << 16) | 0xc3c0,
++ 0x00000000,
++ (0x0081 << 16) | 0xc3c0,
++ 0x00000000,
++ (0x0082 << 16) | 0xc3c0,
++ 0x00000000,
++ (0x0083 << 16) | 0xc3c0,
++ 0x00000000,
++ (0x0000 << 16) | 0xc3c1,
++ 0x00000000,
++ (0x0001 << 16) | 0xc3c1,
++ 0x00000000,
++ (0x0002 << 16) | 0xc3c1,
++ 0x00000000,
++ (0x0003 << 16) | 0xc3c1,
++ 0x00000000,
++ (0x0080 << 16) | 0xc3c1,
++ 0x00000000,
++ (0x0081 << 16) | 0xc3c1,
++ 0x00000000,
++ (0x0082 << 16) | 0xc3c1,
++ 0x00000000,
++ (0x0083 << 16) | 0xc3c1,
++ 0x00000000,
++ (0x0000 << 16) | 0xc3c2,
++ 0x00000000,
++ (0x0001 << 16) | 0xc3c2,
++ 0x00000000,
++ (0x0002 << 16) | 0xc3c2,
++ 0x00000000,
++ (0x0003 << 16) | 0xc3c2,
++ 0x00000000,
++ (0x0080 << 16) | 0xc3c2,
++ 0x00000000,
++ (0x0081 << 16) | 0xc3c2,
++ 0x00000000,
++ (0x0082 << 16) | 0xc3c2,
++ 0x00000000,
++ (0x0083 << 16) | 0xc3c2,
++ 0x00000000,
++ (0x0000 << 16) | 0xc3c3,
++ 0x00000000,
++ (0x0001 << 16) | 0xc3c3,
++ 0x00000000,
++ (0x0002 << 16) | 0xc3c3,
++ 0x00000000,
++ (0x0003 << 16) | 0xc3c3,
++ 0x00000000,
++ (0x0080 << 16) | 0xc3c3,
++ 0x00000000,
++ (0x0081 << 16) | 0xc3c3,
++ 0x00000000,
++ (0x0082 << 16) | 0xc3c3,
++ 0x00000000,
++ (0x0083 << 16) | 0xc3c3,
++ 0x00000000,
++ (0x0600 << 16) | 0x26df,
++ 0x00000000,
++ (0x0680 << 16) | 0x26df,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2285,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2286,
++ 0x00000000,
++ (0x0600 << 16) | 0xc280,
++ 0x00000000,
++ (0x0680 << 16) | 0xc280,
++ 0x00000000,
++ (0x1600 << 16) | 0xc280,
++ 0x00000000,
++ (0x1680 << 16) | 0xc280,
++ 0x00000000,
++ (0x0e00 << 16) | 0x22fc,
++ 0x00000000,
++ (0x0e00 << 16) | 0x22f3,
++ 0x00000000,
++ (0x0e00 << 16) | 0x22c9,
++ 0x00000000,
++ (0x0e00 << 16) | 0xc281,
++ 0x00000000,
++ (0x1e00 << 16) | 0xc281,
++ 0x00000000,
++ (0x0600 << 16) | 0xc284,
++ 0x00000000,
++ (0x0680 << 16) | 0xc284,
++ 0x00000000,
++ (0x1600 << 16) | 0xc284,
++ 0x00000000,
++ (0x1680 << 16) | 0xc284,
++ 0x00000000,
++ (0x0600 << 16) | 0xc285,
++ 0x00000000,
++ (0x0680 << 16) | 0xc285,
++ 0x00000000,
++ (0x1600 << 16) | 0xc285,
++ 0x00000000,
++ (0x1680 << 16) | 0xc285,
++ 0x00000000,
++ (0x0600 << 16) | 0xc286,
++ 0x00000000,
++ (0x0680 << 16) | 0xc286,
++ 0x00000000,
++ (0x1600 << 16) | 0xc286,
++ 0x00000000,
++ (0x1680 << 16) | 0xc286,
++ 0x00000000,
++ (0x0600 << 16) | 0xc28b,
++ 0x00000000,
++ (0x0680 << 16) | 0xc28b,
++ 0x00000000,
++ (0x1600 << 16) | 0xc28b,
++ 0x00000000,
++ (0x1680 << 16) | 0xc28b,
++ 0x00000000,
++ (0x0e00 << 16) | 0x31c0,
++ 0x00000000,
++ (0x0e00 << 16) | 0x31c1,
++ 0x00000000,
++ (0x0e00 << 16) | 0x31c2,
++ 0x00000000,
++ (0x0e00 << 16) | 0x31da,
++ 0x00000000,
++ (0x0400 << 16) | 0x31dc,
++ 0x00000000,
++ (0x0480 << 16) | 0x31dc,
++ 0x00000000,
++ (0x0400 << 16) | 0x31dd,
++ 0x00000000,
++ (0x0480 << 16) | 0x31dd,
++ 0x00000000,
++ (0x0400 << 16) | 0x31de,
++ 0x00000000,
++ (0x0480 << 16) | 0x31de,
++ 0x00000000,
++ (0x0400 << 16) | 0x31df,
++ 0x00000000,
++ (0x0480 << 16) | 0x31df,
++ 0x00000000,
++ (0x0400 << 16) | 0x31e0,
++ 0x00000000,
++ (0x0480 << 16) | 0x31e0,
++ 0x00000000,
++ (0x0400 << 16) | 0x31e1,
++ 0x00000000,
++ (0x0480 << 16) | 0x31e1,
++ 0x00000000,
++ (0x0400 << 16) | 0x31e2,
++ 0x00000000,
++ (0x0480 << 16) | 0x31e2,
++ 0x00000000,
++ (0x0400 << 16) | 0x31e3,
++ 0x00000000,
++ (0x0480 << 16) | 0x31e3,
++ 0x00000000,
++ (0x0400 << 16) | 0x31e4,
++ 0x00000000,
++ (0x0480 << 16) | 0x31e4,
++ 0x00000000,
++ (0x0400 << 16) | 0x31e5,
++ 0x00000000,
++ (0x0480 << 16) | 0x31e5,
++ 0x00000000,
++ (0x0400 << 16) | 0x31e6,
++ 0x00000000,
++ (0x0480 << 16) | 0x31e6,
++ 0x00000000,
++ (0x0400 << 16) | 0x31e7,
++ 0x00000000,
++ (0x0480 << 16) | 0x31e7,
++ 0x00000000,
++ (0x0400 << 16) | 0x31e8,
++ 0x00000000,
++ (0x0480 << 16) | 0x31e8,
++ 0x00000000,
++ (0x0400 << 16) | 0x31e9,
++ 0x00000000,
++ (0x0480 << 16) | 0x31e9,
++ 0x00000000,
++ (0x0400 << 16) | 0x31ea,
++ 0x00000000,
++ (0x0480 << 16) | 0x31ea,
++ 0x00000000,
++ (0x0400 << 16) | 0x31eb,
++ 0x00000000,
++ (0x0480 << 16) | 0x31eb,
++ 0x00000000,
++ (0x0400 << 16) | 0x31ec,
++ 0x00000000,
++ (0x0480 << 16) | 0x31ec,
++ 0x00000000,
++ (0x0400 << 16) | 0x31ed,
++ 0x00000000,
++ (0x0480 << 16) | 0x31ed,
++ 0x00000000,
++ (0x0400 << 16) | 0x31ee,
++ 0x00000000,
++ (0x0480 << 16) | 0x31ee,
++ 0x00000000,
++ (0x0400 << 16) | 0x31ef,
++ 0x00000000,
++ (0x0480 << 16) | 0x31ef,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2440,
++ 0x00000000,
++ (0x0e00 << 16) | 0xf004,
++ 0x00000000,
++ (0x0e00 << 16) | 0x24aa,
++ 0x00000000,
++ (0x0e00 << 16) | 0x24ab,
++ 0x00000000,
++ (0x0e00 << 16) | 0x24ac,
++ 0x00000000,
++ (0x0e00 << 16) | 0x24ad,
++ 0x00000000,
++ (0x0e00 << 16) | 0x24ae,
++ 0x00000000,
++ (0x0e00 << 16) | 0x24af,
++ 0x00000000,
++ (0x0e00 << 16) | 0x24b0,
++ 0x00000000,
++ (0x0e00 << 16) | 0x24b1,
++ 0x00000000,
++ (0x0e00 << 16) | 0x24b2,
++ 0x00000000,
++ (0x0e00 << 16) | 0x24b3,
++ 0x00000000,
++ (0x0e00 << 16) | 0x24b4,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2300,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2301,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2308,
++ 0x00000000,
++ (0x0e00 << 16) | 0x230e,
++ 0x00000000,
++ (0x0e00 << 16) | 0x230f,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b80,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2581,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b02,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b03,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b04,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b05,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b16,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b1a,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b1b,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b1c,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b1d,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b1e,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b1f,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b20,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b21,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b22,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2b23,
++ 0x00000000,
++ (0x0e00 << 16) | 0x25c3,
++ 0x00000000,
++ (0x0e00 << 16) | 0x25c5,
++ 0x00000000,
++ (0x0e00 << 16) | 0x25c6,
++ 0x00000000,
++ (0x0e00 << 16) | 0x25c7,
++ 0x00000000,
++ (0x0e00 << 16) | 0xc41a,
++ 0x00000000,
++ (0x1e00 << 16) | 0xc41a,
++ 0x00000000,
++ (0x4e00 << 16) | 0xc41a,
++ 0x00000000,
++ (0x5e00 << 16) | 0xc41a,
++ 0x00000000,
++ (0x6e00 << 16) | 0xc41a,
++ 0x00000000,
++ (0x7e00 << 16) | 0xc41a,
++ 0x00000000,
++ (0x8e00 << 16) | 0xc41a,
++ 0x00000000,
++ (0x9e00 << 16) | 0xc41a,
++ 0x00000000,
++ (0xae00 << 16) | 0xc41a,
++ 0x00000000,
++ (0xbe00 << 16) | 0xc41a,
++ 0x00000000,
++ (0x0e00 << 16) | 0x3344,
++ 0x00000000,
++ (0x0e00 << 16) | 0x3345,
++ 0x00000000,
++ (0x0e00 << 16) | 0x222c,
++ 0x00000000,
++ (0x0e00 << 16) | 0x222d,
++ 0x00000000,
++ (0x0e00 << 16) | 0x222e,
++ 0x00000000,
++ (0x0e00 << 16) | 0x222f,
++ 0x00000000,
++ (0x0400 << 16) | 0x2270,
++ 0x00000000,
++ (0x0480 << 16) | 0x2270,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2231,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2274,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2234,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2235,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2236,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2260,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2262,
++ 0x00000000,
++ (0x0e00 << 16) | 0x226c,
++ 0x00000000,
++ (0x0e00 << 16) | 0x226e,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2268,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2232,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2233,
++ 0x00000000,
++ (0x0e00 << 16) | 0x226d,
++ 0x00000000,
++ (0x0e00 << 16) | 0xf87f,
++ 0x00000000,
++ (0x0e00 << 16) | 0xf084,
++ 0x00000000,
++ (0x0e00 << 16) | 0xf085,
++ 0x00000000,
++ (0x0e00 << 16) | 0xf086,
++ 0x00000000,
++ (0x0e00 << 16) | 0x2241,
++ 0x00000000,
++ 1,
++ (0x0e00 << 16) | 0x230d,
++};
++
+ static const u32 bonaire_golden_spm_registers[] =
+ {
+ 0x30800, 0xe0ffffff, 0xe0000000
+@@ -1175,6 +1597,163 @@ static const u32 bonaire_mgcg_cgcg_init[] =
+ 0xd80c, 0xff000ff0, 0x00000100
+ };
+
++static const u32 liverpool_golden_common_registers[] =
++{
++ 0xc770, 0xffffffff, 0x00000800, /* SPI_RESOURCE_RESERVE_CU_0 */
++ 0xc774, 0xffffffff, 0x00000800, /* SPI_RESOURCE_RESERVE_CU_1 */
++ 0xc798, 0xffffffff, 0x00ffffbf, /* SPI_RESOURCE_RESERVE_EN_CU_0 */
++ 0xc79c, 0xffffffff, 0x00ffffaf, /* SPI_RESOURCE_RESERVE_EN_CU_1 */
++ 0xc7a0, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_2 */
++ 0xc7a4, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_3*/
++ 0xc7a8, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_4 */
++ 0xc7ac, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_5 */
++ 0xc7b0, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_6 */
++ 0xc7b4, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_7 */
++ 0xc7b8, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_8 */
++ 0xc7bc, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_9 */
++ 0x28350, 0xffffffff, 0x2a00161a, /* PA_SC_RASTER_CONFIG */
++ 0x28354, 0xffffffff, 0x00000000, /* PA_SC_RASTER_CONFIG_1 */
++ 0x5004, 0x00002000, 0x00002000, /* GARLIC_FLUSH_CNTL */
++};
++
++onst u32 liverpool_golden_registers[] =
++{
++ 0xc420, 0xffffffff, 0xfffffffc, /* RLC_CGTT_MGCG_OVERRIDE */
++ 0x30800, 0xffffffff, 0xe0000000, /* GRBM_GFX_INDEX */
++ /* These are all setting OFF_HYSTERESIS = 0x10 */
++ 0x3c2a0, 0xffffffff, 0x00000100, /* CB_CGTT_SCLK_CTRL */
++ 0x3c208, 0xffffffff, 0x00000100, /* CGTT_BCI_CLK_CTRL */
++ 0x3c2c0, 0xffffffff, 0x00000100, /* CGTT_CP_CLK_CTRL */
++ 0x3c2c8, 0xffffffff, 0x00000100, /* CGTT_CPC_CLK_CTRL */
++ 0x3c2c4, 0xffffffff, 0x00000100, /* CGTT_CPF_CLK_CTRL */
++ 0x55e4, 0xffffffff, 0x00600100, /* CGTT_DRM_CLK_CTRL0 */
++ 0x3c280, 0xffffffff, 0x00000100, /* CGTT_GDS_CLK_CTRL */
++ 0x3c214, 0xffffffff, 0x06000100, /* CGTT_IA_CLK_CTRL */
++ 0x3c220, 0xffffffff, 0x00000100, /* CGTT_PA_CLK_CTRL */
++ 0x3c218, 0xffffffff, 0x06000100, /* CGTT_WD_CLK_CTRL */
++ 0x3c204, 0xffffffff, 0x00000100, /* CGTT_PC_CLK_CTRL */
++ 0x3c2e0, 0xffffffff, 0x00000100, /* CGTT_RLC_CLK_CTRL */
++ 0x3c224, 0xffffffff, 0x00000100, /* CGTT_SC_CLK_CTRL */
++ 0x3c200, 0xffffffff, 0x00000100, /* CGTT_SPI_CLK_CTRL */
++ 0x3c230, 0xffffffff, 0x00000100, /* CGTT_SQ_CLK_CTRL */
++ 0x3c234, 0xffffffff, 0x00000100, /* CGTT_SQG_CLK_CTRL */
++ 0x3c250, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL0 */
++ 0x3c254, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL1 */
++ 0x3c258, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL2 */
++ 0x3c25c, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL3 */
++ 0x3c260, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL4 */
++ 0x3c27c, 0xffffffff, 0x00000100, /* CGTT_TCI_CLK_CTRL */
++ 0x3c278, 0xffffffff, 0x00000100, /* CGTT_TCP_CLK_CTRL */
++ 0x3c210, 0xffffffff, 0x06000100, /* CGTT_VGT_CLK_CTRL */
++ 0x3c290, 0xffffffff, 0x00000100, /* DB_CGTT_CLK_CTRL_0 */
++ 0x3c274, 0xffffffff, 0x00000100, /* TA_CGTT_CTRL */
++ 0x3c2b4, 0xffffffff, 0x00000100, /* TCA_CGTT_SCLK_CTRL */
++ 0x3c2b0, 0xffffffff, 0x00000100, /* TCC_CGTT_SCLK_CTRL */
++ 0x3c270, 0xffffffff, 0x00000100, /* TD_CGTT_CTRL */
++ 0x30800, 0xffffffff, 0xe0000000, /* GRBM_GFX_INDEX */
++ 0x3c020, 0xffffffff, 0x00010000, /* CGTS_CU0_SP0_CTRL_REG */
++ 0x3c024, 0xffffffff, 0x00030002, /* CGTS_CU0_LDS_SQ_CTRL_REG */
++ 0x3c028, 0xffffffff, 0x00040007, /* CGTS_CU0_TA_SQC_CTRL_REG */
++ 0x3c02c, 0xffffffff, 0x00060005, /* CGTS_CU0_SP1_CTRL_REG */
++ 0x3c030, 0xffffffff, 0x00090008, /* CGTS_CU0_TD_TCP_CTRL_REG */
++ 0x3c034, 0xffffffff, 0x00010000, /* CGTS_CU1_SP0_CTRL_REG */
++ 0x3c038, 0xffffffff, 0x00030002, /* CGTS_CU1_LDS_SQ_CTRL_REG */
++ 0x3c03c, 0xffffffff, 0x00040007, /* CGTS_CU1_TA_CTRL_REG */
++ 0x3c040, 0xffffffff, 0x00060005, /* CGTS_CU1_SP1_CTRL_REG */
++ 0x3c044, 0xffffffff, 0x00090008, /* CGTS_CU1_TD_TCP_CTRL_REG */
++ 0x3c048, 0xffffffff, 0x00010000, /* CGTS_CU2_SP0_CTRL_REG */
++ 0x3c04c, 0xffffffff, 0x00030002, /* CGTS_CU2_LDS_SQ_CTRL_REG */
++ 0x3c050, 0xffffffff, 0x00040007, /* CGTS_CU2_TA_CTRL_REG */
++ 0x3c054, 0xffffffff, 0x00060005, /* CGTS_CU2_SP1_CTRL_REG */
++ 0x3c058, 0xffffffff, 0x00090008, /* CGTS_CU2_TD_TCP_CTRL_REG */
++ 0x3c05c, 0xffffffff, 0x00010000, /* CGTS_CU3_SP0_CTRL_REG */
++ 0x3c060, 0xffffffff, 0x00030002, /* CGTS_CU3_LDS_SQ_CTRL_REG */
++ 0x3c064, 0xffffffff, 0x00040007, /* CGTS_CU3_TA_SQC_CTRL_REG */
++ 0x3c068, 0xffffffff, 0x00060005, /* CGTS_CU3_SP1_CTRL_REG */
++ 0x3c06c, 0xffffffff, 0x00090008, /* CGTS_CU3_TD_TCP_CTRL_REG */
++ 0x3c070, 0xffffffff, 0x00010000, /* CGTS_CU4_SP0_CTRL_REG */
++ 0x3c074, 0xffffffff, 0x00030002, /* CGTS_CU4_LDS_SQ_CTRL_REG */
++ 0x3c078, 0xffffffff, 0x00040007, /* CGTS_CU4_TA_CTRL_REG */
++ 0x3c07c, 0xffffffff, 0x00060005, /* CGTS_CU4_SP1_CTRL_REG */
++ 0x3c080, 0xffffffff, 0x00090008, /* CGTS_CU4_TD_TCP_CTRL_REG */
++ 0x3c084, 0xffffffff, 0x00010000, /* CGTS_CU5_SP0_CTRL_REG */
++ 0x3c088, 0xffffffff, 0x00030002, /* CGTS_CU5_LDS_SQ_CTRL_REG */
++ 0x3c08c, 0xffffffff, 0x00040007, /* CGTS_CU5_TA_CTRL_REG */
++ 0x3c090, 0xffffffff, 0x00060005, /* CGTS_CU5_SP1_CTRL_REG */
++ 0x3c094, 0xffffffff, 0x00090008, /* CGTS_CU5_TD_TCP_CTRL_REG */
++ 0x3c098, 0xffffffff, 0x00010000, /* CGTS_CU6_SP0_CTRL_REG */
++ 0x3c09c, 0xffffffff, 0x00030002, /* CGTS_CU6_LDS_SQ_CTRL_REG */
++ 0x3c0a0, 0xffffffff, 0x00040007, /* CGTS_CU6_TA_SQC_CTRL_REG */
++ 0x3c0a4, 0xffffffff, 0x00060005, /* CGTS_CU6_SP1_CTRL_REG */
++ 0x3c0a8, 0xffffffff, 0x00090008, /* CGTS_CU6_TD_TCP_CTRL_REG */
++ 0x3c0ac, 0xffffffff, 0x00010000, /* CGTS_CU7_SP0_CTRL_REG */
++ 0x3c0b0, 0xffffffff, 0x00030002, /* CGTS_CU7_LDS_SQ_CTRL_REG */
++ 0x3c0b4, 0xffffffff, 0x00040007, /* CGTS_CU7_TA_SQC_CTRL_REG */
++ 0x3c0b8, 0xffffffff, 0x00060005, /* CGTS_CU7_SP1_CTRL_REG */
++ 0x3c0bc, 0xffffffff, 0x00090008, /* CGTS_CU7_TD_TCP_CTRL_REG */
++ 0x3c0c0, 0xffffffff, 0x00010000, /* CGTS_CU8_SP0_CTRL_REG */
++ 0x3c0c4, 0xffffffff, 0x00030002, /* CGTS_CU8_LDS_SQ_CTRL_REG */
++ 0x3c0c8, 0xffffffff, 0x00040007, /* CGTS_CU8_TA_CTRL_REG */
++ 0x3c0cc, 0xffffffff, 0x00060005, /* CGTS_CU8_SP1_CTRL_REG */
++ 0x3c0d0, 0xffffffff, 0x00090008, /* CGTS_CU8_TD_TCP_CTRL_REG */
++ 0x3c0d4, 0xffffffff, 0x00010000, /* CGTS_CU9_SP0_CTRL_REG */
++ 0x3c0d8, 0xffffffff, 0x00030002, /* CGTS_CU9_LDS_SQ_CTRL_REG */
++ 0x3c0dc, 0xffffffff, 0x00040007, /* CGTS_CU9_TA_CTRL_REG */
++ 0x3c0e0, 0xffffffff, 0x00060005, /* CGTS_CU9_SP1_CTRL_REG */
++ 0x3c0e4, 0xffffffff, 0x00090008, /* CGTS_CU9_TD_TCP_CTRL_REG */
++ 0x3c000, 0xffffffff, 0x96940200, /* CGTS_SM_CTRL_REG */
++ 0x8708, 0xffffffff, 0x00900100, /* CP_RB_WPTR_POLL_CNTL */
++ 0xc424, 0xffffffff, 0x0020003f, /* RLC_CGCG_CGLS_CTRL */
++ 0x9a10, 0x00210000, 0x00018208, /* CB_HW_CONTROL */
++ 0x3c000, 0xffff1fff, 0x96940200, /* CGTS_SM_CTRL_REG */
++ 0x3c00c, 0xffff0001, 0xff000000, /* CGTS_TCC_DISABLE */
++ 0x3c010, 0xffff0000, 0xff000000, /* CGTS_USER_TCC_DISABLE */
++ 0x55e4, 0xff607fff, 0xfc000100, /* CGTT_DRM_CLK_CTRL0 */
++ 0x3c200, 0xfdfc0fff, 0x00000100, /* CGTT_SPI_CLK_CTRL */
++ 0x6ed8, 0x00010000, 0x00010000, /* CRTC_DOUBLE_BUFFER_CONTROL */
++ 0x9834, 0xf00fffff, 0x00004400, /* DB_DEBUG2 */
++ 0x5bb0, 0x000000f0, 0x00000070, /* FBC_DEBUG_COMP */
++ 0x98f8, 0x73773777, 0x12011002, /* GB_ADDR_CONFIG 0x12011003*/
++ 0x2f48, 0x73773777, 0x12010001, /* HDP_ADDR_CONFIG */
++ 0x8a14, 0xf000003f, 0x00000007, /* PA_CL_ENHANCE */
++ 0x8bf0, 0x00000001, 0x00000001, /* PA_SC_ENHANCE */
++ 0x8b24, 0xffffffff, 0x00ffffff, /* PA_SC_FORCE_EOV_MAX_CNTS */
++ 0x30a04, 0x0000ff0f, 0x00000000, /* PA_SC_LINE_STIPPLE_STATE */
++ 0x28a4c, 0x07ffffff, 0x06000000, /* PA_SC_MODE_CNTL_1 */
++ 0xc37c, 0xffffffff, 0x00000b00, /* RLC_PG_DELAY_2 */
++ 0x4d8, 0x00000fff, 0x00000100, /* SCLK_CGTT_BLK_CTRL_REG */
++ 0x3e78, 0x00000001, 0x00000002, /* SEM_CHICKEN_BITS */
++ 0xc768, 0x00000008, 0x00000008, /* SPI_RESET_DEBUG */
++ 0x8c00, 0x000000ff, 0x00000001, /* SQ_CONFIG */
++ 0x9508, 0x00010000, 0x00010000, /* TA_CNTL_AUX */
++ 0xac0c, 0xffffffff, 0x76325410, /* TCP_CHAN_STEER_LO */
++ 0xc770, 0xffffffff, 0x00000800, /* SPI_RESOURCE_RESERVE_CU_0 */
++ 0xc774, 0xffffffff, 0x00000800, /* SPI_RESOURCE_RESERVE_CU_1 */
++ 0xc798, 0xffffffff, 0x00ffffbf, /* SPI_RESOURCE_RESERVE_EN_CU_0 */
++ 0xc79c, 0xffffffff, 0x00ffffaf, /* SPI_RESOURCE_RESERVE_EN_CU_1 */
++ 0xc7a0, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_2 */
++ 0xc7a4, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_3 */
++ 0xc7a8, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_4 */
++ 0xc7ac, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_5*/
++ 0xc7b0, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_6 */
++ 0xc7b4, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_7 */
++ 0xc7b8, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_8 */
++ 0xc7bc, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_9 */
++ 0x28350, 0xffffffff, 0x2a00161a, /* PA_SC_RASTER_CONFIG */
++ 0x28354, 0xffffffff, 0x00000000, /* PA_SC_RASTER_CONFIG_1 */
++ 0x5004, 0x00002000, 0x00002000, /* GARLIC_FLUSH_CNTL */
++ /* SDMA */
++ 0xd010, 0xffffffff, 0x08050400, /* SDMA0_CNTL */
++ 0xd810, 0xffffffff, 0x08050400, /* SDMA1_CNTL */
++ 0xda00, 0xffffffff, 0x00000018, /*SDMA0_GFX_RB_CNTL */
++ 0xd200, 0xffffffff, 0x00000018, /*SDMA1_GFX_RB_CNTL */
++ 0xd228, 0xffffffff, 0x00000100, /*SDMA0_GFX_IB_CNTL */
++ 0xda28, 0xffffffff, 0x00000100, /*SDMA1_GFX_IB_CNTL */
++ 0xd034, 0xffffffff, 0x00000000, /*SDMA1_GFX_CONTEXT_STATUS */
++ 0xd834, 0xffffffff, 0x00000000, /*SDMA1_GFX_CONTEXT_STATUS */
++ 0x14d4, 0xffffffff, 0x00000000, /* VM_CONTEXTS_DISABLE */
++};
++
+ static const u32 spectre_golden_spm_registers[] =
+ {
+ 0x30800, 0xe0ffffff, 0xe0000000
+@@ -1633,6 +2212,22 @@ static void cik_init_golden_registers(struct radeon_device *rdev)
+ bonaire_golden_spm_registers,
+ (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
+ break;
++ case CHIP_LIVERPOOL:
++ /*radeon_program_register_sequence(rdev,
++ liverpool_mgcg_cgcg_init,
++ (const u32)ARRAY_SIZE(liverpool_mgcg_cgcg_init));*/
++ radeon_program_register_sequence(rdev,
++ liverpool_golden_registers,
++ (const u32)ARRAY_SIZE(liverpool_golden_registers));
++
++ radeon_program_register_sequence(rdev,
++ liverpool_golden_common_registers,
++ (const u32)ARRAY_SIZE(liverpool_golden_common_registers));
++
++ /*radeon_program_register_sequence(rdev,
++ liverpool_golden_spm_registers,
++ (const u32)ARRAY_SIZE(liverpool_golden_spm_registers));*/
++ break;
+ case CHIP_KABINI:
+ radeon_program_register_sequence(rdev,
+ kalindi_mgcg_cgcg_init,
+@@ -2046,6 +2641,17 @@ static int cik_init_microcode(struct radeon_device *rdev)
+ sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
+ num_fw = 6;
+ break;
++ case CHIP_LIVERPOOL:
++ chip_name = "LIVERPOOL";
++ new_chip_name = "liverpool";
++ pfp_req_size = LIVERPOOL_PFP_UCODE_SIZE * 4;
++ me_req_size = LIVERPOOL_ME_UCODE_SIZE * 4;
++ ce_req_size = CIK_CE_UCODE_SIZE * 4;
++ mec_req_size = CIK_MEC_UCODE_SIZE * 4;
++ rlc_req_size = LIVERPOOL_RLC_UCODE_SIZE * 4;
++ sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
++ num_fw = 6;
++ break;
+ default: BUG();
+ }
+
+@@ -3225,6 +3831,26 @@ static void cik_gpu_init(struct radeon_device *rdev)
+ rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
+ gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
+ break;
++
++ case CHIP_LIVERPOOL:
++ rdev->config.cik.max_shader_engines = 2; // VERIFIED
++ rdev->config.cik.max_tile_pipes = 8; // VERIFIED
++ rdev->config.cik.max_cu_per_sh = 9; // VERIFIED
++ rdev->config.cik.max_sh_per_se = 1; // VERIFIED
++ rdev->config.cik.max_backends_per_se = 2; // PROBABLY OK, >1?
++ rdev->config.cik.max_texture_channel_caches = 4; // ??
++ rdev->config.cik.max_gprs = 256;
++ rdev->config.cik.max_gs_threads = 32; // ??
++ rdev->config.cik.max_hw_contexts = 8;
++
++ rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
++ rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
++ rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
++ rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
++
++ gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
++ break;
++
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
+ default:
+@@ -3904,6 +4530,9 @@ static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
+ radeon_ucode_print_gfx_hdr(&ce_hdr->header);
+ radeon_ucode_print_gfx_hdr(&me_hdr->header);
+
++ // TODO (ps4patches): This might be correct already
++ // + for (i = 0; i < rdev->pfp_fw->size/4; i++)
++
+ /* PFP */
+ fw_data = (const __le32 *)
+ (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
+@@ -4936,6 +5565,22 @@ static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
+ dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
+ RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
+
++ dev_info(rdev->dev, " VM_CONTEXT0_CNTL 0x%08X\n",
++ RREG32(VM_CONTEXT0_CNTL));
++ dev_info(rdev->dev, " VM_CONTEXT1_CNTL 0x%08X\n",
++ RREG32(VM_CONTEXT1_CNTL));
++ dev_info(rdev->dev, " VM_CONTEXT0_CNTL2 0x%08X\n",
++ RREG32(VM_CONTEXT0_CNTL2));
++ dev_info(rdev->dev, " VM_CONTEXT1_CNTL2 0x%08X\n",
++ RREG32(VM_CONTEXT1_CNTL2));
++ dev_info(rdev->dev, " VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x%08X\n",
++ RREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR));
++ dev_info(rdev->dev, " VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x%08X\n",
++ RREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR));
++ dev_info(rdev->dev, " VM_DEBUG 0x%08X\n",
++ RREG32(0x15bc));
++ //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
++
+ /* disable CG/PG */
+ cik_fini_pg(rdev);
+ cik_fini_cg(rdev);
+@@ -5443,9 +6088,18 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
+ EFFECTIVE_L2_QUEUE_SIZE(7) |
+ CONTEXT1_IDENTITY_ACCESS_MODE(1));
+ WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
+- WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
+- BANK_SELECT(4) |
+- L2_CACHE_BIGK_FRAGMENT_SIZE(4));
++
++ if(rdev->family == CHIP_LIVERPOOL)
++ {
++ WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
++ BANK_SELECT(6) |
++ L2_CACHE_BIGK_FRAGMENT_SIZE(6));
++ } else {
++ WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
++ BANK_SELECT(4) |
++ L2_CACHE_BIGK_FRAGMENT_SIZE(4));
++ }
++
+ /* setup context0 */
+ WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
+ WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
+@@ -5461,7 +6115,6 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
+ WREG32(0x15DC, 0);
+
+ /* restore context1-15 */
+- /* set vm size, must be a multiple of 4 */
+ WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
+ WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
+ for (i = 1; i < 16; i++) {
+@@ -5473,6 +6126,36 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
+ rdev->vm_manager.saved_table_addr[i]);
+ }
+
++ if(rdev->family == CHIP_LIVERPOOL) {
++ /* empty context1-15 */
++ /* Assign the pt base to something valid for now; the pts used for
++ * the VMs are determined by the application and setup and assigned
++ * on the fly in the vm part of radeon_gart.c
++ */
++ for (i = 1; i < 16; i++) {
++ if (i < 8) {
++ WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR +
++ (i << 2),
++ 0);
++ WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR +
++ (i << 2),
++ rdev->vm_manager.max_pfn - 1);
++ WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR +
++ (i << 2),
++ rdev->vm_manager.saved_table_addr[i]);
++ } else {
++ WREG32(VM_CONTEXT8_PAGE_TABLE_START_ADDR +
++ ((i - 8) << 2),
++ 0);
++ /*WREG32(VM_CONTEXT8_PAGE_TABLE_END_ADDR + ((i - 8) << 2),
++ rdev->vm_manager.max_pfn - 1);*/
++ WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR +
++ ((i - 8) << 2),
++ rdev->vm_manager.saved_table_addr[i]);
++ }
++ }
++ }
++
+ /* enable context1-15 */
+ WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
+ (u32)(rdev->dummy_page.addr >> 12));
+@@ -5967,6 +6650,9 @@ static int cik_rlc_resume(struct radeon_device *rdev)
+ case CHIP_MULLINS:
+ size = ML_RLC_UCODE_SIZE;
+ break;
++ case CHIP_LIVERPOOL:
++ size = LIVERPOOL_RLC_UCODE_SIZE;
++ break;
+ }
+
+ fw_data = (const __be32 *)rdev->rlc_fw->data;
+@@ -6748,6 +7434,10 @@ void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
+ buffer[count++] = cpu_to_le32(0x3a00161a);
+ buffer[count++] = cpu_to_le32(0x0000002e);
+ break;
++ case CHIP_LIVERPOOL:
++ buffer[count++] = cpu_to_le32(0x2a00161a);
++ buffer[count++] = cpu_to_le32(0x00000000);
++ break;
+ default:
+ buffer[count++] = cpu_to_le32(0x00000000);
+ buffer[count++] = cpu_to_le32(0x00000000);
+@@ -7923,6 +8613,7 @@ int cik_irq_process(struct radeon_device *rdev)
+ break;
+ case 176: /* GFX RB CP_INT */
+ case 177: /* GFX IB CP_INT */
++ DRM_ERROR("radeon_fence_process 176 177\n"); // eeply
+ radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
+ break;
+ case 181: /* CP EOP event */
+@@ -8310,6 +9001,10 @@ static int cik_startup(struct radeon_device *rdev)
+ rdev->rlc.reg_list = spectre_rlc_save_restore_register_list;
+ rdev->rlc.reg_list_size =
+ (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
++ } else if (rdev->family == CHIP_LIVERPOOL) {
++ rdev->rlc.reg_list = liverpool_rlc_save_restore_register_list;
++ rdev->rlc.reg_list_size =
++ (u32)ARRAY_SIZE(liverpool_rlc_save_restore_register_list);
+ } else {
+ rdev->rlc.reg_list = kalindi_rlc_save_restore_register_list;
+ rdev->rlc.reg_list_size =
+@@ -8444,8 +9139,10 @@ static int cik_startup(struct radeon_device *rdev)
+ if (r)
+ return r;
+
+- cik_uvd_resume(rdev);
+- cik_vce_resume(rdev);
++ if (rdev->family != CHIP_LIVERPOOL) {
++ cik_uvd_resume(rdev);
++ cik_vce_resume(rdev);
++ }
+
+ r = radeon_ib_pool_init(rdev);
+ if (r) {
+@@ -9368,6 +10065,11 @@ void dce8_bandwidth_update(struct radeon_device *rdev)
+ u32 num_heads = 0, lb_size;
+ int i;
+
++ if (rdev->family == CHIP_LIVERPOOL) {
++ // FIXME PS4 (ps4patches): this stuff is broken
++ return;
++ }
++
+ if (!rdev->mode_info.mode_config_initialized)
+ return;
+
+diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
+index 919b14845c3c..0840f96d0813 100644
+--- a/drivers/gpu/drm/radeon/cik_sdma.c
++++ b/drivers/gpu/drm/radeon/cik_sdma.c
+@@ -140,11 +140,23 @@ void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
+ while ((next_rptr & 7) != 4)
+ next_rptr++;
+ next_rptr += 4;
+- radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
+- radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
+- radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
+- radeon_ring_write(ring, 1); /* number of DWs to follow */
+- radeon_ring_write(ring, next_rptr);
++
++ if (rdev->family == CHIP_LIVERPOOL) {
++ /* SDMA_OPCODE_WRITE is broken on Liverpool when used
++ * in the ring (works in IBs) */
++ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0,
++ SDMA_CONSTANT_FILL_EXTRA_SIZE(2)));
++ radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
++ radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
++ radeon_ring_write(ring, next_rptr);
++ radeon_ring_write(ring, 4);
++ } else {
++ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
++ radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
++ radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
++ radeon_ring_write(ring, 1); /* number of DWs to follow */
++ radeon_ring_write(ring, next_rptr);
++ }
+ }
+
+ /* IB packet must end on a 8 DW boundary */
+@@ -665,11 +677,24 @@ int cik_sdma_ring_test(struct radeon_device *rdev,
+ DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
+ return r;
+ }
+- radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
+- radeon_ring_write(ring, lower_32_bits(gpu_addr));
+- radeon_ring_write(ring, upper_32_bits(gpu_addr));
+- radeon_ring_write(ring, 1); /* number of DWs to follow */
+- radeon_ring_write(ring, 0xDEADBEEF);
++
++ if (rdev->family == CHIP_LIVERPOOL) {
++ /* SDMA_OPCODE_WRITE is broken on Liverpool when used in the
++ * ring (works in IBs) */
++ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0,
++ SDMA_CONSTANT_FILL_EXTRA_SIZE(2)));
++ radeon_ring_write(ring, lower_32_bits(gpu_addr));
++ radeon_ring_write(ring, upper_32_bits(gpu_addr));
++ radeon_ring_write(ring, 0xDEADBEEF); /* Fill value */
++ radeon_ring_write(ring, 4); /* number of bytes */
++ } else {
++ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE,
++ SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
++ radeon_ring_write(ring, lower_32_bits(gpu_addr));
++ radeon_ring_write(ring, upper_32_bits(gpu_addr));
++ radeon_ring_write(ring, 1); /* number of DWs to follow */
++ radeon_ring_write(ring, 0xDEADBEEF);
++ }
+ radeon_ring_unlock_commit(rdev, ring, false);
+
+ for (i = 0; i < rdev->usec_timeout; i++) {
+@@ -684,7 +709,11 @@ int cik_sdma_ring_test(struct radeon_device *rdev,
+ } else {
+ DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
+ ring->idx, tmp);
+- r = -EINVAL;
++
++ // TODO (ps4patches): rip errors i guess
++ if (rdev->family != CHIP_LIVERPOOL) {
++ r = -EINVAL;
++ }
+ }
+ return r;
+ }
+diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
+index cda16fcd43bb..e4be5298496f 100644
+--- a/drivers/gpu/drm/radeon/cikd.h
++++ b/drivers/gpu/drm/radeon/cikd.h
+@@ -534,10 +534,27 @@
+ #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
+ #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
+ #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
++#define VM_CONTEXT8_PAGE_TABLE_START_ADDR 0x1458
++#define VM_CONTEXT9_PAGE_TABLE_START_ADDR 0x145c
++#define VM_CONTEXT10_PAGE_TABLE_START_ADDR 0x1460
++#define VM_CONTEXT11_PAGE_TABLE_START_ADDR 0x1464
++#define VM_CONTEXT12_PAGE_TABLE_START_ADDR 0x1468
++#define VM_CONTEXT13_PAGE_TABLE_START_ADDR 0x146c
++#define VM_CONTEXT14_PAGE_TABLE_START_ADDR 0x1470
++#define VM_CONTEXT15_PAGE_TABLE_START_ADDR 0x1474
+
+ #define VM_INVALIDATE_REQUEST 0x1478
+ #define VM_INVALIDATE_RESPONSE 0x147c
+
++#define VM_CONTEXT8_PAGE_TABLE_END_ADDR 0x1480
++#define VM_CONTEXT9_PAGE_TABLE_END_ADDR 0x1484
++#define VM_CONTEXT10_PAGE_TABLE_END_ADDR 0x1488
++#define VM_CONTEXT11_PAGE_TABLE_END_ADDR 0x148c
++#define VM_CONTEXT12_PAGE_TABLE_END_ADDR 0x1490
++#define VM_CONTEXT13_PAGE_TABLE_END_ADDR 0x1494
++#define VM_CONTEXT14_PAGE_TABLE_END_ADDR 0x1498
++#define VM_CONTEXT15_PAGE_TABLE_END_ADDR 0x149c
++
+ #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
+ #define PROTECTIONS_MASK (0xf << 0)
+ #define PROTECTIONS_SHIFT 0
+@@ -573,6 +590,13 @@
+ #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
+ #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
+
++#define VM_CONTEXT2_PAGE_TABLE_START_ADDR 0x1564
++#define VM_CONTEXT3_PAGE_TABLE_START_ADDR 0x1568
++#define VM_CONTEXT4_PAGE_TABLE_START_ADDR 0x156c
++#define VM_CONTEXT5_PAGE_TABLE_START_ADDR 0x1570
++#define VM_CONTEXT6_PAGE_TABLE_START_ADDR 0x1574
++#define VM_CONTEXT7_PAGE_TABLE_START_ADDR 0x1578
++
+ #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
+ #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
+
+diff --git a/drivers/gpu/drm/radeon/ps4_bridge.c b/drivers/gpu/drm/radeon/ps4_bridge.c
+new file mode 100644
+index 000000000000..1c1cb0b4dabb
+--- /dev/null
++++ b/drivers/gpu/drm/radeon/ps4_bridge.c
+@@ -0,0 +1,758 @@
++/*
++ * Panasonic MN86471A / MN864729 DP->HDMI bridge driver (via PS4 Aeolia ICC interface)
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <asm/ps4.h>
++
++#include <drm/drm_crtc.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/drm_atomic_helper.h>
++#include <drm/drm_edid.h>
++#include <drm/drmP.h>
++
++#include "radeon_mode.h"
++#include "ObjectID.h"
++
++#define CMD_READ 1, 1
++#define CMD_WRITE 2, 2
++#define CMD_MASK 2, 3
++#define CMD_DELAY 3, 1
++#define CMD_WAIT_SET 3, 2
++#define CMD_WAIT_CLEAR 3, 3
++
++#define TSYSCTRL 0x7005
++# define TSYSCTRL_HDMI BIT(7)
++
++#define TSRST 0x7006
++# define TSRST_AVCSRST BIT(0)
++# define TSRST_ENCSRST BIT(1)
++# define TSRST_FIFOSRST BIT(2)
++# define TSRST_CCSRST BIT(3)
++# define TSRST_HDCPSRST BIT(4)
++# define TSRST_AUDSRST BIT(6)
++# define TSRST_VIFSRST BIT(7)
++
++#define TMONREG 0x7008
++# define TMONREG_HPD BIT(3)
++
++#define TDPCMODE 0x7009
++
++
++#define UPDCTRL 0x7011
++# define UPDCTRL_ALLUPD BIT(7)
++# define UPDCTRL_AVIIUPD BIT(6)
++# define UPDCTRL_AUDIUPD BIT(5)
++# define UPDCTRL_CLKUPD BIT(4)
++# define UPDCTRL_HVSIUPD BIT(3)
++# define UPDCTRL_VIFUPD BIT(2)
++# define UPDCTRL_AUDUPD BIT(1)
++# define UPDCTRL_CSCUPD BIT(0)
++
++
++#define VINCNT 0x7040
++# define VINCNT_VIF_FILEN BIT(6)
++
++#define VMUTECNT 0x705f
++# define VMUTECNT_CCVMUTE BIT(7)
++# define VMUTECNT_DUMON BIT(6)
++# define VMUTECNT_LINEWIDTH_80 (0<<4)
++# define VMUTECNT_LINEWIDTH_90 (1<<4)
++# define VMUTECNT_LINEWIDTH_180 (2<<4)
++# define VMUTECNT_LINEWIDTH_360 (3<<4)
++# define VMUTECNT_VMUTE_MUTE_ASYNC 1
++# define VMUTECNT_VMUTE_MUTE_NORMAL 2
++# define VMUTECNT_VMUTE_MUTE_RAMPA 4
++# define VMUTECNT_VMUTE_MUTE_RAMPB 8
++# define VMUTECNT_VMUTE_MUTE_COLORBAR_RGB 10
++# define VMUTECNT_VMUTE_MUTE_TOGGLE 12
++# define VMUTECNT_VMUTE_MUTE_COLORBAR_YCBCR 14
++
++#define CSCMOD 0x70c0
++#define C420SET 0x70c2
++#define OUTWSET 0x70c3
++
++#define PKTENA 0x7202
++
++#define INFENA 0x7203
++# define INFENA_AVIEN BIT(6)
++
++#define AKESTA 0x7a84
++# define AKESTA_BUSY BIT(0)
++
++#define AKESRST 0x7a88
++
++#define HDCPEN 0x7a8b
++# define HDCPEN_NONE 0x00
++# define HDCPEN_ENC_EN 0x03
++# define HDCPEN_ENC_DIS 0x05
++
++#define PCI_VENDOR_ID_AMD 0x1002
++#define PCI_DEVICE_ID_CUH_11XX 0x9920
++#define PCI_DEVICE_ID_CUH_12XX 0x9922
++#define PCI_DEVICE_ID_CUH_2XXX 0x9923
++#define PCI_DEVICE_ID_CUH_7XXX 0x9924
++
++struct i2c_cmd_hdr {
++ u8 major;
++ u8 length;
++ u8 minor;
++ u8 count;
++} __packed;
++
++struct i2c_cmdqueue {
++ struct {
++ u8 code;
++ u16 length;
++ u8 count;
++ u8 cmdbuf[0x7ec];
++ } __packed req;
++ struct {
++ u8 res1, res2;
++ u8 unk1, unk2;
++ u8 count;
++ u8 databuf[0x7eb];
++ } __packed reply;
++
++ u8 *p;
++ struct i2c_cmd_hdr *cmd;
++};
++
++struct radeon_ps4_bridge {
++ struct drm_connector *connector;
++ struct drm_encoder *encoder;
++ struct drm_bridge bridge;
++ struct i2c_cmdqueue cq;
++ struct mutex mutex;
++
++ int mode;
++};
++
++/* this should really be taken care of by the connector, but that is currently
++ * contained/owned by radeon_connector so just use a global for now */
++static struct radeon_ps4_bridge g_bridge = {
++ .mutex = __MUTEX_INITIALIZER(g_bridge.mutex)
++};
++
++static void cq_init(struct i2c_cmdqueue *q, u8 code)
++{
++ q->req.code = code;
++ q->req.count = 0;
++ q->p = q->req.cmdbuf;
++ q->cmd = NULL;
++}
++
++static void cq_cmd(struct i2c_cmdqueue *q, u8 major, u8 minor)
++{
++ if (!q->cmd || q->cmd->major != major || q->cmd->minor != minor) {
++ if (q->cmd)
++ q->cmd->length = q->p - (u8 *)q->cmd;
++ q->cmd = (struct i2c_cmd_hdr *)q->p;
++ q->cmd->major = major;
++ q->cmd->minor = minor;
++ q->cmd->length = 0;
++ q->cmd->count = 1;
++ q->req.count += 1;
++ q->p += sizeof(*q->cmd);
++ } else {
++ q->cmd->count += 1;
++ }
++}
++
++static int cq_exec(struct i2c_cmdqueue *q)
++{
++ int res;
++
++ if (!q->cmd)
++ return 0;
++
++ q->cmd->length = q->p - (u8 *)q->cmd;
++ q->req.length = q->p - (u8 *)&q->req;
++
++ res = apcie_icc_cmd(0x10, 0, &q->req, q->req.length,
++ &q->reply, sizeof(q->reply));
++
++ if (res < 5) {
++ DRM_ERROR("icc i2c commandqueue failed: %d\n", res);
++ return -EIO;
++ }
++ if (q->reply.res1 != 0 || q->reply.res2) {
++ DRM_ERROR("icc i2c commandqueue failed: %d, %d\n",
++ q->reply.res1, q->reply.res2);
++ return -EIO;
++ }
++
++ return res;
++}
++
++static void cq_read(struct i2c_cmdqueue *q, u16 addr, u8 count)
++{
++ cq_cmd(q, CMD_READ);
++ *q->p++ = count;
++ *q->p++ = addr >> 8;
++ *q->p++ = addr & 0xff;
++ *q->p++ = 0;
++}
++
++static void cq_writereg(struct i2c_cmdqueue *q, u16 addr, u8 data)
++{
++ cq_cmd(q, CMD_WRITE);
++ *q->p++ = 1;
++ *q->p++ = addr >> 8;
++ *q->p++ = addr & 0xff;
++ *q->p++ = data;
++}
++
++#if 0
++static void cq_write(struct i2c_cmdqueue *q, u16 addr, u8 *data, u8 count)
++{
++ cq_cmd(q, CMD_WRITE);
++ *q->p++ = count;
++ *q->p++ = addr >> 8;
++ *q->p++ = addr & 0xff;
++ while (count--)
++ *q->p++ = *data++;
++}
++#endif
++
++static void cq_mask(struct i2c_cmdqueue *q, u16 addr, u8 value, u8 mask)
++{
++ cq_cmd(q, CMD_MASK);
++ *q->p++ = 1;
++ *q->p++ = addr >> 8;
++ *q->p++ = addr & 0xff;
++ *q->p++ = value;
++ *q->p++ = mask;
++}
++
++#if 0
++static void cq_delay(struct i2c_cmdqueue *q, u16 time)
++{
++ cq_cmd(q, CMD_DELAY);
++ *q->p++ = 0;
++ *q->p++ = time & 0xff;
++ *q->p++ = time>>8;
++ *q->p++ = 0;
++}
++#endif
++
++static void cq_wait_set(struct i2c_cmdqueue *q, u16 addr, u8 mask)
++{
++ cq_cmd(q, CMD_WAIT_SET);
++ *q->p++ = 0;
++ *q->p++ = addr >> 8;
++ *q->p++ = addr & 0xff;
++ *q->p++ = mask;
++}
++
++static void cq_wait_clear(struct i2c_cmdqueue *q, u16 addr, u8 mask)
++{
++ cq_cmd(q, CMD_WAIT_CLEAR);
++ *q->p++ = 0;
++ *q->p++ = addr >> 8;
++ *q->p++ = addr & 0xff;
++ *q->p++ = mask;
++}
++
++static inline struct radeon_ps4_bridge *
++ bridge_to_radeon_ps4_bridge(struct drm_bridge *bridge)
++{
++ return container_of(bridge, struct radeon_ps4_bridge, bridge);
++}
++
++static void radeon_ps4_bridge_mode_set(struct drm_bridge *bridge,
++ struct drm_display_mode *mode,
++ struct drm_display_mode *adjusted_mode)
++{
++ struct radeon_ps4_bridge *mn_bridge = bridge_to_radeon_ps4_bridge(bridge);
++
++ /* This gets called before pre_enable/enable, so we just stash
++ * the vic ID for later */
++ mn_bridge->mode = drm_match_cea_mode(adjusted_mode);
++ DRM_DEBUG_KMS("vic mode: %d\n", mn_bridge->mode);
++ if (!mn_bridge->mode) {
++ DRM_ERROR("attempted to set non-CEA mode\n");
++ }
++}
++
++static void radeon_ps4_bridge_pre_enable(struct drm_bridge *bridge)
++{
++ struct radeon_ps4_bridge *mn_bridge = bridge_to_radeon_ps4_bridge(bridge);
++ DRM_DEBUG_KMS("radeon_ps4_bridge_pre_enable\n");
++
++ mutex_lock(&mn_bridge->mutex);
++ cq_init(&mn_bridge->cq, 4);
++
++#if 0
++ /* No idea. DP stuff probably. This borks for some reason. Meh. */
++ cq_writereg(&mn_bridge->cq, 0x7657,0xff);
++ cq_writereg(&mn_bridge->cq, 0x76a5,0x80);
++ cq_writereg(&mn_bridge->cq, 0x76a6,0x04);
++ cq_writereg(&mn_bridge->cq, 0x7601,0x0a);
++ cq_writereg(&mn_bridge->cq, 0x7602,0x84);
++ cq_writereg(&mn_bridge->cq, 0x7603,0x00);
++ cq_writereg(&mn_bridge->cq, 0x76a8,0x09);
++ cq_writereg(&mn_bridge->cq, 0x76ae,0xd1);
++ cq_writereg(&mn_bridge->cq, 0x76af,0x50);
++ cq_writereg(&mn_bridge->cq, 0x76b0,0x70);
++ cq_writereg(&mn_bridge->cq, 0x76b1,0xb0);
++ cq_writereg(&mn_bridge->cq, 0x76b2,0xf0);
++ cq_writereg(&mn_bridge->cq, 0x76db,0x00);
++ cq_writereg(&mn_bridge->cq, 0x76dc,0x64);
++ cq_writereg(&mn_bridge->cq, 0x76dd,0x22);
++ cq_writereg(&mn_bridge->cq, 0x76e4,0x00);
++ cq_writereg(&mn_bridge->cq, 0x76e6,0x1e); /* 0 for (DP?) scramble off */
++ cq_writereg(&mn_bridge->cq, 0x7670,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7671,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7672,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7673,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7668,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7669,0xff);
++ cq_writereg(&mn_bridge->cq, 0x766a,0xff);
++ cq_writereg(&mn_bridge->cq, 0x766b,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7655,0x04);
++ cq_writereg(&mn_bridge->cq, 0x7007,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7098,0xff);
++ cq_writereg(&mn_bridge->cq, 0x7099,0x00);
++ cq_writereg(&mn_bridge->cq, 0x709a,0x0f);
++ cq_writereg(&mn_bridge->cq, 0x709b,0x00);
++ cq_writereg(&mn_bridge->cq, 0x709c,0x50);
++ cq_writereg(&mn_bridge->cq, 0x709d,0x00);
++ cq_writereg(&mn_bridge->cq, 0x709e,0x00);
++ cq_writereg(&mn_bridge->cq, 0x709f,0xd0);
++ cq_writereg(&mn_bridge->cq, 0x7a9c,0x2e);
++ cq_writereg(&mn_bridge->cq, 0x7021,0x04);
++ cq_writereg(&mn_bridge->cq, 0x7028,0x00);
++ cq_writereg(&mn_bridge->cq, 0x7030,0xa3);
++ cq_writereg(&mn_bridge->cq, 0x7016,0x04);
++#endif
++
++ /* Disable InfoFrames */
++ cq_writereg(&mn_bridge->cq, INFENA, 0x00);
++ /* Reset HDCP */
++ cq_writereg(&mn_bridge->cq, TSRST, TSRST_ENCSRST | TSRST_HDCPSRST);
++ /* Disable HDCP flag */
++ cq_writereg(&mn_bridge->cq, TSRST, HDCPEN_ENC_DIS);
++ /* HDCP AKE reset */
++ cq_writereg(&mn_bridge->cq, AKESRST, 0xff);
++ /* Wait AKE busy */
++ cq_wait_clear(&mn_bridge->cq, AKESTA, AKESTA_BUSY);
++
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("failed to run pre-enable sequence");
++ }
++ mutex_unlock(&mn_bridge->mutex);
++}
++
++static void radeon_ps4_bridge_enable(struct drm_bridge *bridge)
++{
++ struct radeon_ps4_bridge *mn_bridge = bridge_to_radeon_ps4_bridge(bridge);
++ struct drm_connector *connector = mn_bridge->connector;
++ struct drm_device *dev = connector->dev;
++ struct pci_dev *pdev = dev->pdev;
++ u8 dp[3];
++
++ if (!mn_bridge->mode) {
++ DRM_ERROR("mode not available\n");
++ return;
++ }
++
++ if(pdev->vendor != PCI_VENDOR_ID_AMD) {
++ DRM_ERROR("Invalid vendor: %04x", pdev->vendor);
++ return;
++ }
++
++ DRM_DEBUG_KMS("radeon_ps4_bridge_enable (mode: %d)\n", mn_bridge->mode);
++
++ /* Here come the dragons */
++
++ if(pdev->device == PCI_DEVICE_ID_CUH_11XX)
++ {
++ /* Panasonic MN86471A */
++ mutex_lock(&mn_bridge->mutex);
++ cq_init(&mn_bridge->cq, 4);
++
++ /* Read DisplayPort status (?) */
++ cq_read(&mn_bridge->cq, 0x76e1, 3);
++ if (cq_exec(&mn_bridge->cq) < 11) {
++ mutex_unlock(&mn_bridge->mutex);
++ DRM_ERROR("could not read DP status");
++ return;
++ }
++ memcpy(dp, &mn_bridge->cq.reply.databuf[3], 3);
++
++ cq_init(&mn_bridge->cq, 4);
++
++ /* Wait for DP lane status */
++ cq_wait_set(&mn_bridge->cq, 0x761e, 0x77);
++ cq_wait_set(&mn_bridge->cq, 0x761f, 0x77);
++ /* Wait for ?? */
++ cq_wait_set(&mn_bridge->cq, 0x7669, 0x01);
++ cq_writereg(&mn_bridge->cq, 0x76d9, (dp[0] & 0x1f) | (dp[0] << 5));
++ cq_writereg(&mn_bridge->cq, 0x76da, (dp[1] & 0x7c) | ((dp[0] >> 3) & 3) | ((dp[1] << 5) & 0x80));
++ cq_writereg(&mn_bridge->cq, 0x76db, 0x80 | ((dp[1] >> 3) & 0xf));
++ cq_writereg(&mn_bridge->cq, 0x76e4, 0x01);
++ cq_writereg(&mn_bridge->cq, TSYSCTRL, TSYSCTRL_HDMI);
++ cq_writereg(&mn_bridge->cq, VINCNT, VINCNT_VIF_FILEN);
++ cq_writereg(&mn_bridge->cq, 0x7071, 0);
++ cq_writereg(&mn_bridge->cq, 0x7062, mn_bridge->mode);
++ cq_writereg(&mn_bridge->cq, 0x765a, 0);
++ cq_writereg(&mn_bridge->cq, 0x7062, mn_bridge->mode | 0x80);
++ cq_writereg(&mn_bridge->cq, 0x7215, 0x28); /* aspect */
++ cq_writereg(&mn_bridge->cq, 0x7217, mn_bridge->mode);
++ cq_writereg(&mn_bridge->cq, 0x7218, 0);
++ cq_writereg(&mn_bridge->cq, CSCMOD, 0xdc);
++ cq_writereg(&mn_bridge->cq, C420SET, 0xaa);
++ cq_writereg(&mn_bridge->cq, TDPCMODE, 0x4a);
++ cq_writereg(&mn_bridge->cq, OUTWSET, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x70c4, 0x08);
++ cq_writereg(&mn_bridge->cq, 0x70c5, 0x08);
++ cq_writereg(&mn_bridge->cq, 0x7096, 0xff);
++ cq_writereg(&mn_bridge->cq, 0x7027, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7020, 0x20);
++ cq_writereg(&mn_bridge->cq, 0x700b, 0x01);
++ cq_writereg(&mn_bridge->cq, PKTENA, 0x20);
++ cq_writereg(&mn_bridge->cq, 0x7096, 0xff);
++ cq_writereg(&mn_bridge->cq, INFENA, INFENA_AVIEN);
++ cq_writereg(&mn_bridge->cq, UPDCTRL, UPDCTRL_ALLUPD | UPDCTRL_AVIIUPD |
++ UPDCTRL_CLKUPD | UPDCTRL_VIFUPD |
++ UPDCTRL_CSCUPD);
++ cq_wait_set(&mn_bridge->cq, 0x7096, 0x80);
++
++ cq_mask(&mn_bridge->cq, 0x7216, 0x00, 0x80);
++ cq_writereg(&mn_bridge->cq, 0x7218, 0x00);
++
++ cq_writereg(&mn_bridge->cq, 0x7096, 0xff);
++ cq_writereg(&mn_bridge->cq, VMUTECNT, VMUTECNT_LINEWIDTH_90 | VMUTECNT_VMUTE_MUTE_NORMAL);
++ cq_writereg(&mn_bridge->cq, 0x7016, 0x04);
++ cq_writereg(&mn_bridge->cq, 0x7a88, 0xff);
++ cq_writereg(&mn_bridge->cq, 0x7a83, 0x88);
++ cq_writereg(&mn_bridge->cq, 0x7204, 0x40);
++
++ cq_wait_set(&mn_bridge->cq, 0x7096, 0x80);
++
++ cq_writereg(&mn_bridge->cq, 0x7006, 0x02);
++ cq_writereg(&mn_bridge->cq, 0x7020, 0x21);
++ cq_writereg(&mn_bridge->cq, 0x7a8b, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7020, 0x21);
++
++ cq_writereg(&mn_bridge->cq, VMUTECNT, VMUTECNT_LINEWIDTH_90);
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("Failed to configure ps4-bridge (MN86471A) mode\n");
++ }
++ #if 1
++ // preinit
++ cq_init(&mn_bridge->cq, 4);
++ cq_writereg(&mn_bridge->cq,0x70b3, 0x00);
++ cq_writereg(&mn_bridge->cq,0x70b7, 0x0b);
++ cq_writereg(&mn_bridge->cq,0x70a8, 0x24);
++
++ cq_mask(&mn_bridge->cq,0x70b9, 0x06, 0x06);
++ cq_mask(&mn_bridge->cq,0x70b6, 0x02, 0x0f);
++ cq_mask(&mn_bridge->cq,0x70ba, 0x40, 0x70);
++ cq_mask(&mn_bridge->cq,0x70b2, 0x20, 0xe0);
++ cq_mask(&mn_bridge->cq,0x7257, 0x00, 0xff);
++ cq_mask(&mn_bridge->cq,0x70b0, 0x01, 0x21);
++ cq_mask(&mn_bridge->cq,0x70ba, 0x00, 0x88);
++ cq_mask(&mn_bridge->cq,0x70b9, 0x01, 0x01);
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("failed to run enable MN86471A hdmi audio seq. 0");
++ }
++
++ cq_init(&mn_bridge->cq, 4);
++ cq_writereg(&mn_bridge->cq,0x7ed8, 0x01);
++
++ cq_mask(&mn_bridge->cq,0x70b4, 0x00, 0x3e);
++ cq_mask(&mn_bridge->cq,0x70b5, 0x79, 0xff);
++ cq_mask(&mn_bridge->cq,0x70ab, 0x00, 0xff);
++ cq_mask(&mn_bridge->cq,0x70b6, 0x02, 0x3f);
++ cq_mask(&mn_bridge->cq,0x70b7, 0x0b, 0x0f);
++ cq_mask(&mn_bridge->cq,0x70ac, 0x00, 0xff);
++ cq_mask(&mn_bridge->cq,0x70bd, 0x00, 0xff);
++
++ cq_writereg(&mn_bridge->cq, 0x7204, 0x10);
++ cq_writereg(&mn_bridge->cq,0x7011, 0xa2);
++
++ cq_wait_set(&mn_bridge->cq,0x7096, 0x80);
++ cq_writereg(&mn_bridge->cq,0x7096, 0xff);
++
++ cq_mask(&mn_bridge->cq,0x7203, 0x10, 0x10);
++ cq_writereg(&mn_bridge->cq,0x70b1, 0xc0);
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("failed to run enable hdmi MN86471A audio seq. 1");
++ }
++ #endif
++ mutex_unlock(&mn_bridge->mutex);
++ }
++ else
++ {
++ /* Panasonic MN864729 */
++ mutex_lock(&mn_bridge->mutex);
++ cq_init(&mn_bridge->cq, 4);
++ cq_mask(&mn_bridge->cq, 0x6005, 0x01, 0x01);
++ cq_writereg(&mn_bridge->cq, 0x6a03, 0x47);
++
++ /* Wait for DP lane status */
++ cq_wait_set(&mn_bridge->cq, 0x60f8, 0xff);
++ cq_wait_set(&mn_bridge->cq, 0x60f9, 0x01);
++ cq_writereg(&mn_bridge->cq, 0x6a01, 0x4d);
++ cq_wait_set(&mn_bridge->cq, 0x60f9, 0x1a);
++
++ cq_mask(&mn_bridge->cq, 0x1e00, 0x00, 0x21);
++ cq_mask(&mn_bridge->cq, 0x1e02, 0x00, 0x70);
++
++ cq_writereg(&mn_bridge->cq, 0x6020, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7402, 0x1c);
++ cq_writereg(&mn_bridge->cq, 0x6020, 0x04);
++ cq_writereg(&mn_bridge->cq, TSYSCTRL, TSYSCTRL_HDMI);
++ cq_writereg(&mn_bridge->cq, 0x10c7, 0x38);
++ cq_writereg(&mn_bridge->cq, 0x1e02, 0x88);
++ cq_writereg(&mn_bridge->cq, 0x1e00, 0x66);
++ cq_writereg(&mn_bridge->cq, 0x100c, 0x01);
++ cq_writereg(&mn_bridge->cq, TSYSCTRL, TSYSCTRL_HDMI);
++
++ cq_writereg(&mn_bridge->cq, 0x7009, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7040, 0x42);
++ cq_writereg(&mn_bridge->cq, 0x7225, 0x28);
++ cq_writereg(&mn_bridge->cq, 0x7227, mn_bridge->mode);
++ cq_writereg(&mn_bridge->cq, 0x7228, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7070, mn_bridge->mode);
++ cq_writereg(&mn_bridge->cq, 0x7071, mn_bridge->mode | 0x80);
++ cq_writereg(&mn_bridge->cq, 0x7072, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7073, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7074, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x7075, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x70c4, 0x0a);
++ cq_writereg(&mn_bridge->cq, 0x70c5, 0x0a);
++ cq_writereg(&mn_bridge->cq, 0x70c2, 0x00);
++ cq_writereg(&mn_bridge->cq, 0x70fe, 0x12);
++ cq_writereg(&mn_bridge->cq, 0x70c3, 0x10);
++
++ if(pdev->device == PCI_DEVICE_ID_CUH_12XX) {
++ /* newer ps4 phats need here 0x03 idk why. */
++ cq_writereg(&mn_bridge->cq, 0x10c5, 0x03);
++ } else {
++ cq_writereg(&mn_bridge->cq, 0x10c5, 0x00);
++ }
++
++ cq_writereg(&mn_bridge->cq, 0x10f6, 0xff);
++ cq_writereg(&mn_bridge->cq, 0x7202, 0x20);
++ cq_writereg(&mn_bridge->cq, 0x7203, 0x60);
++ cq_writereg(&mn_bridge->cq, 0x7011, 0xd5);
++ //cq_writereg(&mn_bridge->cq, 0x7a00, 0x0e);
++
++ cq_wait_set(&mn_bridge->cq, 0x10f6, 0x80);
++ cq_mask(&mn_bridge->cq, 0x7226, 0x00, 0x80);
++ cq_mask(&mn_bridge->cq, 0x7228, 0x00, 0xFF);
++ cq_writereg(&mn_bridge->cq, 0x7204, 0x40);
++ cq_wait_clear(&mn_bridge->cq, 0x7204, 0x40);
++ cq_writereg(&mn_bridge->cq, 0x7a8b, 0x05);
++ cq_mask(&mn_bridge->cq, 0x1e02, 0x70, 0x70);
++ cq_mask(&mn_bridge->cq, 0x1034, 0x02, 0x02);
++ cq_mask(&mn_bridge->cq, 0x1e00, 0x01, 0x01);
++ cq_writereg(&mn_bridge->cq, VMUTECNT, VMUTECNT_LINEWIDTH_90);
++ cq_writereg(&mn_bridge->cq, HDCPEN, 0x00);
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("Failed to configure ps4-bridge (MN864729) mode\n");
++ }
++ #if 1
++ // AUDIO preinit
++ cq_init(&mn_bridge->cq, 4);
++ cq_writereg(&mn_bridge->cq,0x70aa, 0x00);
++ cq_writereg(&mn_bridge->cq,0x70af, 0x07);
++ cq_writereg(&mn_bridge->cq,0x70a9, 0x5a);
++
++ cq_mask(&mn_bridge->cq,0x70af, 0x06, 0x06);
++ cq_mask(&mn_bridge->cq,0x70af, 0x02, 0x0f);
++ cq_mask(&mn_bridge->cq,0x70b3, 0x02, 0x0f);
++ cq_mask(&mn_bridge->cq,0x70ae, 0x80, 0xe0);
++ cq_mask(&mn_bridge->cq,0x70ae, 0x01, 0x07);
++ cq_mask(&mn_bridge->cq,0x70ac, 0x01, 0x21);
++ cq_mask(&mn_bridge->cq,0x70ab, 0x80, 0x88);
++ cq_mask(&mn_bridge->cq,0x70a9, 0x01, 0x01);
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("failed to run enable hdmi audio seq. 0");
++ }
++
++ cq_init(&mn_bridge->cq, 4);
++ cq_writereg(&mn_bridge->cq,0x70b0, 0x01);
++ cq_mask(&mn_bridge->cq,0x70b0, 0x00, 0xff);
++ cq_mask(&mn_bridge->cq,0x70b1, 0x79, 0xff);
++ cq_mask(&mn_bridge->cq,0x70b2, 0x00, 0xff);
++ cq_mask(&mn_bridge->cq,0x70b3, 0x02, 0xff);
++ cq_mask(&mn_bridge->cq,0x70b4, 0x0b, 0x0f);
++ cq_mask(&mn_bridge->cq,0x70b5, 0x00, 0xff);
++ cq_mask(&mn_bridge->cq,0x70b6, 0x00, 0xff);
++ cq_writereg(&mn_bridge->cq,0x10f6, 0xff);
++ cq_writereg(&mn_bridge->cq,0x7011, 0xa2);
++ cq_wait_set(&mn_bridge->cq,0x10f6, 0xa2);
++ cq_mask(&mn_bridge->cq,0x7267, 0x00, 0xff);
++ cq_writereg(&mn_bridge->cq,0x7204, 0x10);
++ cq_wait_clear(&mn_bridge->cq,0x7204, 0x10);
++ cq_writereg(&mn_bridge->cq,0x10f6, 0xff);
++ cq_mask(&mn_bridge->cq,0x7203, 0x10, 0x10);
++ cq_writereg(&mn_bridge->cq,0x70a8, 0xc0);
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("failed to run enable hdmi audio seq. 1");
++ }
++ #endif
++ mutex_unlock(&mn_bridge->mutex);
++ }
++
++}
++
++static void radeon_ps4_bridge_disable(struct drm_bridge *bridge)
++{
++ struct radeon_ps4_bridge *mn_bridge = bridge_to_radeon_ps4_bridge(bridge);
++ DRM_DEBUG_KMS("radeon_ps4_bridge_disable\n");
++
++ mutex_lock(&mn_bridge->mutex);
++ cq_init(&mn_bridge->cq, 4);
++ cq_writereg(&mn_bridge->cq, VMUTECNT, VMUTECNT_LINEWIDTH_90 | VMUTECNT_VMUTE_MUTE_NORMAL);
++ cq_writereg(&mn_bridge->cq, INFENA, 0x00);
++ if (cq_exec(&mn_bridge->cq) < 0) {
++ DRM_ERROR("Failed to disable bridge\n");
++ }
++ mutex_unlock(&mn_bridge->mutex);
++}
++
++static void radeon_ps4_bridge_post_disable(struct drm_bridge *bridge)
++{
++ /* struct radeon_ps4_bridge *mn_bridge = bridge_to_mn864729(bridge); */
++ DRM_DEBUG_KMS("radeon_ps4_bridge_post_disable\n");
++}
++
++/* Hardcoded modes, since we don't really know how to do custom modes yet.
++ * Other CEA modes *should* work (and are allowed if externally added) */
++
++/* 1 - 640x480@60Hz */
++static const struct drm_display_mode mode_480p = {
++ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
++ 752, 800, 0, 480, 490, 492, 525, 0,
++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
++ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3
++};
++/* 4 - 1280x720@60Hz */
++static const struct drm_display_mode mode_720p = {
++ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
++ 1430, 1650, 0, 720, 725, 730, 750, 0,
++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
++ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9
++};
++/* 16 - 1920x1080@60Hz */
++static const struct drm_display_mode mode_1080p = {
++ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
++ 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
++ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
++ .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9
++};
++
++int radeon_ps4_bridge_get_modes(struct drm_connector *connector)
++{
++ struct drm_device *dev = connector->dev;
++ struct drm_display_mode *newmode;
++ DRM_DEBUG_KMS("radeon_ps4_bridge_get_modes\n");
++
++ newmode = drm_mode_duplicate(dev, &mode_1080p);
++ drm_mode_probed_add(connector, newmode);
++
++ //newmode = drm_mode_duplicate(dev, &mode_720p);
++ //drm_mode_probed_add(connector, newmode);
++ //newmode = drm_mode_duplicate(dev, &mode_480p);
++ //drm_mode_probed_add(connector, newmode);
++
++ drm_mode_connector_update_edid_property(connector, NULL);
++
++ return 0;
++}
++
++enum drm_connector_status radeon_ps4_bridge_detect(struct drm_connector *connector,
++ bool force)
++{
++ struct radeon_ps4_bridge *mn_bridge = &g_bridge;
++ u8 reg;
++
++ struct radeon_connector *radeon_connector = to_radeon_connector(connector);
++ struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
++
++ radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
++ radeon_dp_getdpcd(radeon_connector);
++
++ mutex_lock(&mn_bridge->mutex);
++ cq_init(&mn_bridge->cq, 4);
++ cq_read(&mn_bridge->cq, TMONREG, 1);
++ if (cq_exec(&mn_bridge->cq) < 9) {
++ mutex_unlock(&mn_bridge->mutex);
++ DRM_ERROR("could not read TMONREG");
++ return connector_status_disconnected;
++ }
++ reg = mn_bridge->cq.reply.databuf[3];
++ mutex_unlock(&mn_bridge->mutex);
++
++ DRM_DEBUG_KMS("TMONREG=0x%02x\n", reg);
++
++ if (reg & TMONREG_HPD)
++ return connector_status_connected;
++ else
++ return connector_status_disconnected;
++}
++
++int radeon_ps4_bridge_mode_valid(struct drm_connector *connector,
++ struct drm_display_mode *mode)
++{
++ int vic = drm_match_cea_mode(mode);
++
++ /* Allow anything that we can match up to a VIC (CEA modes) */
++ if (!vic || (vic != 16 && vic != 4)) {
++ return MODE_BAD;
++ }
++
++ return MODE_OK;
++}
++
++static int radeon_ps4_bridge_attach(struct drm_bridge *bridge)
++{
++ /* struct radeon_ps4_bridge *mn_bridge = bridge_to_radeon_ps4_bridge(bridge); */
++
++ return 0;
++}
++
++static struct drm_bridge_funcs radeon_ps4_bridge_funcs = {
++ .pre_enable = radeon_ps4_bridge_pre_enable,
++ .enable = radeon_ps4_bridge_enable,
++ .disable = radeon_ps4_bridge_disable,
++ .post_disable = radeon_ps4_bridge_post_disable,
++ .attach = radeon_ps4_bridge_attach,
++ .mode_set = radeon_ps4_bridge_mode_set
++};
++
++int radeon_ps4_bridge_register(struct drm_connector *connector,
++ struct drm_encoder *encoder)
++{
++ int ret;
++ struct radeon_ps4_bridge *mn_bridge = &g_bridge;
++ //struct drm_device *dev = connector->dev;
++
++ mn_bridge->encoder = encoder;
++ mn_bridge->connector = connector;
++ mn_bridge->bridge.funcs = &radeon_ps4_bridge_funcs;
++ ret = drm_bridge_attach(mn_bridge->encoder, &mn_bridge->bridge, NULL, 0);
++ if (ret) {
++ DRM_ERROR("Failed to initialize bridge with drm\n");
++ return -EINVAL;
++ }
++
++ //encoder->bridge = &mn_bridge->bridge;
++ // TODO (ps4patches): This seems to be the new way of adding bridges
++ drm_bridge_add(&mn_bridge->bridge);
++
++ return 0;
++}
+diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
+index 895776c421d4..314fd436f3c9 100644
+--- a/drivers/gpu/drm/radeon/radeon.h
++++ b/drivers/gpu/drm/radeon/radeon.h
+@@ -2679,7 +2679,8 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
+ #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
+ #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
+ #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
+- (rdev->family == CHIP_MULLINS))
++ (rdev->family == CHIP_MULLINS || \
++ (rdev->family == CHIP_LIVERPOOL))
+
+ #define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \
+ (rdev->pdev->device == 0x6850) || \
+diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
+index bfacf8fe5cc1..8f6dfa22daed 100644
+--- a/drivers/gpu/drm/radeon/radeon_asic.c
++++ b/drivers/gpu/drm/radeon/radeon_asic.c
+@@ -2632,7 +2632,16 @@ int radeon_asic_init(struct radeon_device *rdev)
+ case CHIP_KAVERI:
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
++ case CHIP_LIVERPOOL:
++ if(rdev->family == CHIP_LIVERPOOL)
++ {
++ // TODO (ps4patches): Does this work?
++ kv_asic.copy.blit = &cik_copy_cpdma;
++ kv_asic.copy.blit_ring_index = R600_RING_TYPE_DMA_INDEX;
++ }
++
+ rdev->asic = &kv_asic;
++
+ /* set num crtcs */
+ if (rdev->family == CHIP_KAVERI) {
+ rdev->num_crtc = 4;
+@@ -2689,8 +2698,14 @@ int radeon_asic_init(struct radeon_device *rdev)
+ RADEON_PG_SUPPORT_RLC_SMU_HS |
+ RADEON_PG_SUPPORT_SAMU;*/
+ }
+- rdev->has_uvd = true;
+- rdev->has_vce = true;
++
++ if(rdev->family == CHIP_LIVERPOOL) {
++ rdev->has_uvd = false;
++ rdev->has_vce = false;
++ } else {
++ rdev->has_uvd = true;
++ rdev->has_vce = true;
++ }
+ break;
+ default:
+ /* FIXME: not supported yet */
+diff --git a/drivers/gpu/drm/radeon/radeon_audio.c b/drivers/gpu/drm/radeon/radeon_audio.c
+index 7c5e80d03fc9..ba877d0b73fd 100644
+--- a/drivers/gpu/drm/radeon/radeon_audio.c
++++ b/drivers/gpu/drm/radeon/radeon_audio.c
+@@ -273,8 +273,14 @@ int radeon_audio_init(struct radeon_device *rdev)
+ radeon_audio_interface_init(rdev);
+
+ /* disable audio. it will be set up later */
+- for (i = 0; i < rdev->audio.num_pins; i++)
+- radeon_audio_enable(rdev, &rdev->audio.pin[i], 0);
++ for (i = 0; i < rdev->audio.num_pins; i++) {
++ /* LVP has standalone S/PDIF on the third pin, always enable */
++ if (rdev->family == CHIP_LIVERPOOL) {
++ radeon_audio_enable(rdev, &rdev->audio.pin[i], 0xf);
++ } else {
++ radeon_audio_enable(rdev, &rdev->audio.pin[i], 0);
++ }
++ }
+
+ return 0;
+ }
+diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
+index d157bb9072e8..984323a541ba 100644
+--- a/drivers/gpu/drm/radeon/radeon_connectors.c
++++ b/drivers/gpu/drm/radeon/radeon_connectors.c
+@@ -1480,6 +1480,30 @@ static void radeon_dvi_force(struct drm_connector *connector)
+ radeon_connector->use_digital = true;
+ }
+
++#ifdef CONFIG_X86_PS4
++int radeon_ps4_bridge_get_modes(struct drm_connector *connector);
++enum drm_connector_status radeon_ps4_bridge_detect(struct drm_connector *connector,
++ bool force);
++int radeon_ps4_bridge_mode_valid(struct drm_connector *connector,
++ struct drm_display_mode *mode);
++
++static const struct drm_connector_helper_funcs radeon_ps4_dp_connector_helper_funcs = {
++ .get_modes = radeon_ps4_bridge_get_modes,
++ .mode_valid = radeon_ps4_bridge_mode_valid,
++ .best_encoder = radeon_dvi_encoder,
++};
++
++static const struct drm_connector_funcs radeon_ps4_dp_connector_funcs = {
++ .dpms = drm_helper_connector_dpms,
++ .detect = radeon_ps4_bridge_detect,
++ .fill_modes = drm_helper_probe_single_connector_modes,
++ //.set_property = radeon_connector_set_property,
++ .destroy = radeon_connector_destroy,
++ .force = radeon_dvi_force,
++};
++
++#endif
++
+ static enum drm_mode_status radeon_dvi_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+ {
+@@ -1879,6 +1903,7 @@ radeon_add_atom_connector(struct drm_device *dev,
+ uint32_t subpixel_order = SubPixelNone;
+ bool shared_ddc = false;
+ bool is_dp_bridge = false;
++ bool is_ps4_bridge = false;
+ bool has_aux = false;
+
+ if (connector_type == DRM_MODE_CONNECTOR_Unknown)
+@@ -1930,6 +1955,18 @@ radeon_add_atom_connector(struct drm_device *dev,
+ if (!radeon_connector)
+ return;
+
++ /* Liverpool (PS4) has an DP bridge which needs a special driver, and
++ * a fake HDMI port that doesn't really exist. */
++ if (rdev->family == CHIP_LIVERPOOL) {
++ if (connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
++ connector_type = DRM_MODE_CONNECTOR_HDMIA;
++ is_dp_bridge = true;
++ is_ps4_bridge = true;
++ } else {
++ return;
++ }
++ }
++
+ connector = &radeon_connector->base;
+
+ radeon_connector->connector_id = connector_id;
+@@ -1989,12 +2026,20 @@ radeon_add_atom_connector(struct drm_device *dev,
+ case DRM_MODE_CONNECTOR_HDMIA:
+ case DRM_MODE_CONNECTOR_HDMIB:
+ case DRM_MODE_CONNECTOR_DisplayPort:
+- drm_connector_init_with_ddc(dev, &radeon_connector->base,
+- &radeon_dp_connector_funcs,
+- connector_type,
+- ddc);
+- drm_connector_helper_add(&radeon_connector->base,
+- &radeon_dp_connector_helper_funcs);
++ if (is_ps4_bridge) {
++ drm_connector_init(dev, &radeon_connector->base,
++ &radeon_dp_connector_funcs, connector_type);
++ drm_connector_helper_add(&radeon_connector->base,
++ &radeon_dp_connector_helper_funcs);
++ } else {
++ drm_connector_init_with_ddc(dev, &radeon_connector->base,
++ &radeon_dp_connector_funcs,
++ connector_type,
++ ddc);
++ drm_connector_helper_add(&radeon_connector->base,
++ &radeon_dp_connector_helper_funcs);
++ }
++
+ drm_object_attach_property(&radeon_connector->base.base,
+ rdev->mode_info.underscan_property,
+ UNDERSCAN_OFF);
+diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
+index 1c005e0ddd38..efa4c92762dd 100644
+--- a/drivers/gpu/drm/radeon/radeon_device.c
++++ b/drivers/gpu/drm/radeon/radeon_device.c
+@@ -107,6 +107,7 @@ static const char radeon_family_name[][16] = {
+ "BONAIRE",
+ "KAVERI",
+ "KABINI",
++ "LIVERPOOL",
+ "HAWAII",
+ "MULLINS",
+ "LAST",
+diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
+index 573154268d43..c10008fd1ac4 100644
+--- a/drivers/gpu/drm/radeon/radeon_display.c
++++ b/drivers/gpu/drm/radeon/radeon_display.c
+@@ -688,7 +688,7 @@ static void radeon_crtc_init(struct drm_device *dev, int index)
+ radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
+ rdev->mode_info.crtcs[index] = radeon_crtc;
+
+- if (rdev->family >= CHIP_BONAIRE) {
++ if (rdev->family >= CHIP_BONAIRE && rdev->family != CHIP_LIVERPOOL) {
+ radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
+ radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
+ } else {
+diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
+index b74cebca1f89..3f72fc64df20 100644
+--- a/drivers/gpu/drm/radeon/radeon_drv.c
++++ b/drivers/gpu/drm/radeon/radeon_drv.c
+@@ -51,6 +51,11 @@
+ #include <drm/radeon_drm.h>
+
+ #include "radeon_drv.h"
++
++#ifdef CONFIG_X86_PS4
++#include <asm/ps4.h>
++#endif
++
+ #include "radeon.h"
+ #include "radeon_kms.h"
+ #include "radeon_ttm.h"
+@@ -334,6 +339,16 @@ static int radeon_pci_probe(struct pci_dev *pdev,
+ if (ret)
+ return ret;
+
++ #ifdef CONFIG_X86_PS4
++ /* On the PS4 (Liverpool graphics) we have a hard dependency on the
++ * Aeolia driver to set up the HDMI encoder which is connected to it,
++ * so defer probe until it is ready. This test passes if this isn't
++ * a PS4 (returns -ENODEV).
++ */
++ if (apcie_status() == 0)
++ return -EPROBE_DEFER;
++ #endif
++
+ dev = drm_dev_alloc(&kms_driver, &pdev->dev);
+ if (IS_ERR(dev))
+ return PTR_ERR(dev);
+diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
+index 46549d5179ee..abfc75d5d138 100644
+--- a/drivers/gpu/drm/radeon/radeon_encoders.c
++++ b/drivers/gpu/drm/radeon/radeon_encoders.c
+@@ -195,6 +195,22 @@ static void radeon_encoder_add_backlight(struct radeon_encoder *radeon_encoder,
+ }
+ }
+
++#ifdef CONFIG_X86_PS4
++int radeon_ps4_bridge_register(struct drm_connector *connector,
++ struct drm_encoder *encoder);
++
++static void radeon_maybe_add_bridge(struct drm_connector *connector,
++ struct drm_encoder *encoder)
++{
++ struct drm_device *dev = connector->dev;
++ struct radeon_device *rdev = dev->dev_private;
++
++ if (rdev->family == CHIP_LIVERPOOL) {
++ radeon_ps4_bridge_register(connector, encoder);
++ }
++}
++#endif
++
+ void
+ radeon_link_encoder_connector(struct drm_device *dev)
+ {
+@@ -209,6 +225,9 @@ radeon_link_encoder_connector(struct drm_device *dev)
+ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+ radeon_encoder = to_radeon_encoder(encoder);
+ if (radeon_encoder->devices & radeon_connector->devices) {
++ #ifdef CONFIG_X86_PS4
++ radeon_maybe_add_bridge(connector, encoder);
++ #endif
+ drm_connector_attach_encoder(connector, encoder);
+ if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
+ radeon_encoder_add_backlight(radeon_encoder, connector);
+diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h
+index 4b7b87f71a63..ca1a89fccbeb 100644
+--- a/drivers/gpu/drm/radeon/radeon_family.h
++++ b/drivers/gpu/drm/radeon/radeon_family.h
+@@ -97,6 +97,7 @@ enum radeon_family {
+ CHIP_KAVERI,
+ CHIP_KABINI,
+ CHIP_HAWAII,
++ CHIP_LIVERPOOL,
+ CHIP_MULLINS,
+ CHIP_LAST,
+ };
+diff --git a/drivers/gpu/drm/radeon/radeon_ib.c b/drivers/gpu/drm/radeon/radeon_ib.c
+index 62b116727b4f..a40e4f6b7b18 100644
+--- a/drivers/gpu/drm/radeon/radeon_ib.c
++++ b/drivers/gpu/drm/radeon/radeon_ib.c
+@@ -259,8 +259,15 @@ int radeon_ib_ring_tests(struct radeon_device *rdev)
+ {
+ unsigned i;
+ int r;
++ int num_rings = 0;
+
+- for (i = 0; i < RADEON_NUM_RINGS; ++i) {
++ if(rdev->family == CHIP_LIVERPOOL) {
++ num_rings = 1;
++ } else {
++ num_rings = RADEON_NUM_RINGS;
++ }
++
++ for (i = 0; i < num_rings; ++i) {
+ struct radeon_ring *ring = &rdev->ring[i];
+
+ if (!ring->ready)
+diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
+index c67b6ddb29a4..2dfb2c72ca12 100644
+--- a/drivers/gpu/drm/radeon/radeon_pm.c
++++ b/drivers/gpu/drm/radeon/radeon_pm.c
+@@ -1555,6 +1555,7 @@ int radeon_pm_init(struct radeon_device *rdev)
+ case CHIP_BONAIRE:
+ case CHIP_KABINI:
+ case CHIP_KAVERI:
++ case CHIP_LIVERPOOL:
+ case CHIP_HAWAII:
+ case CHIP_MULLINS:
+ /* DPM requires the RLC, RV770+ dGPU requires SMC */
+diff --git a/drivers/gpu/drm/radeon/radeon_ucode.h b/drivers/gpu/drm/radeon/radeon_ucode.h
+index dc4576e4d8ad..4896ea0d25a4 100644
+--- a/drivers/gpu/drm/radeon/radeon_ucode.h
++++ b/drivers/gpu/drm/radeon/radeon_ucode.h
+@@ -38,6 +38,8 @@
+ #define CIK_PFP_UCODE_SIZE 2144
+ #define CIK_ME_UCODE_SIZE 2144
+ #define CIK_CE_UCODE_SIZE 2144
++#define LIVERPOOL_PFP_UCODE_SIZE 4192
++#define LIVERPOOL_ME_UCODE_SIZE 4192
+
+ /* MEC */
+ #define CIK_MEC_UCODE_SIZE 4192
+@@ -53,6 +55,7 @@
+ #define KB_RLC_UCODE_SIZE 2560
+ #define KV_RLC_UCODE_SIZE 2560
+ #define ML_RLC_UCODE_SIZE 2560
++#define LIVERPOOL_RLC_UCODE_SIZE 1536
+
+ /* MC */
+ #define BTC_MC_UCODE_SIZE 6024
+diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
+index 2ea86919d953..42d4918dbb2c 100644
+--- a/drivers/gpu/drm/radeon/radeon_uvd.c
++++ b/drivers/gpu/drm/radeon/radeon_uvd.c
+@@ -124,6 +124,7 @@ int radeon_uvd_init(struct radeon_device *rdev)
+ case CHIP_BONAIRE:
+ case CHIP_KABINI:
+ case CHIP_KAVERI:
++ case CHIP_LIVERPOOL:
+ case CHIP_HAWAII:
+ case CHIP_MULLINS:
+ legacy_fw_name = FIRMWARE_BONAIRE_LEGACY;
+diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c
+index 511a942e851d..a5096b33cc5f 100644
+--- a/drivers/gpu/drm/radeon/radeon_vce.c
++++ b/drivers/gpu/drm/radeon/radeon_vce.c
+@@ -75,6 +75,7 @@ int radeon_vce_init(struct radeon_device *rdev)
+ case CHIP_BONAIRE:
+ case CHIP_KAVERI:
+ case CHIP_KABINI:
++ case CHIP_LIVERPOOL:
+ case CHIP_HAWAII:
+ case CHIP_MULLINS:
+ fw_name = FIRMWARE_BONAIRE;
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0004-feat-temperature-sensors.patch b/device/testing/linux-sony-ps4/0004-feat-temperature-sensors.patch
new file mode 100644
index 0000000000000000000000000000000000000000..c64dcb3bad57163d22558651263611c11e274b0d
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0004-feat-temperature-sensors.patch
@@ -0,0 +1,37 @@
+From e9382715a310fc01a375e6e3eff7b185ce4277b4 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Mon, 20 Dec 2021 14:01:45 +0100
+Subject: [PATCH 04/22] feat: temperature sensors
+
+---
+ drivers/hwmon/fam15h_power.c | 1 +
+ drivers/hwmon/k10temp.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon/fam15h_power.c
+index 521534d5c1e5..5b84627c7942 100644
+--- a/drivers/hwmon/fam15h_power.c
++++ b/drivers/hwmon/fam15h_power.c
+@@ -486,6 +486,7 @@ static const struct pci_device_id fam15h_power_id_table[] = {
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
++ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M41H_F4) },
+ {}
+ };
+ MODULE_DEVICE_TABLE(pci, fam15h_power_id_table);
+diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
+index 3618a924e78e..478672b391cb 100644
+--- a/drivers/hwmon/k10temp.c
++++ b/drivers/hwmon/k10temp.c
+@@ -487,6 +487,7 @@ static const struct pci_device_id k10temp_id_table[] = {
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
++ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M41H_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0005-feat-sdhci-support.patch b/device/testing/linux-sony-ps4/0005-feat-sdhci-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..0bdc1be46a62323dc78e498647fe964d89247d3c
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0005-feat-sdhci-support.patch
@@ -0,0 +1,147 @@
+From 0d69fe3288f2c3444a25c72847a6d670ab07c77b Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Mon, 20 Dec 2021 14:56:09 +0100
+Subject: [PATCH 05/22] feat: sdhci support
+
+---
+ drivers/mmc/host/sdhci-pci-core.c | 67 +++++++++++++++++++++++++++++++
+ drivers/mmc/host/sdhci-pci.h | 2 +
+ 2 files changed, 69 insertions(+)
+
+diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
+index 8736e04fa73c..d50a3658820d 100644
+--- a/drivers/mmc/host/sdhci-pci-core.c
++++ b/drivers/mmc/host/sdhci-pci-core.c
+@@ -37,6 +37,10 @@
+
+ #include "cqhci.h"
+
++#ifdef CONFIG_X86_PS4
++#include <asm/ps4.h>
++#endif
++
+ #include "sdhci.h"
+ #include "sdhci-pci.h"
+
+@@ -319,6 +323,54 @@ static const struct sdhci_pci_fixes sdhci_intel_qrk = {
+ .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
+ };
+
++#ifdef CONFIG_X86_PS4
++static int aeolia_probe(struct sdhci_pci_chip *chip)
++{
++ chip->num_slots = 1;
++ chip->first_bar = 0;
++ if (apcie_status() == 0)
++ return -EPROBE_DEFER;
++
++ chip->pdev->class &= ~0x0000FF;
++ chip->pdev->class |= PCI_SDHCI_IFDMA;
++ return 0;
++}
++
++static int aeolia_probe_slot(struct sdhci_pci_slot *slot)
++{
++ int err = apcie_assign_irqs(slot->chip->pdev, 1);
++ if (err <= 0) {
++ dev_err(&slot->chip->pdev->dev, "failed to get IRQ: %d\n", err);
++ return -ENODEV;
++ }
++ slot->host->irq = slot->chip->pdev->irq;
++ return 0;
++}
++
++static void aeolia_remove_slot(struct sdhci_pci_slot *slot, int dead)
++{
++ apcie_free_irqs(slot->chip->pdev->irq, 1);
++}
++
++static int aeolia_enable_dma(struct sdhci_pci_slot *slot)
++{
++ if (pci_set_dma_mask(slot->chip->pdev, DMA_BIT_MASK(31))) {
++ return -EINVAL;
++ }
++ if (pci_set_consistent_dma_mask(slot->chip->pdev, DMA_BIT_MASK(31))) {
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static const struct sdhci_pci_fixes sdhci_aeolia = {
++ .probe = aeolia_probe,
++ .probe_slot = aeolia_probe_slot,
++ .remove_slot = aeolia_remove_slot,
++ .enable_dma = aeolia_enable_dma,
++};
++#endif
++
+ static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
+ {
+ slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
+@@ -1974,6 +2026,12 @@ static const struct pci_device_id pci_ids[] = {
+ SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
+ SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
+ SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
++ #ifdef CONFIG_X86_PS4
++ SDHCI_PCI_DEVICE(SONY, AEOLIA_SDHCI, aeolia),
++ SDHCI_PCI_DEVICE(SONY, BELIZE_SDHCI, aeolia),
++ // TODO (ps4patches): What is this doing in comments?
++ //SDHCI_PCI_DEVICE(SONY, BAIKAL_SDHCI, aeolia),
++ #endif
+ SDHCI_PCI_DEVICE(GLI, 9750, gl9750),
+ SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
+ SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e),
+@@ -2008,6 +2066,10 @@ int sdhci_pci_enable_dma(struct sdhci_host *host)
+
+ pci_set_master(pdev);
+
++ if (slot->chip->fixes && slot->chip->fixes->enable_dma) {
++ return slot->chip->fixes->enable_dma(slot);
++ }
++
+ return 0;
+ }
+
+@@ -2361,6 +2423,7 @@ static int sdhci_pci_probe(struct pci_dev *pdev,
+ chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
+ }
+ chip->num_slots = slots;
++ chip->first_bar = first_bar;
+ chip->pm_retune = true;
+ chip->rpm_retune = true;
+
+@@ -2375,7 +2438,11 @@ static int sdhci_pci_probe(struct pci_dev *pdev,
+ slots = chip->num_slots; /* Quirk may have changed this */
+
+ for (i = 0; i < slots; i++) {
++ #ifdef CONFIG_X86_PS4
++ slot = sdhci_pci_probe_slot(pdev, chip, chip->first_bar, i);
++ #else
+ slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
++ #endif
+ if (IS_ERR(slot)) {
+ for (i--; i >= 0; i--)
+ sdhci_pci_remove_slot(chip->slots[i]);
+diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h
+index dcd99d5057ee..8caa7acbddb0 100644
+--- a/drivers/mmc/host/sdhci-pci.h
++++ b/drivers/mmc/host/sdhci-pci.h
+@@ -140,6 +140,7 @@ struct sdhci_pci_fixes {
+ int (*probe_slot) (struct sdhci_pci_slot *);
+ int (*add_host) (struct sdhci_pci_slot *);
+ void (*remove_slot) (struct sdhci_pci_slot *, int);
++ int (*enable_dma) (struct sdhci_pci_slot *);
+
+ #ifdef CONFIG_PM_SLEEP
+ int (*suspend) (struct sdhci_pci_chip *);
+@@ -181,6 +182,7 @@ struct sdhci_pci_chip {
+ const struct sdhci_pci_fixes *fixes;
+
+ int num_slots; /* Slots on controller */
++ int first_bar; /* First valid BAR */
+ struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
+ };
+
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0006-feat-ethernet-support.patch b/device/testing/linux-sony-ps4/0006-feat-ethernet-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..20487671083c096d34452cd3949dba5229605be2
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0006-feat-ethernet-support.patch
@@ -0,0 +1,323 @@
+From 905b33761e7344f07d4b2270896ebaa298d55047 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Mon, 20 Dec 2021 15:29:54 +0100
+Subject: [PATCH 06/22] feat: ethernet support
+
+---
+ drivers/net/ethernet/marvell/sky2.c | 164 +++++++++++++++++++++++++---
+ drivers/net/ethernet/marvell/sky2.h | 3 +
+ 2 files changed, 150 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/net/ethernet/marvell/sky2.c b/drivers/net/ethernet/marvell/sky2.c
+index e9fc74e54b22..66ee6f8ab1bd 100644
+--- a/drivers/net/ethernet/marvell/sky2.c
++++ b/drivers/net/ethernet/marvell/sky2.c
+@@ -38,6 +38,11 @@
+
+ #include <asm/irq.h>
+
++#ifdef CONFIG_X86_PS4
++#include <asm/ps4.h>
++#include "../../../ps4/aeolia.h"
++#endif
++
+ #include "sky2.h"
+
+ #define DRV_NAME "sky2"
+@@ -134,6 +139,9 @@ static const struct pci_device_id sky2_id_table[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
++ { PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_AEOLIA_GBE) },
++ { PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_BELIZE_GBE) },
++ { PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_BAIKAL_GBE) },
+ { 0 }
+ };
+
+@@ -154,7 +162,7 @@ static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
+
+ gma_write16(hw, port, GM_SMI_DATA, val);
+ gma_write16(hw, port, GM_SMI_CTRL,
+- GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
++ GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
+
+ for (i = 0; i < PHY_RETRIES; i++) {
+ u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
+@@ -179,7 +187,7 @@ static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
+ {
+ int i;
+
+- gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
++ gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(hw->phy_addr)
+ | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
+
+ for (i = 0; i < PHY_RETRIES; i++) {
+@@ -1375,7 +1383,7 @@ static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+
+ switch (cmd) {
+ case SIOCGMIIPHY:
+- data->phy_id = PHY_ADDR_MARV;
++ data->phy_id = hw->phy_addr;
+
+ fallthrough;
+ case SIOCGMIIREG: {
+@@ -3234,6 +3242,24 @@ static void sky2_reset(struct sky2_hw *hw)
+ int i;
+ u32 hwe_mask = Y2_HWE_ALL_MASK;
+
++ #ifdef CONFIG_X86_PS4
++ if (pdev->vendor == PCI_VENDOR_ID_SONY &&
++ pdev->device == PCI_DEVICE_ID_SONY_AEOLIA_GBE) {
++ u32 val1, val2;
++
++ sky2_write32(hw, 0x60, 0x32100);
++ sky2_write32(hw, 0x64, 6);
++ sky2_write32(hw, 0x68, 0x63b9c);
++ sky2_write32(hw, 0x6c, 0x300);
++ val1 = sky2_read32(hw, 0x158);
++ val2 = sky2_read32(hw, 0x160);
++ val1 &= ~0x33333333;
++ val2 &= ~0xCC00000;
++ sky2_write32(hw, 0x158, val1);
++ sky2_write32(hw, 0x160, val2);
++ }
++ #endif
++
+ /* disable ASF */
+ if (hw->chip_id == CHIP_ID_YUKON_EX
+ || hw->chip_id == CHIP_ID_YUKON_SUPR) {
+@@ -3298,6 +3324,13 @@ static void sky2_reset(struct sky2_hw *hw)
+ sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
+ }
+
++ #ifdef CONFIG_X86_PS4
++ if (pdev->vendor == PCI_VENDOR_ID_SONY &&
++ pdev->device == PCI_DEVICE_ID_SONY_AEOLIA_GBE) {
++ ; /* Do not perform phy resets on aeolia, it will hang */
++ } else
++ #endif
++
+ if (hw->chip_id == CHIP_ID_YUKON_OPT ||
+ hw->chip_id == CHIP_ID_YUKON_PRM ||
+ hw->chip_id == CHIP_ID_YUKON_OP_2) {
+@@ -3582,7 +3615,7 @@ static int sky2_get_link_ksettings(struct net_device *dev,
+ u32 supported, advertising;
+
+ supported = sky2_supported_modes(hw);
+- cmd->base.phy_address = PHY_ADDR_MARV;
++ cmd->base.phy_address = hw->phy_addr;
+ if (sky2_is_copper(hw)) {
+ cmd->base.port = PORT_TP;
+ cmd->base.speed = sky2->speed;
+@@ -4726,6 +4759,44 @@ static const struct net_device_ops sky2_netdev_ops[2] = {
+ },
+ };
+
++#ifdef CONFIG_X86_PS4
++/* NOTE: This region is no longer referenced by current ps4 x86 code. */
++/* However it still contains the mac address. */
++static void aeolia_get_mac_address(struct sky2_hw *hw, unsigned char *addr) {
++ u8 default_addr[ETH_ALEN] = { 0x52, 0x54, 0x00, 0xf0, 0xff, 0x0f };
++ unsigned int mem_devfn = PCI_DEVFN(PCI_SLOT(hw->pdev->devfn), AEOLIA_FUNC_ID_MEM);
++ struct pci_dev *mem_dev;
++ phys_addr_t bp_base;
++ void __iomem *bp;
++
++ memcpy(addr, default_addr, sizeof(default_addr));
++
++ mem_dev = pci_get_slot(hw->pdev->bus, mem_devfn);
++ if (!mem_dev) {
++ dev_err(&hw->pdev->dev, "sky2: could not get handle to mem device\n");
++ return;
++ }
++
++ bp_base = pci_resource_start(mem_dev, 5) + APCIE_SPM_BP_BASE;
++ if (!request_mem_region(bp_base, APCIE_SPM_BP_SIZE, "spm.bp")) {
++ dev_err(&hw->pdev->dev, "sky2: failed to request bootparam SPM region\n");
++ return;
++ }
++
++ bp = ioremap(bp_base, APCIE_SPM_BP_SIZE);
++ if (!bp) {
++ dev_err(&hw->pdev->dev, "sky2: failed to map bootparam portion of SPM\n");
++ goto release_bp;
++ }
++
++ memcpy_fromio(addr, bp, ETH_ALEN);
++
++ iounmap(bp);
++release_bp:
++ release_mem_region(bp_base, APCIE_SPM_BP_SIZE);
++}
++#endif
++
+ /* Initialize network device */
+ static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port,
+ int highmem, int wol)
+@@ -4798,26 +4869,34 @@ static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port,
+ else
+ dev->max_mtu = ETH_JUMBO_MTU;
+
+- /* try to get mac address in the following order:
+- * 1) from device tree data
+- * 2) from internal registers set by bootloader
+- */
+- ret = of_get_mac_address(hw->pdev->dev.of_node, dev->dev_addr);
+- if (ret)
+- memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8,
+- ETH_ALEN);
++ #ifdef CONFIG_X86_PS4
++ if (hw->pdev->vendor == PCI_VENDOR_ID_SONY) {
++ aeolia_get_mac_address(hw, dev->dev_addr);
++ } else
++ #endif
++ {
++ /* try to get mac address in the following order:
++ * 1) from device tree data
++ * 2) from internal registers set by bootloader
++ */
++ ret = of_get_mac_address(hw->pdev->dev.of_node, dev->dev_addr);
++ if (ret)
++ memcpy_fromio(dev->dev_addr,
++ hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
++ }
+
+ /* if the address is invalid, use a random value */
+ if (!is_valid_ether_addr(dev->dev_addr)) {
+ struct sockaddr sa = { AF_UNSPEC };
+
+- dev_warn(&hw->pdev->dev, "Invalid MAC address, defaulting to random\n");
++ dev_warn(&hw->pdev->dev,
++ "Invalid MAC address, defaulting to random\n");
+ eth_hw_addr_random(dev);
+ memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
+ if (sky2_set_mac_address(dev, &sa))
+- dev_warn(&hw->pdev->dev, "Failed to set MAC address.\n");
++ dev_warn(&hw->pdev->dev,
++ "Failed to set MAC address.\n");
+ }
+-
+ return dev;
+ }
+
+@@ -4957,6 +5036,12 @@ static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+ u32 reg;
+ char buf1[16];
+
++ #ifdef CONFIG_X86_PS4
++ /* This will return negative on non-PS4 platforms */
++ if (apcie_status() == 0)
++ return -EPROBE_DEFER;
++ #endif
++
+ err = pci_enable_device(pdev);
+ if (err) {
+ dev_err(&pdev->dev, "cannot enable PCI device\n");
+@@ -4988,6 +5073,16 @@ static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+
+ pci_set_master(pdev);
+
++ #ifdef CONFIG_X86_PS4
++ if (pdev->vendor == PCI_VENDOR_ID_SONY) {
++ if (pci_set_dma_mask(pdev, DMA_BIT_MASK(31)) < 0 ||
++ pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(31)) < 0) {
++ dev_err(&pdev->dev, "no usable DMA configuration\n");
++ goto err_out_free_regions;
++ }
++ } else
++ #endif
++
+ if (sizeof(dma_addr_t) > sizeof(u32) &&
+ !(err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)))) {
+ using_dac = 1;
+@@ -5036,6 +5131,16 @@ static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+ goto err_out_free_hw;
+ }
+
++ hw->phy_addr = PHY_ADDR_MARV;
++ #ifdef CONFIG_X86_PS4
++ if (pdev->vendor == PCI_VENDOR_ID_SONY &&
++ pdev->device == PCI_DEVICE_ID_SONY_AEOLIA_GBE) {
++ /* aeolia supports some sort of "l2 switch" */
++ /* it has normal phy at addr 1 with a possibly-active switch at addr 2 */
++ hw->phy_addr = 1;
++ }
++ #endif
++
+ err = sky2_init(hw);
+ if (err)
+ goto err_out_iounmap;
+@@ -5064,6 +5169,19 @@ static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+ if (disable_msi == -1)
+ disable_msi = !!dmi_check_system(msi_blacklist);
+
++ #ifdef CONFIG_X86_PS4
++ if (pdev->vendor == PCI_VENDOR_ID_SONY &&
++ apcie_assign_irqs(pdev, 1) > 0) {
++ err = sky2_test_msi(hw);
++ if (err) {
++ apcie_free_irqs(pdev->irq, 1);
++ /* PS4 requires MSI, so if it fails, bail out. */
++ goto err_out_free_netdev;
++ }
++ hw->flags |= SKY2_HW_USE_AEOLIA_MSI;
++ } else
++ #endif
++
+ if (!disable_msi && pci_enable_msi(pdev) == 0) {
+ err = sky2_test_msi(hw);
+ if (err) {
+@@ -5120,8 +5238,14 @@ static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+ err_out_unregister:
+ unregister_netdev(dev);
+ err_out_free_netdev:
+- if (hw->flags & SKY2_HW_USE_MSI)
+- pci_disable_msi(pdev);
++ #ifdef CONFIG_X86_PS4
++ if (hw->flags & SKY2_HW_USE_AEOLIA_MSI)
++ apcie_free_irqs(pdev->irq, 1);
++ else
++ #endif
++ if (hw->flags & SKY2_HW_USE_MSI)
++ pci_disable_msi(pdev);
++
+ free_netdev(dev);
+ err_out_free_pci:
+ dma_free_coherent(&pdev->dev,
+@@ -5168,6 +5292,12 @@ static void sky2_remove(struct pci_dev *pdev)
+ free_irq(pdev->irq, hw);
+ }
+
++ #ifdef CONFIG_X86_PS4
++ if (hw->flags & SKY2_HW_USE_AEOLIA_MSI)
++ apcie_free_irqs(pdev->irq, 1);
++ else
++ #endif
++
+ if (hw->flags & SKY2_HW_USE_MSI)
+ pci_disable_msi(pdev);
+ dma_free_coherent(&pdev->dev,
+diff --git a/drivers/net/ethernet/marvell/sky2.h b/drivers/net/ethernet/marvell/sky2.h
+index ddec1627f1a7..eeb3a5a8b029 100644
+--- a/drivers/net/ethernet/marvell/sky2.h
++++ b/drivers/net/ethernet/marvell/sky2.h
+@@ -2289,6 +2289,8 @@ struct sky2_hw {
+ #define SKY2_HW_RSS_CHKSUM 0x00000400 /* RSS requires chksum */
+ #define SKY2_HW_IRQ_SETUP 0x00000800
+
++#define SKY2_HW_USE_AEOLIA_MSI 0x00001000
++
+ u8 chip_id;
+ u8 chip_rev;
+ u8 pmd_type;
+@@ -2303,6 +2305,7 @@ struct sky2_hw {
+ struct work_struct restart_work;
+ wait_queue_head_t msi_wait;
+
++ u8 phy_addr;
+ char irq_name[];
+ };
+
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0007-feat-usb-support.patch b/device/testing/linux-sony-ps4/0007-feat-usb-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..9cf81fdd7634d3cad9fce9c8814b4c87fe10bec5
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0007-feat-usb-support.patch
@@ -0,0 +1,701 @@
+From 915809af6ee266c1c7792a0be01ae4da02d4766f Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Mon, 20 Dec 2021 16:30:44 +0100
+Subject: [PATCH 07/22] feat: usb support
+
+---
+ drivers/usb/host/Kconfig | 8 +
+ drivers/usb/host/Makefile | 1 +
+ drivers/usb/host/xhci-aeolia.c | 585 +++++++++++++++++++++++++++++++++
+ drivers/usb/host/xhci-aeolia.h | 14 +
+ drivers/usb/host/xhci.c | 30 +-
+ 5 files changed, 624 insertions(+), 14 deletions(-)
+ create mode 100644 drivers/usb/host/xhci-aeolia.c
+ create mode 100644 drivers/usb/host/xhci-aeolia.h
+
+diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
+index c4736d1d020c..92107bda6004 100644
+--- a/drivers/usb/host/Kconfig
++++ b/drivers/usb/host/Kconfig
+@@ -104,6 +104,14 @@ config USB_XHCI_TEGRA
+ Say 'Y' to enable the support for the xHCI host controller
+ found in NVIDIA Tegra124 and later SoCs.
+
++
++config USB_XHCI_AEOLIA
++ tristate "xHCI support for Sony PS4 (Aeolia)"
++ depends on X86_PS4
++ help
++ Say 'Y' to enable the support for the xHCI host controller
++ found in the Sony PlayStation 4.
++
+ endif # USB_XHCI_HCD
+
+ config USB_EHCI_BRCMSTB
+diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
+index 171de4df50bd..d0365fbf8b45 100644
+--- a/drivers/usb/host/Makefile
++++ b/drivers/usb/host/Makefile
+@@ -73,6 +73,7 @@ obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
+ obj-$(CONFIG_USB_XHCI_HISTB) += xhci-histb.o
+ obj-$(CONFIG_USB_XHCI_MTK) += xhci-mtk-hcd.o
+ obj-$(CONFIG_USB_XHCI_TEGRA) += xhci-tegra.o
++obj-$(CONFIG_USB_XHCI_AEOLIA) += xhci-aeolia.o
+ obj-$(CONFIG_USB_SL811_HCD) += sl811-hcd.o
+ obj-$(CONFIG_USB_SL811_CS) += sl811_cs.o
+ obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o
+diff --git a/drivers/usb/host/xhci-aeolia.c b/drivers/usb/host/xhci-aeolia.c
+new file mode 100644
+index 000000000000..a9b345284495
+--- /dev/null
++++ b/drivers/usb/host/xhci-aeolia.c
+@@ -0,0 +1,585 @@
++/*
++ * xhci-aeoliat.c - xHCI host controller driver for Aeolia (Sony PS4)
++ *
++ * Borrows code from xhci-pci.c, hcd-pci.c, and xhci-plat.c.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ */
++
++#include <linux/pci.h>
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/acpi.h>
++#include <asm/ps4.h>
++#include "xhci-aeolia.h"
++#include "../../ps4/aeolia.h"
++
++#include "xhci.h"
++
++static const char hcd_name[] = "xhci_aeolia";
++
++static struct hc_driver __read_mostly xhci_aeolia_hc_driver;
++
++#define NR_DEVICES 3
++
++struct aeolia_xhci {
++ // TODO (ps4patches): Belize, enable in ahci commit
++ // struct ata_host *host;
++ int nr_irqs;
++ struct usb_hcd *hcd[NR_DEVICES];
++};
++
++static int xhci_aeolia_setup(struct usb_hcd *hcd);
++
++static const struct xhci_driver_overrides xhci_aeolia_overrides __initconst = {
++ .extra_priv_size = sizeof(struct xhci_hcd),
++ .reset = xhci_aeolia_setup,
++};
++
++static void xhci_aeolia_quirks(struct device *dev, struct xhci_hcd *xhci)
++{
++ /*
++ * Do not try to enable MSIs, we provide the MSIs ourselves
++ * Do not touch DMA mask, we need a custom one
++ */
++ xhci->quirks |= XHCI_PLAT | XHCI_PLAT_DMA;
++}
++
++/* called during probe() after chip reset completes */
++static int xhci_aeolia_setup(struct usb_hcd *hcd)
++{
++ return xhci_gen_setup(hcd, xhci_aeolia_quirks);
++}
++
++static int xhci_aeolia_probe_one(struct pci_dev *dev, int index)
++{
++ int retval;
++ struct aeolia_xhci *axhci = pci_get_drvdata(dev);
++ struct hc_driver *driver = &xhci_aeolia_hc_driver;
++ struct usb_hcd *hcd;
++ struct xhci_hcd *xhci;
++ int irq = (axhci->nr_irqs > 1) ? (dev->irq + index) : dev->irq;
++
++ // ok...adding this printk appears to have introduced a delay that fixed
++ // bringup of the middle host controller, so w/e for now...
++
++ printk("xhci_aeolia_probe_one %d, controller is %x\n", index, dev->device);
++
++ hcd = usb_create_hcd(driver, &dev->dev, pci_name(dev));
++ pci_set_drvdata(dev, axhci); /* usb_create_hcd clobbers this */
++ if (!hcd)
++ return -ENOMEM;
++
++ hcd->rsrc_start = pci_resource_start(dev, 2 * index);
++ hcd->rsrc_len = pci_resource_len(dev, 2 * index);
++
++ /*
++ * TODO (ps4patches): Belize, enable in ahci commit
++ if (!devm_request_mem_region(&dev->dev, hcd->rsrc_start, hcd->rsrc_len,
++ driver->description)) {
++ */
++
++ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
++ driver->description)) {
++ dev_dbg(&dev->dev, "controller already in use\n");
++ retval = -EBUSY;
++ goto put_hcd;
++ }
++ hcd->regs = pci_ioremap_bar(dev, 2 * index);
++ if (hcd->regs == NULL) {
++ dev_dbg(&dev->dev, "error mapping memory\n");
++ retval = -EFAULT;
++ goto release_mem_region;
++ }
++
++ device_wakeup_enable(hcd->self.controller);
++
++ xhci = hcd_to_xhci(hcd);
++ xhci->main_hcd = hcd;
++ xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
++ pci_name(dev), hcd);
++ if (!xhci->shared_hcd) {
++ retval = -ENOMEM;
++ goto unmap_registers;
++ }
++
++ retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
++ if (retval)
++ goto put_usb3_hcd;
++
++ retval = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
++ if (retval)
++ goto dealloc_usb2_hcd;
++
++ axhci->hcd[index] = hcd;
++
++ return 0;
++
++dealloc_usb2_hcd:
++ usb_remove_hcd(hcd);
++put_usb3_hcd:
++ usb_put_hcd(xhci->shared_hcd);
++unmap_registers:
++ iounmap(hcd->regs);
++release_mem_region:
++ //
++ // devm_release_mem_region(&dev->dev, hcd->rsrc_start, hcd->rsrc_len);
++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
++put_hcd:
++ usb_put_hcd(hcd);
++ dev_err(&dev->dev, "init %s(%d) fail, %d\n",
++ pci_name(dev), index, retval);
++ return retval;
++}
++
++static void xhci_aeolia_remove_one(struct pci_dev *dev, int index)
++{
++ struct aeolia_xhci *axhci = pci_get_drvdata(dev);
++ struct usb_hcd *hcd = axhci->hcd[index];
++ struct xhci_hcd *xhci;
++
++ if (!hcd)
++ return;
++ xhci = hcd_to_xhci(hcd);
++
++ usb_remove_hcd(xhci->shared_hcd);
++ usb_remove_hcd(hcd);
++ usb_put_hcd(xhci->shared_hcd);
++ iounmap(hcd->regs);
++ usb_put_hcd(hcd);
++ axhci->hcd[index] = NULL;
++}
++
++// TODO (ps4patches): Belize, enable in ahci commit
++//#define DRV_VERSION "3.0"
++//#define DRV_NAME "ahci"
++//static const struct ata_port_info ahci_port_info = {
++// .flags = AHCI_FLAG_COMMON,
++// .pio_mask = ATA_PIO4,
++// .udma_mask = ATA_UDMA6,
++// .port_ops = &ahci_ops,
++//};
++//
++//static struct scsi_host_template ahci_sht = {
++// AHCI_SHT(DRV_NAME),
++//};
++//
++//static bool bus_master;
++//static int ahci_init_one(struct pci_dev *pdev)
++//{
++// struct f_resource* r_mem;
++// struct ahci_controller* ctlr;
++// struct aeolia_xhci *axhci = pci_get_drvdata(pdev);
++// struct ata_port_info pi = ahci_port_info;
++// const struct ata_port_info *ppi[] = { &pi, NULL };
++// struct ahci_host_priv *hpriv;
++// struct ata_host *host;
++// int n_ports, i, rc;
++// int ahci_pci_bar = 2;
++// resource_size_t rsrc_start;
++// resource_size_t rsrc_len;
++//
++// VPRINTK("ENTER\n");
++//
++// WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
++//
++// ata_print_version_once(&pdev->dev, DRV_VERSION);
++//
++// /*
++// rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
++// if (rc == -EBUSY)
++// pcim_pin_device(pdev);
++// if (rc)
++// return rc;
++// */
++//
++// hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
++// //hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
++// if (!hpriv)
++// return -ENOMEM;
++// hpriv->flags |= (unsigned long)pi.private_data;
++//
++// //hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
++// rsrc_start = pci_resource_start(pdev, ahci_pci_bar);
++// rsrc_len = pci_resource_len(pdev, ahci_pci_bar);
++// //if (!request_mem_region(rsrc_start, rsrc_len, "xhci-ahci.mem")) {
++// if (!devm_request_mem_region(&pdev->dev, rsrc_start, rsrc_len, "xhci-ahci.mem")) {
++// dev_dbg(&pdev->dev, "controller already in use\n");
++// rc = -EBUSY;
++// goto put_hpriv;
++// }
++//
++//
++// hpriv->mmio = pci_ioremap_bar(pdev, ahci_pci_bar);
++// if (hpriv->mmio == NULL) {
++// dev_dbg(&pdev->dev, "error mapping memory\n");
++// rc = -EFAULT;
++// goto release_mem_region;
++// }
++//
++// r_mem = kzalloc(sizeof(*r_mem), GFP_KERNEL);
++// if (r_mem) {
++// r_mem->r_bustag = 1;//mem
++// r_mem->r_bushandle = hpriv->mmio;
++//
++// ctlr = kzalloc(sizeof(*ctlr), GFP_KERNEL);
++// if (ctlr) {
++// ctlr->r_mem = r_mem;
++// ctlr->dev_id = 0; //or 0x90ca104d;
++// ctlr->trace_len = 6;
++// bpcie_sata_phy_init(&pdev->dev, ctlr);
++// kfree(ctlr);
++// }
++// kfree(r_mem);
++// }
++// device_wakeup_enable(&pdev->dev);
++//
++// /* save initial config */
++// ahci_save_initial_config(&pdev->dev, hpriv);
++//
++// /* prepare host */
++// if (hpriv->cap & HOST_CAP_NCQ) {
++// pi.flags |= ATA_FLAG_NCQ;
++// /*
++// * Auto-activate optimization is supposed to be
++// * supported on all AHCI controllers indicating NCQ
++// * capability, but it seems to be broken on some
++// * chipsets including NVIDIAs.
++// */
++// if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
++// pi.flags |= ATA_FLAG_FPDMA_AA;
++//
++// /*
++// * All AHCI controllers should be forward-compatible
++// * with the new auxiliary field. This code should be
++// * conditionalized if any buggy AHCI controllers are
++// * encountered.
++// */
++// pi.flags |= ATA_FLAG_FPDMA_AUX;
++// }
++//
++// if (hpriv->cap & HOST_CAP_PMP)
++// pi.flags |= ATA_FLAG_PMP;
++//
++// ahci_set_em_messages(hpriv, &pi);
++//
++// /* CAP.NP sometimes indicate the index of the last enabled
++// * port, at other times, that of the last possible port, so
++// * determining the maximum port number requires looking at
++// * both CAP.NP and port_map.
++// */
++// n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
++//
++// host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
++// if (!host) {
++// rc = -ENOMEM;
++// goto unmap_registers;
++// }
++// axhci->host = host;
++// pci_set_drvdata(pdev, axhci);
++//
++// host->private_data = hpriv;
++//
++// {
++// int index = 1;
++// int irq = (axhci->nr_irqs > 1) ? (pdev->irq + index) : pdev->irq;
++// hpriv->irq = irq;
++// }
++//
++// if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
++// host->flags |= ATA_HOST_PARALLEL_SCAN;
++// else
++// dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
++//
++// if (pi.flags & ATA_FLAG_EM)
++// ahci_reset_em(host);
++//
++// for (i = 0; i < host->n_ports; i++) {
++// struct ata_port *ap = host->ports[i];
++//
++// ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
++// ata_port_pbar_desc(ap, ahci_pci_bar,
++// 0x100 + ap->port_no * 0x80, "port");
++//
++// /* set enclosure management message type */
++// if (ap->flags & ATA_FLAG_EM)
++// ap->em_message_type = hpriv->em_msg_type;
++//
++//
++// /* disabled/not-implemented port */
++// if (!(hpriv->port_map & (1 << i)))
++// ap->ops = &ata_dummy_port_ops;
++// }
++//
++// rc = ahci_reset_controller(host);
++// dev_dbg(&pdev->dev, "ahci_reset_controller returned %d\n", rc);
++// if (rc)
++// goto release_host;
++//
++// ahci_init_controller(host);
++// ahci_print_info(host, "ATA");
++//
++// if (!bus_master) {
++// pci_set_master(pdev);
++// bus_master = true;
++// }
++//
++// rc = ahci_host_activate(host, &ahci_sht);
++// dev_dbg(&pdev->dev, "ahci_host_activate returned %d\n", rc);
++// if (rc) {
++// goto host_deactivate;
++// }
++//
++// pm_runtime_put_noidle(&pdev->dev);
++// return 0;
++//
++// host_deactivate:
++// release_host:
++// unmap_registers:
++// iounmap(hpriv->mmio);
++// release_mem_region:
++//
++// release_mem_region(rsrc_start, rsrc_len);
++//
++// // TODO (ps4patches): Belize, enable in ahci commit
++// //devm_release_mem_region(&pdev->dev, rsrc_start, rsrc_len);
++// put_hpriv:
++// //kfree(hpriv);
++// devm_kfree(&pdev->dev, hpriv);
++// dev_err(&pdev->dev, "init %s fail, %d\n",
++// pci_name(pdev), rc);
++// return rc;
++//}
++//
++//static void ahci_remove_one(struct pci_dev *pdev)
++//{
++// pm_runtime_get_noresume(&pdev->dev);
++//
++// struct aeolia_xhci *axhci = pci_get_drvdata(pdev);
++// if (axhci && axhci->host) {
++// ata_host_detach(axhci->host);
++// struct ahci_host_priv *hpriv = axhci->host->private_data;
++// if (hpriv) {
++// iounmap(hpriv->mmio);
++// }
++// axhci->host = NULL;
++// }
++//}
++
++static int xhci_aeolia_probe(struct pci_dev *dev, const struct pci_device_id *id)
++{
++ int idx;
++ int retval;
++ struct aeolia_xhci *axhci;
++
++ if (apcie_status() == 0)
++ return -EPROBE_DEFER;
++
++ if (pci_enable_device(dev) < 0)
++ return -ENODEV;
++
++ axhci = kzalloc(sizeof(*axhci), GFP_KERNEL);
++ // TODO (ps4patches): Belize, enable in ahci commit
++ // axhci = devm_kzalloc(&dev->dev, sizeof(*axhci), GFP_KERNEL);
++ if (!axhci) {
++ retval = -ENOMEM;
++ goto disable_device;
++ }
++ pci_set_drvdata(dev, axhci);
++
++ axhci->nr_irqs = retval = apcie_assign_irqs(dev, NR_DEVICES);
++ if (retval < 0) {
++ goto free_axhci;
++ }
++
++ // TODO (ps4patches): Belize, disable in ahci commit
++ pci_set_master(dev);
++
++ if (pci_set_dma_mask(dev, DMA_BIT_MASK(31)) ||
++ pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(31))) {
++ return -ENODEV;
++ }
++
++ // TODO (ps4patches): Belize, enable in ahci commit
++// retval = ahci_init_one(dev);
++// dev_dbg(&dev->dev, "ahci_init_one returned %d", retval);
++// if (!bus_master) {
++// pci_set_master(dev);
++// bus_master = true;
++// }
++
++ for (idx = 0; idx < NR_DEVICES; idx++) {
++ if(dev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI && idx == 1){ //this is for Belize and Baikal
++ continue;
++ }
++ retval = xhci_aeolia_probe_one(dev, idx);
++ if (retval)
++ goto remove_hcds;
++ }
++
++ return 0;
++
++remove_hcds:
++ while (idx--)
++ xhci_aeolia_remove_one(dev, idx);
++ apcie_free_irqs(dev->irq, axhci->nr_irqs);
++free_axhci:
++ kfree(axhci);
++
++ // TODO (ps4patches): Belize, disable in ahci commit
++ // devm_kfree(&dev->dev, axhci);
++ // pci_set_drvdata(dev, NULL);
++disable_device:
++ pci_disable_device(dev);
++ return retval;
++}
++
++static void xhci_aeolia_remove(struct pci_dev *dev)
++{
++ int idx;
++ struct aeolia_xhci *axhci = pci_get_drvdata(dev);
++ if (!axhci)
++ return;
++
++ for (idx = 0; idx < NR_DEVICES; idx++) {
++ if(dev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI) {
++ if(idx != 1)
++ xhci_aeolia_remove_one(dev, idx);
++ // TODO (ps4patches): Belize, enable in ahci commit
++ // else
++ // ahci_remove_one(dev);
++ }
++ else
++ xhci_aeolia_remove_one(dev, idx);
++ }
++
++ apcie_free_irqs(dev->irq, axhci->nr_irqs);
++
++ // TODO (ps4patches): Belize, remove in ahci commit
++ kfree(axhci);
++
++ pci_disable_device(dev);
++}
++
++// TODO (ps4patches): Belize, enable in ahci commit
++//static void xhci_hcd_pci_shutdown(struct pci_dev *dev){
++// struct aeolia_xhci *axhci;
++// struct usb_hcd *hcd;
++// int idx;
++//
++// axhci = pci_get_drvdata(dev);
++// if (!axhci)
++// return;
++//
++// for (idx = 0; idx < NR_DEVICES; idx++) {
++// if(dev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI) {
++// if(idx != 1) {
++// hcd = axhci->hcd[idx];
++// if (hcd) {
++// if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) && hcd->driver->shutdown) {
++// hcd->driver->shutdown(hcd);
++// if (usb_hcd_is_primary_hcd(hcd) && hcd->irq > 0)
++// free_irq(hcd->irq, hcd);
++// }
++// }
++// }
++// }
++// }
++//}
++
++
++static const struct pci_device_id pci_ids[] = {
++ { PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_AEOLIA_XHCI) },
++ { PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_BELIZE_XHCI) },
++ { PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_BAIKAL_XHCI) },
++ { /* end: all zeroes */ }
++};
++MODULE_DEVICE_TABLE(pci, pci_ids);
++
++#ifdef CONFIG_PM_SLEEP
++static int xhci_aeolia_suspend(struct device *dev)
++{
++ int idx;
++ struct aeolia_xhci *axhci = dev_get_drvdata(dev);
++ struct xhci_hcd *xhci;
++ int retval;
++ struct pci_dev *pdev = to_pci_dev(dev);
++
++ for (idx = 0; idx < NR_DEVICES; idx++) {
++ if(pdev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI && idx == 1)
++ continue;
++ xhci = hcd_to_xhci(axhci->hcd[idx]);
++ retval = xhci_suspend(xhci, device_may_wakeup(dev));
++ if (retval < 0)
++ goto resume;
++ }
++ return 0;
++
++resume:
++ while (idx--) {
++ xhci = hcd_to_xhci(axhci->hcd[idx]);
++ xhci_resume(xhci, 0);
++ }
++ return retval;
++}
++
++static int xhci_aeolia_resume(struct device *dev)
++{
++ int idx;
++ struct aeolia_xhci *axhci = dev_get_drvdata(dev);
++ struct xhci_hcd *xhci;
++ int retval;
++ struct pci_dev *pdev = to_pci_dev(dev);
++
++ for (idx = 0; idx < NR_DEVICES; idx++) {
++ if(pdev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI && idx == 1)
++ continue;
++ xhci = hcd_to_xhci(axhci->hcd[idx]);
++ retval = xhci_resume(xhci, 0);
++ if (retval < 0)
++ return retval;
++ }
++ return 0;
++}
++
++static const struct dev_pm_ops xhci_aeolia_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(xhci_aeolia_suspend, xhci_aeolia_resume)
++};
++#endif
++
++/* pci driver glue; this is a "new style" PCI driver module */
++static struct pci_driver xhci_aeolia_driver = {
++ .name = "xhci_aeolia",
++ .id_table = pci_ids,
++
++ .probe = xhci_aeolia_probe,
++ .remove = xhci_aeolia_remove,
++ /* suspend and resume implemented later */
++
++ .shutdown = usb_hcd_pci_shutdown,
++ // TODO (ps4patches): Belize, enable in ahci commit
++ //.shutdown = xhci_hcd_pci_shutdown,
++#ifdef CONFIG_PM_SLEEP
++ .driver = {
++ .pm = &xhci_aeolia_pm_ops
++ },
++#endif
++};
++
++static int __init xhci_aeolia_init(void)
++{
++ xhci_init_driver(&xhci_aeolia_hc_driver, &xhci_aeolia_overrides);
++ return pci_register_driver(&xhci_aeolia_driver);
++}
++module_init(xhci_aeolia_init);
++
++static void __exit xhci_aeolia_exit(void)
++{
++ pci_unregister_driver(&xhci_aeolia_driver);
++}
++module_exit(xhci_aeolia_exit);
++
++MODULE_DESCRIPTION("xHCI Aeolia Host Controller Driver");
++MODULE_LICENSE("GPL");
+diff --git a/drivers/usb/host/xhci-aeolia.h b/drivers/usb/host/xhci-aeolia.h
+new file mode 100644
+index 000000000000..2b711d6a92ca
+--- /dev/null
++++ b/drivers/usb/host/xhci-aeolia.h
+@@ -0,0 +1,14 @@
++/*
++ * xhci-aeolia.h
++ *
++ * Created on: 31 Oct 2019
++ * Author: visicva
++ */
++
++#ifndef DRIVERS_USB_HOST_XHCI_AEOLIA_H_
++#define DRIVERS_USB_HOST_XHCI_AEOLIA_H_
++
++#include "../../ata/ahci.h"
++#include <linux/irqdomain.h>
++
++#endif /* DRIVERS_USB_HOST_XHCI_AEOLIA_H_ */
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 1fd2f6a850eb..1c8fb48c7095 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -5373,20 +5373,22 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
+
+ /* Set dma_mask and coherent_dma_mask to 64-bits,
+ * if xHC supports 64-bit addressing */
+- if (HCC_64BIT_ADDR(xhci->hcc_params) &&
+- !dma_set_mask(dev, DMA_BIT_MASK(64))) {
+- xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
+- dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
+- } else {
+- /*
+- * This is to avoid error in cases where a 32-bit USB
+- * controller is used on a 64-bit capable system.
+- */
+- retval = dma_set_mask(dev, DMA_BIT_MASK(32));
+- if (retval)
+- return retval;
+- xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
+- dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
++ if (!(xhci->quirks & XHCI_PLAT_DMA)) {
++ if (HCC_64BIT_ADDR(xhci->hcc_params) &&
++ !dma_set_mask(dev, DMA_BIT_MASK(64))) {
++ xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
++ dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
++ } else {
++ /*
++ * This is to avoid error in cases where a 32-bit USB
++ * controller is used on a 64-bit capable system.
++ */
++ retval = dma_set_mask(dev, DMA_BIT_MASK(32));
++ if (retval)
++ return retval;
++ xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
++ dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
++ }
+ }
+
+ xhci_dbg(xhci, "Calling HCD init\n");
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0008-feat-configuration.patch b/device/testing/linux-sony-ps4/0008-feat-configuration.patch
new file mode 100644
index 0000000000000000000000000000000000000000..dea35e50333c5eda838b7c84a6d7e7f06fb1db49
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0008-feat-configuration.patch
@@ -0,0 +1,4008 @@
+From 67261e0acdbe92d67028fcae441a6284c90c0248 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Mon, 20 Dec 2021 16:54:18 +0100
+Subject: [PATCH 08/22] feat: configuration
+
+---
+ config | 3989 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 3989 insertions(+)
+ create mode 100644 config
+
+diff --git a/config b/config
+new file mode 100644
+index 000000000000..9b3e8c78ecf1
+--- /dev/null
++++ b/config
+@@ -0,0 +1,3989 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# Linux/x86 5.15.10 Kernel Configuration
++#
++CONFIG_CC_VERSION_TEXT="gcc (GCC) 11.1.0"
++CONFIG_CC_IS_GCC=y
++CONFIG_GCC_VERSION=110100
++CONFIG_CLANG_VERSION=0
++CONFIG_AS_IS_GNU=y
++CONFIG_AS_VERSION=23601
++CONFIG_LD_IS_BFD=y
++CONFIG_LD_VERSION=23601
++CONFIG_LLD_VERSION=0
++CONFIG_CC_CAN_LINK=y
++CONFIG_CC_CAN_LINK_STATIC=y
++CONFIG_CC_HAS_ASM_GOTO=y
++CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
++CONFIG_CC_HAS_ASM_INLINE=y
++CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
++CONFIG_IRQ_WORK=y
++CONFIG_BUILDTIME_TABLE_SORT=y
++CONFIG_THREAD_INFO_IN_TASK=y
++
++#
++# General setup
++#
++CONFIG_INIT_ENV_ARG_LIMIT=32
++# CONFIG_COMPILE_TEST is not set
++# CONFIG_WERROR is not set
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_BUILD_SALT=""
++CONFIG_HAVE_KERNEL_GZIP=y
++CONFIG_HAVE_KERNEL_BZIP2=y
++CONFIG_HAVE_KERNEL_LZMA=y
++CONFIG_HAVE_KERNEL_XZ=y
++CONFIG_HAVE_KERNEL_LZO=y
++CONFIG_HAVE_KERNEL_LZ4=y
++CONFIG_HAVE_KERNEL_ZSTD=y
++# CONFIG_KERNEL_GZIP is not set
++# CONFIG_KERNEL_BZIP2 is not set
++# CONFIG_KERNEL_LZMA is not set
++CONFIG_KERNEL_XZ=y
++# CONFIG_KERNEL_LZO is not set
++# CONFIG_KERNEL_LZ4 is not set
++# CONFIG_KERNEL_ZSTD is not set
++CONFIG_DEFAULT_INIT=""
++CONFIG_DEFAULT_HOSTNAME="ps4"
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++CONFIG_SYSVIPC_SYSCTL=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_POSIX_MQUEUE_SYSCTL=y
++# CONFIG_WATCH_QUEUE is not set
++CONFIG_CROSS_MEMORY_ATTACH=y
++CONFIG_USELIB=y
++CONFIG_AUDIT=y
++CONFIG_HAVE_ARCH_AUDITSYSCALL=y
++CONFIG_AUDITSYSCALL=y
++
++#
++# IRQ subsystem
++#
++CONFIG_GENERIC_IRQ_PROBE=y
++CONFIG_GENERIC_IRQ_SHOW=y
++CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
++CONFIG_GENERIC_PENDING_IRQ=y
++CONFIG_GENERIC_IRQ_MIGRATION=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_IRQ_DOMAIN=y
++CONFIG_IRQ_DOMAIN_HIERARCHY=y
++CONFIG_GENERIC_MSI_IRQ=y
++CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
++CONFIG_IRQ_MSI_IOMMU=y
++CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
++CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
++CONFIG_IRQ_FORCED_THREADING=y
++CONFIG_SPARSE_IRQ=y
++# CONFIG_GENERIC_IRQ_DEBUGFS is not set
++# end of IRQ subsystem
++
++CONFIG_CLOCKSOURCE_WATCHDOG=y
++CONFIG_ARCH_CLOCKSOURCE_INIT=y
++CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
++CONFIG_GENERIC_TIME_VSYSCALL=y
++CONFIG_GENERIC_CLOCKEVENTS=y
++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
++CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
++CONFIG_GENERIC_CMOS_UPDATE=y
++CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
++CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
++
++#
++# Timers subsystem
++#
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ_COMMON=y
++# CONFIG_HZ_PERIODIC is not set
++CONFIG_NO_HZ_IDLE=y
++# CONFIG_NO_HZ_FULL is not set
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++# end of Timers subsystem
++
++CONFIG_BPF=y
++CONFIG_HAVE_EBPF_JIT=y
++CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
++
++#
++# BPF subsystem
++#
++# CONFIG_BPF_SYSCALL is not set
++# CONFIG_BPF_JIT is not set
++# end of BPF subsystem
++
++# CONFIG_PREEMPT_NONE is not set
++CONFIG_PREEMPT_VOLUNTARY=y
++# CONFIG_PREEMPT is not set
++# CONFIG_SCHED_CORE is not set
++
++#
++# CPU/Task time and stats accounting
++#
++CONFIG_TICK_CPU_ACCOUNTING=y
++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
++# CONFIG_IRQ_TIME_ACCOUNTING is not set
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++# CONFIG_PSI is not set
++# end of CPU/Task time and stats accounting
++
++# CONFIG_CPU_ISOLATION is not set
++
++#
++# RCU Subsystem
++#
++CONFIG_TREE_RCU=y
++# CONFIG_RCU_EXPERT is not set
++CONFIG_SRCU=y
++CONFIG_TREE_SRCU=y
++CONFIG_RCU_STALL_COMMON=y
++CONFIG_RCU_NEED_SEGCBLIST=y
++# end of RCU Subsystem
++
++CONFIG_BUILD_BIN2C=y
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++# CONFIG_IKHEADERS is not set
++CONFIG_LOG_BUF_SHIFT=16
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=16
++CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
++# CONFIG_PRINTK_INDEX is not set
++CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
++
++#
++# Scheduler features
++#
++# end of Scheduler features
++
++CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
++CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
++CONFIG_CC_HAS_INT128=y
++CONFIG_ARCH_SUPPORTS_INT128=y
++# CONFIG_NUMA_BALANCING is not set
++CONFIG_CGROUPS=y
++CONFIG_PAGE_COUNTER=y
++CONFIG_MEMCG=y
++CONFIG_MEMCG_SWAP=y
++CONFIG_MEMCG_KMEM=y
++CONFIG_BLK_CGROUP=y
++CONFIG_CGROUP_WRITEBACK=y
++CONFIG_CGROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++# CONFIG_CFS_BANDWIDTH is not set
++CONFIG_RT_GROUP_SCHED=y
++# CONFIG_CGROUP_PIDS is not set
++# CONFIG_CGROUP_RDMA is not set
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CGROUP_HUGETLB=y
++# CONFIG_CPUSETS is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++# CONFIG_CGROUP_PERF is not set
++# CONFIG_CGROUP_MISC is not set
++# CONFIG_CGROUP_DEBUG is not set
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_TIME_NS=y
++CONFIG_IPC_NS=y
++CONFIG_USER_NS=y
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++# CONFIG_CHECKPOINT_RESTORE is not set
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_RELAY is not set
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_RD_GZIP=y
++CONFIG_RD_BZIP2=y
++CONFIG_RD_LZMA=y
++CONFIG_RD_XZ=y
++CONFIG_RD_LZO=y
++CONFIG_RD_LZ4=y
++# CONFIG_RD_ZSTD is not set
++# CONFIG_BOOT_CONFIG is not set
++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++CONFIG_LD_ORPHAN_WARN=y
++CONFIG_SYSCTL=y
++CONFIG_HAVE_UID16=y
++CONFIG_SYSCTL_EXCEPTION_TRACE=y
++CONFIG_HAVE_PCSPKR_PLATFORM=y
++CONFIG_EXPERT=y
++CONFIG_UID16=y
++CONFIG_MULTIUSER=y
++CONFIG_SGETMASK_SYSCALL=y
++CONFIG_SYSFS_SYSCALL=y
++CONFIG_FHANDLE=y
++CONFIG_POSIX_TIMERS=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
++# CONFIG_PCSPKR_PLATFORM is not set
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_FUTEX_PI=y
++CONFIG_EPOLL=y
++CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
++CONFIG_EVENTFD=y
++CONFIG_SHMEM=y
++CONFIG_AIO=y
++# CONFIG_IO_URING is not set
++CONFIG_ADVISE_SYSCALLS=y
++CONFIG_MEMBARRIER=y
++# CONFIG_KALLSYMS is not set
++# CONFIG_USERFAULTFD is not set
++CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
++CONFIG_KCMP=y
++# CONFIG_RSEQ is not set
++# CONFIG_EMBEDDED is not set
++CONFIG_HAVE_PERF_EVENTS=y
++# CONFIG_PC104 is not set
++
++#
++# Kernel Performance Events And Counters
++#
++CONFIG_PERF_EVENTS=y
++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
++# end of Kernel Performance Events And Counters
++
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_SLUB_DEBUG=y
++CONFIG_COMPAT_BRK=y
++# CONFIG_SLAB is not set
++CONFIG_SLUB=y
++# CONFIG_SLOB is not set
++CONFIG_SLAB_MERGE_DEFAULT=y
++# CONFIG_SLAB_FREELIST_RANDOM is not set
++# CONFIG_SLAB_FREELIST_HARDENED is not set
++# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
++# CONFIG_SLUB_CPU_PARTIAL is not set
++CONFIG_SYSTEM_DATA_VERIFICATION=y
++# CONFIG_PROFILING is not set
++# end of General setup
++
++CONFIG_64BIT=y
++CONFIG_X86_64=y
++CONFIG_X86=y
++CONFIG_INSTRUCTION_DECODER=y
++CONFIG_OUTPUT_FORMAT="elf64-x86-64"
++CONFIG_LOCKDEP_SUPPORT=y
++CONFIG_STACKTRACE_SUPPORT=y
++CONFIG_MMU=y
++CONFIG_ARCH_MMAP_RND_BITS_MIN=28
++CONFIG_ARCH_MMAP_RND_BITS_MAX=32
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
++CONFIG_GENERIC_ISA_DMA=y
++CONFIG_GENERIC_BUG=y
++CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
++CONFIG_ARCH_MAY_HAVE_PC_FDC=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_ARCH_HAS_CPU_RELAX=y
++CONFIG_ARCH_HAS_FILTER_PGPROT=y
++CONFIG_HAVE_SETUP_PER_CPU_AREA=y
++CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
++CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
++CONFIG_ARCH_HIBERNATION_POSSIBLE=y
++CONFIG_ARCH_NR_GPIO=1024
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
++CONFIG_AUDIT_ARCH=y
++CONFIG_X86_64_SMP=y
++CONFIG_ARCH_SUPPORTS_UPROBES=y
++CONFIG_FIX_EARLYCON_MEM=y
++CONFIG_PGTABLE_LEVELS=4
++CONFIG_CC_HAS_SANE_STACKPROTECTOR=y
++
++#
++# Processor type and features
++#
++CONFIG_SMP=y
++CONFIG_X86_FEATURE_NAMES=y
++CONFIG_X86_X2APIC=y
++CONFIG_X86_MPPARSE=y
++# CONFIG_GOLDFISH is not set
++# CONFIG_RETPOLINE is not set
++# CONFIG_X86_CPU_RESCTRL is not set
++CONFIG_X86_EXTENDED_PLATFORM=y
++# CONFIG_X86_NUMACHIP is not set
++CONFIG_X86_PS4=y
++# CONFIG_X86_VSMP is not set
++# CONFIG_X86_GOLDFISH is not set
++# CONFIG_X86_INTEL_LPSS is not set
++# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
++CONFIG_IOSF_MBI=y
++# CONFIG_IOSF_MBI_DEBUG is not set
++CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
++CONFIG_SCHED_OMIT_FRAME_POINTER=y
++# CONFIG_HYPERVISOR_GUEST is not set
++CONFIG_MK8=y
++# CONFIG_MPSC is not set
++# CONFIG_MCORE2 is not set
++# CONFIG_MATOM is not set
++# CONFIG_GENERIC_CPU is not set
++CONFIG_X86_INTERNODE_CACHE_SHIFT=6
++CONFIG_X86_L1_CACHE_SHIFT=6
++CONFIG_X86_INTEL_USERCOPY=y
++CONFIG_X86_USE_PPRO_CHECKSUM=y
++CONFIG_X86_TSC=y
++CONFIG_X86_CMPXCHG64=y
++CONFIG_X86_CMOV=y
++CONFIG_X86_MINIMUM_CPU_FAMILY=64
++CONFIG_X86_DEBUGCTLMSR=y
++CONFIG_PROCESSOR_SELECT=y
++# CONFIG_CPU_SUP_INTEL is not set
++CONFIG_CPU_SUP_AMD=y
++# CONFIG_CPU_SUP_HYGON is not set
++# CONFIG_CPU_SUP_CENTAUR is not set
++# CONFIG_CPU_SUP_ZHAOXIN is not set
++CONFIG_HPET_TIMER=y
++CONFIG_DMI=y
++CONFIG_GART_IOMMU=y
++# CONFIG_MAXSMP is not set
++CONFIG_NR_CPUS_RANGE_BEGIN=2
++CONFIG_NR_CPUS_RANGE_END=512
++CONFIG_NR_CPUS_DEFAULT=64
++CONFIG_NR_CPUS=8
++CONFIG_SCHED_SMT=y
++CONFIG_SCHED_MC=y
++CONFIG_X86_LOCAL_APIC=y
++CONFIG_X86_IO_APIC=y
++# CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set
++CONFIG_X86_MCE=y
++# CONFIG_X86_MCELOG_LEGACY is not set
++# CONFIG_X86_MCE_INTEL is not set
++CONFIG_X86_MCE_AMD=y
++CONFIG_X86_MCE_THRESHOLD=y
++# CONFIG_X86_MCE_INJECT is not set
++
++#
++# Performance monitoring
++#
++# CONFIG_PERF_EVENTS_INTEL_RAPL is not set
++# CONFIG_PERF_EVENTS_AMD_POWER is not set
++# CONFIG_PERF_EVENTS_AMD_UNCORE is not set
++# end of Performance monitoring
++
++CONFIG_X86_VSYSCALL_EMULATION=y
++CONFIG_X86_IOPL_IOPERM=y
++# CONFIG_I8K is not set
++CONFIG_MICROCODE=y
++# CONFIG_MICROCODE_INTEL is not set
++CONFIG_MICROCODE_AMD=y
++CONFIG_MICROCODE_OLD_INTERFACE=y
++CONFIG_X86_MSR=y
++CONFIG_X86_CPUID=y
++# CONFIG_X86_5LEVEL is not set
++CONFIG_X86_DIRECT_GBPAGES=y
++# CONFIG_X86_CPA_STATISTICS is not set
++# CONFIG_AMD_MEM_ENCRYPT is not set
++CONFIG_NUMA=y
++CONFIG_AMD_NUMA=y
++CONFIG_X86_64_ACPI_NUMA=y
++# CONFIG_NUMA_EMU is not set
++CONFIG_NODES_SHIFT=6
++CONFIG_ARCH_SPARSEMEM_ENABLE=y
++CONFIG_ARCH_SPARSEMEM_DEFAULT=y
++CONFIG_ARCH_SELECT_MEMORY_MODEL=y
++CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
++# CONFIG_X86_PMEM_LEGACY is not set
++# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set
++CONFIG_MTRR=y
++CONFIG_MTRR_SANITIZER=y
++CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0
++CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
++CONFIG_X86_PAT=y
++CONFIG_ARCH_USES_PG_UNCACHED=y
++CONFIG_ARCH_RANDOM=y
++# CONFIG_X86_SMAP is not set
++CONFIG_X86_UMIP=y
++CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y
++# CONFIG_EFI is not set
++# CONFIG_HZ_100 is not set
++# CONFIG_HZ_250 is not set
++# CONFIG_HZ_300 is not set
++CONFIG_HZ_1000=y
++CONFIG_HZ=1000
++CONFIG_SCHED_HRTICK=y
++CONFIG_KEXEC=y
++CONFIG_KEXEC_FILE=y
++CONFIG_ARCH_HAS_KEXEC_PURGATORY=y
++# CONFIG_KEXEC_SIG is not set
++# CONFIG_CRASH_DUMP is not set
++CONFIG_PHYSICAL_START=0x1000000
++CONFIG_RELOCATABLE=y
++# CONFIG_RANDOMIZE_BASE is not set
++CONFIG_PHYSICAL_ALIGN=0x200000
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set
++# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
++# CONFIG_COMPAT_VDSO is not set
++CONFIG_LEGACY_VSYSCALL_EMULATE=y
++# CONFIG_LEGACY_VSYSCALL_XONLY is not set
++# CONFIG_LEGACY_VSYSCALL_NONE is not set
++# CONFIG_CMDLINE_BOOL is not set
++# CONFIG_MODIFY_LDT_SYSCALL is not set
++CONFIG_HAVE_LIVEPATCH=y
++# end of Processor type and features
++
++CONFIG_ARCH_HAS_ADD_PAGES=y
++CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
++CONFIG_USE_PERCPU_NUMA_NODE_ID=y
++
++#
++# Power management and ACPI options
++#
++# CONFIG_SUSPEND is not set
++# CONFIG_HIBERNATION is not set
++# CONFIG_PM is not set
++CONFIG_ARCH_SUPPORTS_ACPI=y
++CONFIG_ACPI=y
++CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
++CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
++CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
++# CONFIG_ACPI_DEBUGGER is not set
++# CONFIG_ACPI_SPCR_TABLE is not set
++# CONFIG_ACPI_FPDT is not set
++CONFIG_ACPI_LPIT=y
++CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
++# CONFIG_ACPI_EC_DEBUGFS is not set
++# CONFIG_ACPI_AC is not set
++# CONFIG_ACPI_BATTERY is not set
++CONFIG_ACPI_BUTTON=y
++CONFIG_ACPI_VIDEO=y
++# CONFIG_ACPI_FAN is not set
++# CONFIG_ACPI_DOCK is not set
++CONFIG_ACPI_CPU_FREQ_PSS=y
++CONFIG_ACPI_PROCESSOR_CSTATE=y
++CONFIG_ACPI_PROCESSOR_IDLE=y
++CONFIG_ACPI_PROCESSOR=y
++CONFIG_ACPI_HOTPLUG_CPU=y
++CONFIG_ACPI_PROCESSOR_AGGREGATOR=y
++CONFIG_ACPI_THERMAL=y
++CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
++CONFIG_ACPI_TABLE_UPGRADE=y
++# CONFIG_ACPI_DEBUG is not set
++# CONFIG_ACPI_PCI_SLOT is not set
++CONFIG_ACPI_CONTAINER=y
++CONFIG_ACPI_HOTPLUG_IOAPIC=y
++# CONFIG_ACPI_SBS is not set
++# CONFIG_ACPI_HED is not set
++CONFIG_ACPI_CUSTOM_METHOD=y
++# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
++# CONFIG_ACPI_NFIT is not set
++CONFIG_ACPI_NUMA=y
++# CONFIG_ACPI_HMAT is not set
++CONFIG_HAVE_ACPI_APEI=y
++CONFIG_HAVE_ACPI_APEI_NMI=y
++# CONFIG_ACPI_APEI is not set
++# CONFIG_ACPI_DPTF is not set
++# CONFIG_ACPI_CONFIGFS is not set
++# CONFIG_PMIC_OPREGION is not set
++# CONFIG_X86_PM_TIMER is not set
++
++#
++# CPU Frequency scaling
++#
++# CONFIG_CPU_FREQ is not set
++# end of CPU Frequency scaling
++
++#
++# CPU Idle
++#
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_CPU_IDLE_GOV_MENU=y
++# CONFIG_CPU_IDLE_GOV_TEO is not set
++# end of CPU Idle
++# end of Power management and ACPI options
++
++#
++# Bus options (PCI etc.)
++#
++CONFIG_PCI_DIRECT=y
++CONFIG_PCI_MMCONFIG=y
++CONFIG_MMCONF_FAM10H=y
++# CONFIG_PCI_CNB20LE_QUIRK is not set
++# CONFIG_ISA_BUS is not set
++CONFIG_ISA_DMA_API=y
++CONFIG_AMD_NB=y
++# end of Bus options (PCI etc.)
++
++#
++# Binary Emulations
++#
++CONFIG_IA32_EMULATION=y
++CONFIG_X86_X32=y
++CONFIG_COMPAT_32=y
++CONFIG_COMPAT=y
++CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
++CONFIG_SYSVIPC_COMPAT=y
++# end of Binary Emulations
++
++CONFIG_HAVE_KVM=y
++CONFIG_HAVE_KVM_IRQCHIP=y
++CONFIG_HAVE_KVM_IRQFD=y
++CONFIG_HAVE_KVM_IRQ_ROUTING=y
++CONFIG_HAVE_KVM_EVENTFD=y
++CONFIG_KVM_MMIO=y
++CONFIG_KVM_ASYNC_PF=y
++CONFIG_HAVE_KVM_MSI=y
++CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
++CONFIG_KVM_VFIO=y
++CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
++CONFIG_KVM_COMPAT=y
++CONFIG_HAVE_KVM_IRQ_BYPASS=y
++CONFIG_HAVE_KVM_NO_POLL=y
++CONFIG_KVM_XFER_TO_GUEST_WORK=y
++CONFIG_VIRTUALIZATION=y
++CONFIG_KVM=y
++# CONFIG_KVM_WERROR is not set
++CONFIG_KVM_AMD=y
++CONFIG_KVM_XEN=y
++CONFIG_AS_AVX512=y
++CONFIG_AS_SHA1_NI=y
++CONFIG_AS_SHA256_NI=y
++CONFIG_AS_TPAUSE=y
++
++#
++# General architecture-dependent options
++#
++CONFIG_CRASH_CORE=y
++CONFIG_KEXEC_CORE=y
++CONFIG_HOTPLUG_SMT=y
++CONFIG_GENERIC_ENTRY=y
++# CONFIG_KPROBES is not set
++CONFIG_JUMP_LABEL=y
++# CONFIG_STATIC_KEYS_SELFTEST is not set
++# CONFIG_STATIC_CALL_SELFTEST is not set
++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
++CONFIG_ARCH_USE_BUILTIN_BSWAP=y
++CONFIG_USER_RETURN_NOTIFIER=y
++CONFIG_HAVE_IOREMAP_PROT=y
++CONFIG_HAVE_KPROBES=y
++CONFIG_HAVE_KRETPROBES=y
++CONFIG_HAVE_OPTPROBES=y
++CONFIG_HAVE_KPROBES_ON_FTRACE=y
++CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
++CONFIG_HAVE_NMI=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HAVE_ARCH_TRACEHOOK=y
++CONFIG_HAVE_DMA_CONTIGUOUS=y
++CONFIG_GENERIC_SMP_IDLE_THREAD=y
++CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
++CONFIG_ARCH_HAS_SET_MEMORY=y
++CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
++CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
++CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
++CONFIG_ARCH_WANTS_NO_INSTR=y
++CONFIG_HAVE_ASM_MODVERSIONS=y
++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
++CONFIG_HAVE_RSEQ=y
++CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
++CONFIG_HAVE_HW_BREAKPOINT=y
++CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
++CONFIG_HAVE_USER_RETURN_NOTIFIER=y
++CONFIG_HAVE_PERF_EVENTS_NMI=y
++CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
++CONFIG_HAVE_PERF_REGS=y
++CONFIG_HAVE_PERF_USER_STACK_DUMP=y
++CONFIG_HAVE_ARCH_JUMP_LABEL=y
++CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
++CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
++CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
++CONFIG_HAVE_CMPXCHG_LOCAL=y
++CONFIG_HAVE_CMPXCHG_DOUBLE=y
++CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
++CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y
++CONFIG_HAVE_ARCH_SECCOMP=y
++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
++# CONFIG_SECCOMP is not set
++CONFIG_HAVE_ARCH_STACKLEAK=y
++CONFIG_HAVE_STACKPROTECTOR=y
++# CONFIG_STACKPROTECTOR is not set
++CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
++CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
++CONFIG_LTO_NONE=y
++CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y
++CONFIG_HAVE_CONTEXT_TRACKING=y
++CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y
++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
++CONFIG_HAVE_MOVE_PUD=y
++CONFIG_HAVE_MOVE_PMD=y
++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y
++CONFIG_HAVE_ARCH_HUGE_VMAP=y
++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
++CONFIG_HAVE_ARCH_SOFT_DIRTY=y
++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
++CONFIG_MODULES_USE_ELF_RELA=y
++CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
++CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
++CONFIG_HAVE_EXIT_THREAD=y
++CONFIG_ARCH_MMAP_RND_BITS=28
++CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
++CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8
++CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y
++CONFIG_HAVE_STACK_VALIDATION=y
++CONFIG_HAVE_RELIABLE_STACKTRACE=y
++CONFIG_OLD_SIGSUSPEND3=y
++CONFIG_COMPAT_OLD_SIGACTION=y
++CONFIG_COMPAT_32BIT_TIME=y
++CONFIG_HAVE_ARCH_VMAP_STACK=y
++# CONFIG_VMAP_STACK is not set
++CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
++# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
++CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
++CONFIG_STRICT_KERNEL_RWX=y
++CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
++CONFIG_STRICT_MODULE_RWX=y
++CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
++# CONFIG_LOCK_EVENT_COUNTS is not set
++CONFIG_ARCH_HAS_MEM_ENCRYPT=y
++CONFIG_HAVE_STATIC_CALL=y
++CONFIG_HAVE_STATIC_CALL_INLINE=y
++CONFIG_HAVE_PREEMPT_DYNAMIC=y
++CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
++CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
++CONFIG_ARCH_HAS_ELFCORE_COMPAT=y
++CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y
++
++#
++# GCOV-based kernel profiling
++#
++# CONFIG_GCOV_KERNEL is not set
++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
++# end of GCOV-based kernel profiling
++
++CONFIG_HAVE_GCC_PLUGINS=y
++CONFIG_GCC_PLUGINS=y
++# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
++# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
++# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
++# end of General architecture-dependent options
++
++CONFIG_RT_MUTEXES=y
++CONFIG_BASE_SMALL=0
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++# CONFIG_MODULE_SIG is not set
++CONFIG_MODULE_COMPRESS_NONE=y
++# CONFIG_MODULE_COMPRESS_GZIP is not set
++# CONFIG_MODULE_COMPRESS_XZ is not set
++# CONFIG_MODULE_COMPRESS_ZSTD is not set
++# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
++CONFIG_MODPROBE_PATH="/sbin/modprobe"
++# CONFIG_TRIM_UNUSED_KSYMS is not set
++CONFIG_MODULES_TREE_LOOKUP=y
++CONFIG_BLOCK=y
++CONFIG_BLK_DEV_BSG_COMMON=y
++# CONFIG_BLK_DEV_BSGLIB is not set
++# CONFIG_BLK_DEV_INTEGRITY is not set
++# CONFIG_BLK_DEV_ZONED is not set
++# CONFIG_BLK_DEV_THROTTLING is not set
++CONFIG_BLK_WBT=y
++CONFIG_BLK_WBT_MQ=y
++# CONFIG_BLK_CGROUP_IOLATENCY is not set
++# CONFIG_BLK_CGROUP_IOCOST is not set
++# CONFIG_BLK_CGROUP_IOPRIO is not set
++CONFIG_BLK_DEBUG_FS=y
++# CONFIG_BLK_SED_OPAL is not set
++# CONFIG_BLK_INLINE_ENCRYPTION is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++# CONFIG_AIX_PARTITION is not set
++# CONFIG_OSF_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_ATARI_PARTITION is not set
++# CONFIG_MAC_PARTITION is not set
++CONFIG_MSDOS_PARTITION=y
++CONFIG_BSD_DISKLABEL=y
++# CONFIG_MINIX_SUBPARTITION is not set
++# CONFIG_SOLARIS_X86_PARTITION is not set
++# CONFIG_UNIXWARE_DISKLABEL is not set
++# CONFIG_LDM_PARTITION is not set
++# CONFIG_SGI_PARTITION is not set
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_SUN_PARTITION is not set
++# CONFIG_KARMA_PARTITION is not set
++CONFIG_EFI_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++# CONFIG_CMDLINE_PARTITION is not set
++# end of Partition Types
++
++CONFIG_BLOCK_COMPAT=y
++CONFIG_BLK_MQ_PCI=y
++CONFIG_BLOCK_HOLDER_DEPRECATED=y
++
++#
++# IO Schedulers
++#
++CONFIG_MQ_IOSCHED_DEADLINE=y
++CONFIG_MQ_IOSCHED_KYBER=y
++# CONFIG_IOSCHED_BFQ is not set
++# end of IO Schedulers
++
++CONFIG_PREEMPT_NOTIFIERS=y
++CONFIG_ASN1=y
++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
++CONFIG_INLINE_READ_UNLOCK=y
++CONFIG_INLINE_READ_UNLOCK_IRQ=y
++CONFIG_INLINE_WRITE_UNLOCK=y
++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
++CONFIG_MUTEX_SPIN_ON_OWNER=y
++CONFIG_RWSEM_SPIN_ON_OWNER=y
++CONFIG_LOCK_SPIN_ON_OWNER=y
++CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
++CONFIG_QUEUED_SPINLOCKS=y
++CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
++CONFIG_QUEUED_RWLOCKS=y
++CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
++CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y
++CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
++CONFIG_FREEZER=y
++
++#
++# Executable file formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_COMPAT_BINFMT_ELF=y
++CONFIG_ELFCORE=y
++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
++CONFIG_BINFMT_SCRIPT=y
++CONFIG_BINFMT_MISC=y
++CONFIG_COREDUMP=y
++# end of Executable file formats
++
++#
++# Memory Management options
++#
++CONFIG_SELECT_MEMORY_MODEL=y
++CONFIG_SPARSEMEM_MANUAL=y
++CONFIG_SPARSEMEM=y
++CONFIG_SPARSEMEM_EXTREME=y
++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
++CONFIG_SPARSEMEM_VMEMMAP=y
++CONFIG_HAVE_FAST_GUP=y
++CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
++# CONFIG_MEMORY_HOTPLUG is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4
++CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
++CONFIG_COMPACTION=y
++# CONFIG_PAGE_REPORTING is not set
++CONFIG_MIGRATION=y
++CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
++CONFIG_ARCH_ENABLE_THP_MIGRATION=y
++CONFIG_PHYS_ADDR_T_64BIT=y
++CONFIG_VIRT_TO_BUS=y
++CONFIG_MMU_NOTIFIER=y
++CONFIG_KSM=y
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
++# CONFIG_MEMORY_FAILURE is not set
++CONFIG_TRANSPARENT_HUGEPAGE=y
++CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
++# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
++CONFIG_ARCH_WANTS_THP_SWAP=y
++CONFIG_THP_SWAP=y
++CONFIG_CLEANCACHE=y
++CONFIG_FRONTSWAP=y
++# CONFIG_CMA is not set
++# CONFIG_ZSWAP is not set
++CONFIG_ZPOOL=y
++# CONFIG_ZBUD is not set
++# CONFIG_Z3FOLD is not set
++# CONFIG_ZSMALLOC is not set
++CONFIG_GENERIC_EARLY_IOREMAP=y
++# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
++# CONFIG_IDLE_PAGE_TRACKING is not set
++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
++CONFIG_ARCH_HAS_PTE_DEVMAP=y
++CONFIG_ARCH_HAS_ZONE_DMA_SET=y
++CONFIG_ZONE_DMA=y
++CONFIG_ZONE_DMA32=y
++CONFIG_HMM_MIRROR=y
++CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
++CONFIG_ARCH_HAS_PKEYS=y
++# CONFIG_PERCPU_STATS is not set
++# CONFIG_GUP_TEST is not set
++# CONFIG_READ_ONLY_THP_FOR_FS is not set
++CONFIG_ARCH_HAS_PTE_SPECIAL=y
++CONFIG_SECRETMEM=y
++
++#
++# Data Access Monitoring
++#
++# CONFIG_DAMON is not set
++# end of Data Access Monitoring
++# end of Memory Management options
++
++CONFIG_NET=y
++CONFIG_COMPAT_NETLINK_MESSAGES=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_SCM=y
++CONFIG_AF_UNIX_OOB=y
++CONFIG_UNIX_DIAG=y
++# CONFIG_TLS is not set
++# CONFIG_XFRM_USER is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE_DEMUX is not set
++CONFIG_NET_IP_TUNNEL=y
++# CONFIG_IP_MROUTE is not set
++CONFIG_SYN_COOKIES=y
++# CONFIG_NET_IPVTI is not set
++CONFIG_NET_UDP_TUNNEL=y
++# CONFIG_NET_FOU is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++CONFIG_INET_UDP_DIAG=y
++# CONFIG_INET_RAW_DIAG is not set
++# CONFIG_INET_DIAG_DESTROY is not set
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_TCP_MD5SIG is not set
++CONFIG_IPV6=y
++# CONFIG_IPV6_ROUTER_PREF is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++# CONFIG_INET6_AH is not set
++# CONFIG_INET6_ESP is not set
++# CONFIG_INET6_IPCOMP is not set
++# CONFIG_IPV6_MIP6 is not set
++# CONFIG_IPV6_VTI is not set
++# CONFIG_IPV6_SIT is not set
++# CONFIG_IPV6_TUNNEL is not set
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
++# CONFIG_IPV6_MROUTE is not set
++# CONFIG_IPV6_SEG6_LWTUNNEL is not set
++# CONFIG_IPV6_SEG6_HMAC is not set
++# CONFIG_IPV6_RPL_LWTUNNEL is not set
++# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
++# CONFIG_MPTCP is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
++# CONFIG_NETFILTER is not set
++# CONFIG_BPFILTER is not set
++# CONFIG_IP_DCCP is not set
++# CONFIG_IP_SCTP is not set
++# CONFIG_RDS is not set
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_L2TP is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_NET_DSA is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_PHONET is not set
++# CONFIG_6LOWPAN is not set
++# CONFIG_IEEE802154 is not set
++# CONFIG_NET_SCHED is not set
++# CONFIG_DCB is not set
++# CONFIG_DNS_RESOLVER is not set
++# CONFIG_BATMAN_ADV is not set
++# CONFIG_OPENVSWITCH is not set
++# CONFIG_VSOCKETS is not set
++CONFIG_NETLINK_DIAG=y
++# CONFIG_MPLS is not set
++# CONFIG_NET_NSH is not set
++# CONFIG_HSR is not set
++# CONFIG_NET_SWITCHDEV is not set
++# CONFIG_NET_L3_MASTER_DEV is not set
++# CONFIG_QRTR is not set
++# CONFIG_NET_NCSI is not set
++CONFIG_PCPU_DEV_REFCNT=y
++CONFIG_RPS=y
++CONFIG_RFS_ACCEL=y
++CONFIG_SOCK_RX_QUEUE_MAPPING=y
++CONFIG_XPS=y
++# CONFIG_CGROUP_NET_PRIO is not set
++# CONFIG_CGROUP_NET_CLASSID is not set
++CONFIG_NET_RX_BUSY_POLL=y
++CONFIG_BQL=y
++CONFIG_NET_FLOW_LIMIT=y
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# end of Network testing
++# end of Networking options
++
++# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
++CONFIG_BT=y
++CONFIG_BT_BREDR=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++CONFIG_BT_HS=y
++CONFIG_BT_LE=y
++# CONFIG_BT_LEDS is not set
++# CONFIG_BT_MSFTEXT is not set
++# CONFIG_BT_AOSPEXT is not set
++# CONFIG_BT_DEBUGFS is not set
++# CONFIG_BT_SELFTEST is not set
++# CONFIG_BT_FEATURE_DEBUG is not set
++
++#
++# Bluetooth device drivers
++#
++# CONFIG_BT_HCIBTUSB is not set
++CONFIG_BT_HCIBTSDIO=y
++# CONFIG_BT_HCIUART is not set
++# CONFIG_BT_HCIBCM203X is not set
++# CONFIG_BT_HCIBPA10X is not set
++# CONFIG_BT_HCIBFUSB is not set
++# CONFIG_BT_HCIVHCI is not set
++CONFIG_BT_MRVL=y
++CONFIG_BT_MRVL_SDIO=y
++# CONFIG_BT_MTKSDIO is not set
++# end of Bluetooth device drivers
++
++# CONFIG_AF_RXRPC is not set
++# CONFIG_AF_KCM is not set
++# CONFIG_MCTP is not set
++CONFIG_WIRELESS=y
++CONFIG_WEXT_CORE=y
++CONFIG_WEXT_PROC=y
++CONFIG_CFG80211=y
++# CONFIG_NL80211_TESTMODE is not set
++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
++CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
++CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
++CONFIG_CFG80211_DEFAULT_PS=y
++# CONFIG_CFG80211_DEBUGFS is not set
++CONFIG_CFG80211_CRDA_SUPPORT=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_HAS_RC=y
++CONFIG_MAC80211_RC_MINSTREL=y
++CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
++CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
++# CONFIG_MAC80211_MESH is not set
++# CONFIG_MAC80211_LEDS is not set
++# CONFIG_MAC80211_DEBUGFS is not set
++# CONFIG_MAC80211_MESSAGE_TRACING is not set
++# CONFIG_MAC80211_DEBUG_MENU is not set
++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
++CONFIG_RFKILL=y
++CONFIG_RFKILL_LEDS=y
++CONFIG_RFKILL_INPUT=y
++# CONFIG_NET_9P is not set
++# CONFIG_CAIF is not set
++# CONFIG_CEPH_LIB is not set
++# CONFIG_NFC is not set
++# CONFIG_PSAMPLE is not set
++# CONFIG_NET_IFE is not set
++# CONFIG_LWTUNNEL is not set
++CONFIG_DST_CACHE=y
++CONFIG_GRO_CELLS=y
++CONFIG_NET_SELFTESTS=y
++# CONFIG_FAILOVER is not set
++CONFIG_ETHTOOL_NETLINK=y
++
++#
++# Device Drivers
++#
++CONFIG_HAVE_EISA=y
++# CONFIG_EISA is not set
++CONFIG_HAVE_PCI=y
++CONFIG_PCI=y
++CONFIG_PCI_DOMAINS=y
++CONFIG_PCIEPORTBUS=y
++CONFIG_PCIEAER=y
++# CONFIG_PCIEAER_INJECT is not set
++# CONFIG_PCIE_ECRC is not set
++CONFIG_PCIEASPM=y
++# CONFIG_PCIEASPM_DEFAULT is not set
++# CONFIG_PCIEASPM_POWERSAVE is not set
++# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
++CONFIG_PCIEASPM_PERFORMANCE=y
++# CONFIG_PCIE_DPC is not set
++# CONFIG_PCIE_PTM is not set
++CONFIG_PCI_MSI=y
++CONFIG_PCI_MSI_IRQ_DOMAIN=y
++CONFIG_PCI_QUIRKS=y
++# CONFIG_PCI_DEBUG is not set
++# CONFIG_PCI_STUB is not set
++CONFIG_PCI_ATS=y
++CONFIG_PCI_LOCKLESS_CONFIG=y
++# CONFIG_PCI_IOV is not set
++CONFIG_PCI_PRI=y
++CONFIG_PCI_PASID=y
++CONFIG_PCI_LABEL=y
++# CONFIG_PCIE_BUS_TUNE_OFF is not set
++CONFIG_PCIE_BUS_DEFAULT=y
++# CONFIG_PCIE_BUS_SAFE is not set
++# CONFIG_PCIE_BUS_PERFORMANCE is not set
++# CONFIG_PCIE_BUS_PEER2PEER is not set
++# CONFIG_HOTPLUG_PCI is not set
++
++#
++# PCI controller drivers
++#
++# CONFIG_VMD is not set
++
++#
++# DesignWare PCI Core Support
++#
++# CONFIG_PCIE_DW_PLAT_HOST is not set
++# CONFIG_PCI_MESON is not set
++# end of DesignWare PCI Core Support
++
++#
++# Mobiveil PCIe Core Support
++#
++# end of Mobiveil PCIe Core Support
++
++#
++# Cadence PCIe controllers support
++#
++# end of Cadence PCIe controllers support
++# end of PCI controller drivers
++
++#
++# PCI Endpoint
++#
++# CONFIG_PCI_ENDPOINT is not set
++# end of PCI Endpoint
++
++#
++# PCI switch controller drivers
++#
++# CONFIG_PCI_SW_SWITCHTEC is not set
++# end of PCI switch controller drivers
++
++# CONFIG_CXL_BUS is not set
++# CONFIG_PCCARD is not set
++# CONFIG_RAPIDIO is not set
++
++#
++# Generic Driver Options
++#
++# CONFIG_UEVENT_HELPER is not set
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++
++#
++# Firmware loader
++#
++CONFIG_FW_LOADER=y
++CONFIG_EXTRA_FIRMWARE="mrvl/sd8897_uapsta.bin mrvl/sd8797_uapsta.bin"
++CONFIG_EXTRA_FIRMWARE_DIR="/lib/firmware"
++# CONFIG_FW_LOADER_USER_HELPER is not set
++# CONFIG_FW_LOADER_COMPRESS is not set
++# end of Firmware loader
++
++CONFIG_WANT_DEV_COREDUMP=y
++CONFIG_ALLOW_DEV_COREDUMP=y
++CONFIG_DEV_COREDUMP=y
++# CONFIG_DEBUG_DRIVER is not set
++# CONFIG_DEBUG_DEVRES is not set
++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
++# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
++CONFIG_GENERIC_CPU_AUTOPROBE=y
++CONFIG_GENERIC_CPU_VULNERABILITIES=y
++CONFIG_REGMAP=y
++CONFIG_REGMAP_I2C=y
++CONFIG_DMA_SHARED_BUFFER=y
++# CONFIG_DMA_FENCE_TRACE is not set
++# end of Generic Driver Options
++
++#
++# Bus devices
++#
++# CONFIG_MHI_BUS is not set
++# end of Bus devices
++
++CONFIG_CONNECTOR=y
++CONFIG_PROC_EVENTS=y
++
++#
++# Firmware Drivers
++#
++
++#
++# ARM System Control and Management Interface Protocol
++#
++# end of ARM System Control and Management Interface Protocol
++
++# CONFIG_EDD is not set
++CONFIG_FIRMWARE_MEMMAP=y
++CONFIG_DMIID=y
++CONFIG_DMI_SYSFS=y
++CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
++# CONFIG_FW_CFG_SYSFS is not set
++CONFIG_SYSFB=y
++# CONFIG_SYSFB_SIMPLEFB is not set
++# CONFIG_GOOGLE_FIRMWARE is not set
++
++#
++# Tegra firmware driver
++#
++# end of Tegra firmware driver
++# end of Firmware Drivers
++
++# CONFIG_GNSS is not set
++# CONFIG_MTD is not set
++# CONFIG_OF is not set
++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
++# CONFIG_PARPORT is not set
++CONFIG_PNP=y
++CONFIG_PNP_DEBUG_MESSAGES=y
++
++#
++# Protocols
++#
++CONFIG_PNPACPI=y
++CONFIG_BLK_DEV=y
++# CONFIG_BLK_DEV_NULL_BLK is not set
++# CONFIG_BLK_DEV_FD is not set
++CONFIG_CDROM=y
++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_DRBD is not set
++# CONFIG_BLK_DEV_NBD is not set
++# CONFIG_BLK_DEV_SX8 is not set
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=1
++CONFIG_BLK_DEV_RAM_SIZE=32768
++# CONFIG_CDROM_PKTCDVD is not set
++# CONFIG_ATA_OVER_ETH is not set
++# CONFIG_BLK_DEV_RBD is not set
++# CONFIG_BLK_DEV_RSXX is not set
++
++#
++# NVME Support
++#
++# CONFIG_BLK_DEV_NVME is not set
++# CONFIG_NVME_FC is not set
++# CONFIG_NVME_TCP is not set
++# CONFIG_NVME_TARGET is not set
++# end of NVME Support
++
++#
++# Misc devices
++#
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_IBM_ASM is not set
++# CONFIG_PHANTOM is not set
++# CONFIG_TIFM_CORE is not set
++# CONFIG_ICS932S401 is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HP_ILO is not set
++# CONFIG_APDS9802ALS is not set
++# CONFIG_ISL29003 is not set
++# CONFIG_ISL29020 is not set
++# CONFIG_SENSORS_TSL2550 is not set
++# CONFIG_SENSORS_BH1770 is not set
++# CONFIG_SENSORS_APDS990X is not set
++# CONFIG_HMC6352 is not set
++# CONFIG_DS1682 is not set
++# CONFIG_SRAM is not set
++# CONFIG_DW_XDATA_PCIE is not set
++# CONFIG_PCI_ENDPOINT_TEST is not set
++# CONFIG_XILINX_SDFEC is not set
++# CONFIG_C2PORT is not set
++
++#
++# EEPROM support
++#
++CONFIG_EEPROM_AT24=y
++CONFIG_EEPROM_LEGACY=y
++# CONFIG_EEPROM_MAX6875 is not set
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_EEPROM_IDT_89HPESX is not set
++# CONFIG_EEPROM_EE1004 is not set
++# end of EEPROM support
++
++# CONFIG_CB710_CORE is not set
++
++#
++# Texas Instruments shared transport line discipline
++#
++# end of Texas Instruments shared transport line discipline
++
++# CONFIG_SENSORS_LIS3_I2C is not set
++# CONFIG_ALTERA_STAPL is not set
++# CONFIG_INTEL_MEI is not set
++# CONFIG_INTEL_MEI_ME is not set
++# CONFIG_INTEL_MEI_TXE is not set
++# CONFIG_VMWARE_VMCI is not set
++# CONFIG_GENWQE is not set
++# CONFIG_ECHO is not set
++# CONFIG_BCM_VK is not set
++# CONFIG_MISC_ALCOR_PCI is not set
++# CONFIG_MISC_RTSX_PCI is not set
++# CONFIG_MISC_RTSX_USB is not set
++# CONFIG_HABANA_AI is not set
++# CONFIG_UACCE is not set
++# CONFIG_PVPANIC is not set
++# end of Misc devices
++
++#
++# SCSI device support
++#
++CONFIG_SCSI_MOD=y
++# CONFIG_RAID_ATTRS is not set
++CONFIG_SCSI_COMMON=y
++CONFIG_SCSI=y
++CONFIG_SCSI_DMA=y
++CONFIG_SCSI_PROC_FS=y
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_BLK_DEV_SD=y
++# CONFIG_CHR_DEV_ST is not set
++CONFIG_BLK_DEV_SR=y
++CONFIG_CHR_DEV_SG=y
++CONFIG_BLK_DEV_BSG=y
++# CONFIG_CHR_DEV_SCH is not set
++# CONFIG_SCSI_CONSTANTS is not set
++# CONFIG_SCSI_LOGGING is not set
++# CONFIG_SCSI_SCAN_ASYNC is not set
++
++#
++# SCSI Transports
++#
++# CONFIG_SCSI_SPI_ATTRS is not set
++# CONFIG_SCSI_FC_ATTRS is not set
++# CONFIG_SCSI_ISCSI_ATTRS is not set
++# CONFIG_SCSI_SAS_ATTRS is not set
++# CONFIG_SCSI_SAS_LIBSAS is not set
++# CONFIG_SCSI_SRP_ATTRS is not set
++# end of SCSI Transports
++
++# CONFIG_SCSI_LOWLEVEL is not set
++# CONFIG_SCSI_DH is not set
++# end of SCSI device support
++
++CONFIG_ATA=y
++CONFIG_SATA_HOST=y
++CONFIG_PATA_TIMINGS=y
++CONFIG_ATA_VERBOSE_ERROR=y
++CONFIG_ATA_FORCE=y
++CONFIG_ATA_ACPI=y
++CONFIG_SATA_PMP=y
++
++#
++# Controllers with non-SFF native interface
++#
++CONFIG_SATA_AHCI=y
++CONFIG_SATA_MOBILE_LPM_POLICY=0
++# CONFIG_SATA_AHCI_PLATFORM is not set
++# CONFIG_SATA_INIC162X is not set
++# CONFIG_SATA_ACARD_AHCI is not set
++# CONFIG_SATA_SIL24 is not set
++# CONFIG_ATA_SFF is not set
++CONFIG_MD=y
++# CONFIG_BLK_DEV_MD is not set
++# CONFIG_BCACHE is not set
++CONFIG_BLK_DEV_DM_BUILTIN=y
++CONFIG_BLK_DEV_DM=y
++# CONFIG_DM_DEBUG is not set
++# CONFIG_DM_UNSTRIPED is not set
++CONFIG_DM_CRYPT=y
++# CONFIG_DM_SNAPSHOT is not set
++# CONFIG_DM_THIN_PROVISIONING is not set
++# CONFIG_DM_CACHE is not set
++# CONFIG_DM_WRITECACHE is not set
++# CONFIG_DM_EBS is not set
++# CONFIG_DM_ERA is not set
++# CONFIG_DM_CLONE is not set
++# CONFIG_DM_MIRROR is not set
++# CONFIG_DM_RAID is not set
++# CONFIG_DM_ZERO is not set
++# CONFIG_DM_MULTIPATH is not set
++# CONFIG_DM_DELAY is not set
++# CONFIG_DM_DUST is not set
++# CONFIG_DM_INIT is not set
++# CONFIG_DM_UEVENT is not set
++# CONFIG_DM_FLAKEY is not set
++# CONFIG_DM_VERITY is not set
++# CONFIG_DM_SWITCH is not set
++# CONFIG_DM_LOG_WRITES is not set
++# CONFIG_DM_INTEGRITY is not set
++# CONFIG_TARGET_CORE is not set
++# CONFIG_FUSION is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++# CONFIG_FIREWIRE is not set
++# CONFIG_FIREWIRE_NOSY is not set
++# end of IEEE 1394 (FireWire) support
++
++# CONFIG_MACINTOSH_DRIVERS is not set
++CONFIG_NETDEVICES=y
++CONFIG_NET_CORE=y
++# CONFIG_BONDING is not set
++# CONFIG_DUMMY is not set
++CONFIG_WIREGUARD=y
++# CONFIG_WIREGUARD_DEBUG is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_NET_FC is not set
++# CONFIG_NET_TEAM is not set
++# CONFIG_MACVLAN is not set
++# CONFIG_IPVLAN is not set
++# CONFIG_VXLAN is not set
++# CONFIG_GENEVE is not set
++# CONFIG_BAREUDP is not set
++# CONFIG_GTP is not set
++# CONFIG_MACSEC is not set
++CONFIG_NETCONSOLE=y
++# CONFIG_NETCONSOLE_DYNAMIC is not set
++CONFIG_NETPOLL=y
++CONFIG_NET_POLL_CONTROLLER=y
++# CONFIG_TUN is not set
++# CONFIG_TUN_VNET_CROSS_LE is not set
++# CONFIG_VETH is not set
++# CONFIG_NLMON is not set
++# CONFIG_ARCNET is not set
++CONFIG_ETHERNET=y
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_NET_VENDOR_ADAPTEC is not set
++# CONFIG_NET_VENDOR_AGERE is not set
++# CONFIG_NET_VENDOR_ALACRITECH is not set
++# CONFIG_NET_VENDOR_ALTEON is not set
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AMD is not set
++# CONFIG_NET_VENDOR_AQUANTIA is not set
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_ATHEROS is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_BROCADE is not set
++# CONFIG_NET_VENDOR_CADENCE is not set
++# CONFIG_NET_VENDOR_CAVIUM is not set
++# CONFIG_NET_VENDOR_CHELSIO is not set
++# CONFIG_NET_VENDOR_CISCO is not set
++# CONFIG_NET_VENDOR_CORTINA is not set
++# CONFIG_CX_ECAT is not set
++# CONFIG_DNET is not set
++# CONFIG_NET_VENDOR_DEC is not set
++# CONFIG_NET_VENDOR_DLINK is not set
++# CONFIG_NET_VENDOR_EMULEX is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_GOOGLE is not set
++# CONFIG_NET_VENDOR_HUAWEI is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MICROSOFT is not set
++# CONFIG_JME is not set
++# CONFIG_NET_VENDOR_LITEX is not set
++CONFIG_NET_VENDOR_MARVELL=y
++# CONFIG_MVMDIO is not set
++# CONFIG_SKGE is not set
++CONFIG_SKY2=y
++# CONFIG_SKY2_DEBUG is not set
++# CONFIG_NET_VENDOR_MELLANOX is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_MICROSEMI is not set
++# CONFIG_NET_VENDOR_MYRI is not set
++# CONFIG_FEALNX is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETERION is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++# CONFIG_NET_VENDOR_NI is not set
++# CONFIG_NET_VENDOR_NVIDIA is not set
++# CONFIG_NET_VENDOR_OKI is not set
++# CONFIG_ETHOC is not set
++# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
++# CONFIG_NET_VENDOR_PENSANDO is not set
++# CONFIG_NET_VENDOR_QLOGIC is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++# CONFIG_NET_VENDOR_RDC is not set
++# CONFIG_NET_VENDOR_REALTEK is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SOLARFLARE is not set
++# CONFIG_NET_VENDOR_SILAN is not set
++# CONFIG_NET_VENDOR_SIS is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_SOCIONEXT is not set
++# CONFIG_NET_VENDOR_STMICRO is not set
++# CONFIG_NET_VENDOR_SUN is not set
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_TEHUTI is not set
++# CONFIG_NET_VENDOR_TI is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_NET_VENDOR_XILINX is not set
++# CONFIG_FDDI is not set
++# CONFIG_HIPPI is not set
++# CONFIG_NET_SB1000 is not set
++CONFIG_PHYLIB=y
++CONFIG_SWPHY=y
++# CONFIG_LED_TRIGGER_PHY is not set
++CONFIG_FIXED_PHY=y
++
++#
++# MII PHY device drivers
++#
++# CONFIG_AMD_PHY is not set
++# CONFIG_ADIN_PHY is not set
++# CONFIG_AQUANTIA_PHY is not set
++# CONFIG_AX88796B_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_BCM54140_PHY is not set
++# CONFIG_BCM7XXX_PHY is not set
++# CONFIG_BCM84881_PHY is not set
++# CONFIG_BCM87XX_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_CORTINA_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_INTEL_XWAY_PHY is not set
++# CONFIG_LSI_ET1011C_PHY is not set
++CONFIG_MARVELL_PHY=y
++# CONFIG_MARVELL_10G_PHY is not set
++# CONFIG_MARVELL_88X2222_PHY is not set
++# CONFIG_MAXLINEAR_GPHY is not set
++# CONFIG_MEDIATEK_GE_PHY is not set
++# CONFIG_MICREL_PHY is not set
++# CONFIG_MICROCHIP_PHY is not set
++# CONFIG_MICROCHIP_T1_PHY is not set
++# CONFIG_MICROSEMI_PHY is not set
++# CONFIG_MOTORCOMM_PHY is not set
++# CONFIG_NATIONAL_PHY is not set
++# CONFIG_NXP_C45_TJA11XX_PHY is not set
++# CONFIG_NXP_TJA11XX_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_RENESAS_PHY is not set
++# CONFIG_ROCKCHIP_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_STE10XP is not set
++# CONFIG_TERANETICS_PHY is not set
++# CONFIG_DP83822_PHY is not set
++# CONFIG_DP83TC811_PHY is not set
++# CONFIG_DP83848_PHY is not set
++# CONFIG_DP83867_PHY is not set
++# CONFIG_DP83869_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_XILINX_GMII2RGMII is not set
++CONFIG_MDIO_DEVICE=y
++CONFIG_MDIO_BUS=y
++CONFIG_FWNODE_MDIO=y
++CONFIG_ACPI_MDIO=y
++CONFIG_MDIO_DEVRES=y
++# CONFIG_MDIO_BITBANG is not set
++# CONFIG_MDIO_BCM_UNIMAC is not set
++# CONFIG_MDIO_MVUSB is not set
++# CONFIG_MDIO_MSCC_MIIM is not set
++# CONFIG_MDIO_THUNDER is not set
++
++#
++# MDIO Multiplexers
++#
++
++#
++# PCS device drivers
++#
++# CONFIG_PCS_XPCS is not set
++# end of PCS device drivers
++
++# CONFIG_PPP is not set
++# CONFIG_SLIP is not set
++# CONFIG_USB_NET_DRIVERS is not set
++CONFIG_WLAN=y
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++# CONFIG_WLAN_VENDOR_BROADCOM is not set
++# CONFIG_WLAN_VENDOR_CISCO is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++CONFIG_WLAN_VENDOR_MARVELL=y
++# CONFIG_LIBERTAS is not set
++# CONFIG_LIBERTAS_THINFIRM is not set
++CONFIG_MWIFIEX=y
++CONFIG_MWIFIEX_SDIO=y
++# CONFIG_MWIFIEX_PCIE is not set
++# CONFIG_MWIFIEX_USB is not set
++# CONFIG_MWL8K is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++CONFIG_WLAN_VENDOR_MICROCHIP=y
++# CONFIG_WILC1000_SDIO is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++# CONFIG_MAC80211_HWSIM is not set
++# CONFIG_USB_NET_RNDIS_WLAN is not set
++# CONFIG_VIRT_WIFI is not set
++# CONFIG_WAN is not set
++
++#
++# Wireless WAN
++#
++# CONFIG_WWAN is not set
++# end of Wireless WAN
++
++# CONFIG_VMXNET3 is not set
++# CONFIG_FUJITSU_ES is not set
++# CONFIG_NETDEVSIM is not set
++# CONFIG_NET_FAILOVER is not set
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_LEDS=y
++CONFIG_INPUT_FF_MEMLESS=y
++# CONFIG_INPUT_SPARSEKMAP is not set
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1280
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=1024
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_ADP5588 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++CONFIG_KEYBOARD_ATKBD=y
++# CONFIG_KEYBOARD_QT1050 is not set
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_DLINK_DIR685 is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_LM8323 is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++CONFIG_INPUT_MOUSE=y
++# CONFIG_MOUSE_PS2 is not set
++# CONFIG_MOUSE_SERIAL is not set
++# CONFIG_MOUSE_APPLETOUCH is not set
++# CONFIG_MOUSE_BCM5974 is not set
++# CONFIG_MOUSE_CYAPA is not set
++# CONFIG_MOUSE_ELAN_I2C is not set
++# CONFIG_MOUSE_VSXXXAA is not set
++# CONFIG_MOUSE_SYNAPTICS_I2C is not set
++# CONFIG_MOUSE_SYNAPTICS_USB is not set
++CONFIG_INPUT_JOYSTICK=y
++# CONFIG_JOYSTICK_ANALOG is not set
++# CONFIG_JOYSTICK_A3D is not set
++# CONFIG_JOYSTICK_ADI is not set
++# CONFIG_JOYSTICK_COBRA is not set
++# CONFIG_JOYSTICK_GF2K is not set
++# CONFIG_JOYSTICK_GRIP is not set
++# CONFIG_JOYSTICK_GRIP_MP is not set
++# CONFIG_JOYSTICK_GUILLEMOT is not set
++# CONFIG_JOYSTICK_INTERACT is not set
++# CONFIG_JOYSTICK_SIDEWINDER is not set
++# CONFIG_JOYSTICK_TMDC is not set
++# CONFIG_JOYSTICK_IFORCE is not set
++# CONFIG_JOYSTICK_WARRIOR is not set
++# CONFIG_JOYSTICK_MAGELLAN is not set
++# CONFIG_JOYSTICK_SPACEORB is not set
++# CONFIG_JOYSTICK_SPACEBALL is not set
++# CONFIG_JOYSTICK_STINGER is not set
++# CONFIG_JOYSTICK_TWIDJOY is not set
++# CONFIG_JOYSTICK_ZHENHUA is not set
++# CONFIG_JOYSTICK_AS5011 is not set
++# CONFIG_JOYSTICK_JOYDUMP is not set
++CONFIG_JOYSTICK_XPAD=y
++CONFIG_JOYSTICK_XPAD_FF=y
++# CONFIG_JOYSTICK_XPAD_LEDS is not set
++# CONFIG_JOYSTICK_PXRC is not set
++# CONFIG_JOYSTICK_QWIIC is not set
++# CONFIG_JOYSTICK_FSIA6B is not set
++# CONFIG_INPUT_TABLET is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++CONFIG_INPUT_MISC=y
++# CONFIG_INPUT_AD714X is not set
++# CONFIG_INPUT_BMA150 is not set
++# CONFIG_INPUT_E3X0_BUTTON is not set
++# CONFIG_INPUT_MMA8450 is not set
++# CONFIG_INPUT_APANEL is not set
++# CONFIG_INPUT_ATLAS_BTNS is not set
++# CONFIG_INPUT_ATI_REMOTE2 is not set
++# CONFIG_INPUT_KEYSPAN_REMOTE is not set
++# CONFIG_INPUT_KXTJ9 is not set
++# CONFIG_INPUT_POWERMATE is not set
++# CONFIG_INPUT_YEALINK is not set
++# CONFIG_INPUT_CM109 is not set
++CONFIG_INPUT_UINPUT=y
++# CONFIG_INPUT_PCF8574 is not set
++# CONFIG_INPUT_DA7280_HAPTICS is not set
++# CONFIG_INPUT_ADXL34X is not set
++# CONFIG_INPUT_IMS_PCU is not set
++# CONFIG_INPUT_IQS269A is not set
++# CONFIG_INPUT_IQS626A is not set
++# CONFIG_INPUT_CMA3000 is not set
++# CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set
++# CONFIG_INPUT_DRV2665_HAPTICS is not set
++# CONFIG_INPUT_DRV2667_HAPTICS is not set
++# CONFIG_RMI4_CORE is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=y
++CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
++CONFIG_SERIO_I8042=y
++CONFIG_SERIO_SERPORT=y
++# CONFIG_SERIO_CT82C710 is not set
++# CONFIG_SERIO_PCIPS2 is not set
++CONFIG_SERIO_LIBPS2=y
++# CONFIG_SERIO_RAW is not set
++# CONFIG_SERIO_ALTERA_PS2 is not set
++# CONFIG_SERIO_PS2MULT is not set
++# CONFIG_SERIO_ARC_PS2 is not set
++# CONFIG_USERIO is not set
++# CONFIG_GAMEPORT is not set
++# end of Hardware I/O ports
++# end of Input device support
++
++#
++# Character devices
++#
++CONFIG_TTY=y
++CONFIG_VT=y
++CONFIG_CONSOLE_TRANSLATIONS=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++CONFIG_VT_HW_CONSOLE_BINDING=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++# CONFIG_LDISC_AUTOLOAD is not set
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_EARLYCON=y
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_PNP=y
++# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
++# CONFIG_SERIAL_8250_FINTEK is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_DMA=y
++CONFIG_SERIAL_8250_PCI=y
++CONFIG_SERIAL_8250_EXAR=y
++CONFIG_SERIAL_8250_NR_UARTS=4
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++# CONFIG_SERIAL_8250_MANY_PORTS is not set
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++# CONFIG_SERIAL_8250_RSA is not set
++# CONFIG_SERIAL_8250_DW is not set
++# CONFIG_SERIAL_8250_RT288X is not set
++# CONFIG_SERIAL_8250_LPSS is not set
++# CONFIG_SERIAL_8250_MID is not set
++
++#
++# Non-8250 serial port support
++#
++# CONFIG_SERIAL_UARTLITE is not set
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_JSM is not set
++CONFIG_SERIAL_LANTIQ=y
++# CONFIG_SERIAL_LANTIQ_CONSOLE is not set
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_SC16IS7XX is not set
++# CONFIG_SERIAL_BCM63XX is not set
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++# CONFIG_SERIAL_ARC is not set
++# CONFIG_SERIAL_RP2 is not set
++# CONFIG_SERIAL_FSL_LPUART is not set
++# CONFIG_SERIAL_FSL_LINFLEXUART is not set
++# CONFIG_SERIAL_SPRD is not set
++# end of Serial drivers
++
++# CONFIG_SERIAL_NONSTANDARD is not set
++# CONFIG_N_GSM is not set
++# CONFIG_NOZOMI is not set
++# CONFIG_NULL_TTY is not set
++# CONFIG_SERIAL_DEV_BUS is not set
++# CONFIG_TTY_PRINTK is not set
++# CONFIG_VIRTIO_CONSOLE is not set
++# CONFIG_IPMI_HANDLER is not set
++# CONFIG_IPMB_DEVICE_INTERFACE is not set
++CONFIG_HW_RANDOM=y
++# CONFIG_HW_RANDOM_TIMERIOMEM is not set
++# CONFIG_HW_RANDOM_INTEL is not set
++CONFIG_HW_RANDOM_AMD=y
++# CONFIG_HW_RANDOM_BA431 is not set
++# CONFIG_HW_RANDOM_VIA is not set
++# CONFIG_HW_RANDOM_XIPHERA is not set
++# CONFIG_APPLICOM is not set
++# CONFIG_MWAVE is not set
++CONFIG_DEVMEM=y
++CONFIG_NVRAM=y
++CONFIG_DEVPORT=y
++# CONFIG_HPET is not set
++# CONFIG_HANGCHECK_TIMER is not set
++# CONFIG_TCG_TPM is not set
++# CONFIG_TELCLOCK is not set
++# CONFIG_XILLYBUS is not set
++# CONFIG_XILLYUSB is not set
++# CONFIG_RANDOM_TRUST_CPU is not set
++# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
++# end of Character devices
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++CONFIG_ACPI_I2C_OPREGION=y
++CONFIG_I2C_BOARDINFO=y
++CONFIG_I2C_COMPAT=y
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++
++#
++# Multiplexer I2C Chip support
++#
++# CONFIG_I2C_MUX_LTC4306 is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_REG is not set
++# CONFIG_I2C_MUX_MLXCPLD is not set
++# end of Multiplexer I2C Chip support
++
++CONFIG_I2C_HELPER_AUTO=y
++CONFIG_I2C_ALGOBIT=y
++
++#
++# I2C Hardware Bus support
++#
++
++#
++# PC SMBus host controller drivers
++#
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_AMD_MP2 is not set
++# CONFIG_I2C_I801 is not set
++# CONFIG_I2C_ISCH is not set
++# CONFIG_I2C_ISMT is not set
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_I2C_NFORCE2 is not set
++# CONFIG_I2C_NVIDIA_GPU is not set
++# CONFIG_I2C_SIS5595 is not set
++# CONFIG_I2C_SIS630 is not set
++# CONFIG_I2C_SIS96X is not set
++# CONFIG_I2C_VIA is not set
++# CONFIG_I2C_VIAPRO is not set
++
++#
++# ACPI drivers
++#
++# CONFIG_I2C_SCMI is not set
++
++#
++# I2C system bus drivers (mostly embedded / system-on-chip)
++#
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_DESIGNWARE_PCI is not set
++# CONFIG_I2C_EMEV2 is not set
++# CONFIG_I2C_OCORES is not set
++# CONFIG_I2C_PCA_PLATFORM is not set
++# CONFIG_I2C_SIMTEC is not set
++# CONFIG_I2C_XILINX is not set
++
++#
++# External I2C/SMBus adapter drivers
++#
++# CONFIG_I2C_DIOLAN_U2C is not set
++# CONFIG_I2C_CP2615 is not set
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_TINY_USB is not set
++
++#
++# Other I2C/SMBus bus drivers
++#
++# CONFIG_I2C_MLXCPLD is not set
++# CONFIG_I2C_VIRTIO is not set
++# end of I2C Hardware Bus support
++
++# CONFIG_I2C_STUB is not set
++CONFIG_I2C_SLAVE=y
++CONFIG_I2C_SLAVE_EEPROM=y
++# CONFIG_I2C_SLAVE_TESTUNIT is not set
++CONFIG_I2C_DEBUG_CORE=y
++CONFIG_I2C_DEBUG_ALGO=y
++CONFIG_I2C_DEBUG_BUS=y
++# end of I2C support
++
++# CONFIG_I3C is not set
++# CONFIG_SPI is not set
++# CONFIG_SPMI is not set
++# CONFIG_HSI is not set
++# CONFIG_PPS is not set
++
++#
++# PTP clock support
++#
++# CONFIG_PTP_1588_CLOCK is not set
++CONFIG_PTP_1588_CLOCK_OPTIONAL=y
++
++#
++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
++#
++# end of PTP clock support
++
++# CONFIG_PINCTRL is not set
++# CONFIG_GPIOLIB is not set
++# CONFIG_W1 is not set
++# CONFIG_POWER_RESET is not set
++CONFIG_POWER_SUPPLY=y
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++# CONFIG_POWER_SUPPLY_HWMON is not set
++# CONFIG_PDA_POWER is not set
++# CONFIG_TEST_POWER is not set
++# CONFIG_CHARGER_ADP5061 is not set
++# CONFIG_BATTERY_CW2015 is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_CHARGER_SBS is not set
++# CONFIG_BATTERY_BQ27XXX is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_LTC4162L is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_BATTERY_GAUGE_LTC2941 is not set
++# CONFIG_BATTERY_GOLDFISH is not set
++# CONFIG_BATTERY_RT5033 is not set
++# CONFIG_CHARGER_BD99954 is not set
++CONFIG_HWMON=y
++# CONFIG_HWMON_DEBUG_CHIP is not set
++
++#
++# Native drivers
++#
++# CONFIG_SENSORS_ABITUGURU is not set
++# CONFIG_SENSORS_ABITUGURU3 is not set
++# CONFIG_SENSORS_AD7414 is not set
++# CONFIG_SENSORS_AD7418 is not set
++# CONFIG_SENSORS_ADM1021 is not set
++# CONFIG_SENSORS_ADM1025 is not set
++# CONFIG_SENSORS_ADM1026 is not set
++# CONFIG_SENSORS_ADM1029 is not set
++# CONFIG_SENSORS_ADM1031 is not set
++# CONFIG_SENSORS_ADM1177 is not set
++# CONFIG_SENSORS_ADM9240 is not set
++# CONFIG_SENSORS_ADT7410 is not set
++# CONFIG_SENSORS_ADT7411 is not set
++# CONFIG_SENSORS_ADT7462 is not set
++# CONFIG_SENSORS_ADT7470 is not set
++# CONFIG_SENSORS_ADT7475 is not set
++# CONFIG_SENSORS_AHT10 is not set
++# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
++# CONFIG_SENSORS_AS370 is not set
++# CONFIG_SENSORS_ASC7621 is not set
++# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
++CONFIG_SENSORS_K8TEMP=y
++CONFIG_SENSORS_K10TEMP=y
++CONFIG_SENSORS_FAM15H_POWER=y
++# CONFIG_SENSORS_APPLESMC is not set
++# CONFIG_SENSORS_ASB100 is not set
++# CONFIG_SENSORS_ASPEED is not set
++# CONFIG_SENSORS_ATXP1 is not set
++# CONFIG_SENSORS_CORSAIR_CPRO is not set
++# CONFIG_SENSORS_CORSAIR_PSU is not set
++# CONFIG_SENSORS_DRIVETEMP is not set
++# CONFIG_SENSORS_DS620 is not set
++# CONFIG_SENSORS_DS1621 is not set
++# CONFIG_SENSORS_DELL_SMM is not set
++# CONFIG_SENSORS_I5K_AMB is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_F71882FG is not set
++# CONFIG_SENSORS_F75375S is not set
++# CONFIG_SENSORS_FSCHMD is not set
++# CONFIG_SENSORS_GL518SM is not set
++# CONFIG_SENSORS_GL520SM is not set
++# CONFIG_SENSORS_G760A is not set
++# CONFIG_SENSORS_G762 is not set
++# CONFIG_SENSORS_HIH6130 is not set
++# CONFIG_SENSORS_I5500 is not set
++# CONFIG_SENSORS_CORETEMP is not set
++# CONFIG_SENSORS_IT87 is not set
++# CONFIG_SENSORS_JC42 is not set
++# CONFIG_SENSORS_POWR1220 is not set
++# CONFIG_SENSORS_LINEAGE is not set
++# CONFIG_SENSORS_LTC2945 is not set
++# CONFIG_SENSORS_LTC2947_I2C is not set
++# CONFIG_SENSORS_LTC2990 is not set
++# CONFIG_SENSORS_LTC4151 is not set
++# CONFIG_SENSORS_LTC4215 is not set
++# CONFIG_SENSORS_LTC4222 is not set
++# CONFIG_SENSORS_LTC4245 is not set
++# CONFIG_SENSORS_LTC4260 is not set
++# CONFIG_SENSORS_LTC4261 is not set
++# CONFIG_SENSORS_MAX127 is not set
++# CONFIG_SENSORS_MAX16065 is not set
++# CONFIG_SENSORS_MAX1619 is not set
++# CONFIG_SENSORS_MAX1668 is not set
++# CONFIG_SENSORS_MAX197 is not set
++# CONFIG_SENSORS_MAX31730 is not set
++# CONFIG_SENSORS_MAX6621 is not set
++# CONFIG_SENSORS_MAX6639 is not set
++# CONFIG_SENSORS_MAX6642 is not set
++# CONFIG_SENSORS_MAX6650 is not set
++# CONFIG_SENSORS_MAX6697 is not set
++# CONFIG_SENSORS_MAX31790 is not set
++# CONFIG_SENSORS_MCP3021 is not set
++# CONFIG_SENSORS_TC654 is not set
++# CONFIG_SENSORS_TPS23861 is not set
++# CONFIG_SENSORS_MR75203 is not set
++# CONFIG_SENSORS_LM63 is not set
++# CONFIG_SENSORS_LM73 is not set
++# CONFIG_SENSORS_LM75 is not set
++# CONFIG_SENSORS_LM77 is not set
++# CONFIG_SENSORS_LM78 is not set
++# CONFIG_SENSORS_LM80 is not set
++# CONFIG_SENSORS_LM83 is not set
++# CONFIG_SENSORS_LM85 is not set
++# CONFIG_SENSORS_LM87 is not set
++# CONFIG_SENSORS_LM90 is not set
++# CONFIG_SENSORS_LM92 is not set
++# CONFIG_SENSORS_LM93 is not set
++# CONFIG_SENSORS_LM95234 is not set
++# CONFIG_SENSORS_LM95241 is not set
++# CONFIG_SENSORS_LM95245 is not set
++# CONFIG_SENSORS_PC87360 is not set
++# CONFIG_SENSORS_PC87427 is not set
++# CONFIG_SENSORS_NTC_THERMISTOR is not set
++# CONFIG_SENSORS_NCT6683 is not set
++# CONFIG_SENSORS_NCT6775 is not set
++# CONFIG_SENSORS_NCT7802 is not set
++# CONFIG_SENSORS_NPCM7XX is not set
++# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
++# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_PMBUS is not set
++# CONFIG_SENSORS_SBTSI is not set
++# CONFIG_SENSORS_SBRMI is not set
++# CONFIG_SENSORS_SHT21 is not set
++# CONFIG_SENSORS_SHT3x is not set
++# CONFIG_SENSORS_SHT4x is not set
++# CONFIG_SENSORS_SHTC1 is not set
++# CONFIG_SENSORS_SIS5595 is not set
++# CONFIG_SENSORS_DME1737 is not set
++# CONFIG_SENSORS_EMC1403 is not set
++# CONFIG_SENSORS_EMC2103 is not set
++# CONFIG_SENSORS_EMC6W201 is not set
++# CONFIG_SENSORS_SMSC47M1 is not set
++# CONFIG_SENSORS_SMSC47M192 is not set
++# CONFIG_SENSORS_SMSC47B397 is not set
++# CONFIG_SENSORS_STTS751 is not set
++# CONFIG_SENSORS_SMM665 is not set
++# CONFIG_SENSORS_ADC128D818 is not set
++# CONFIG_SENSORS_ADS7828 is not set
++# CONFIG_SENSORS_AMC6821 is not set
++# CONFIG_SENSORS_INA209 is not set
++# CONFIG_SENSORS_INA2XX is not set
++# CONFIG_SENSORS_INA3221 is not set
++# CONFIG_SENSORS_TC74 is not set
++# CONFIG_SENSORS_THMC50 is not set
++# CONFIG_SENSORS_TMP102 is not set
++# CONFIG_SENSORS_TMP103 is not set
++# CONFIG_SENSORS_TMP108 is not set
++# CONFIG_SENSORS_TMP401 is not set
++# CONFIG_SENSORS_TMP421 is not set
++# CONFIG_SENSORS_TMP513 is not set
++# CONFIG_SENSORS_VIA_CPUTEMP is not set
++# CONFIG_SENSORS_VIA686A is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_SENSORS_VT8231 is not set
++# CONFIG_SENSORS_W83773G is not set
++# CONFIG_SENSORS_W83781D is not set
++# CONFIG_SENSORS_W83791D is not set
++# CONFIG_SENSORS_W83792D is not set
++# CONFIG_SENSORS_W83793 is not set
++# CONFIG_SENSORS_W83795 is not set
++# CONFIG_SENSORS_W83L785TS is not set
++# CONFIG_SENSORS_W83L786NG is not set
++# CONFIG_SENSORS_W83627HF is not set
++# CONFIG_SENSORS_W83627EHF is not set
++
++#
++# ACPI drivers
++#
++# CONFIG_SENSORS_ACPI_POWER is not set
++# CONFIG_SENSORS_ATK0110 is not set
++CONFIG_THERMAL=y
++# CONFIG_THERMAL_NETLINK is not set
++# CONFIG_THERMAL_STATISTICS is not set
++CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
++# CONFIG_THERMAL_HWMON is not set
++# CONFIG_THERMAL_WRITABLE_TRIPS is not set
++CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
++# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
++# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
++# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
++CONFIG_THERMAL_GOV_STEP_WISE=y
++# CONFIG_THERMAL_GOV_BANG_BANG is not set
++# CONFIG_THERMAL_GOV_USER_SPACE is not set
++# CONFIG_THERMAL_EMULATION is not set
++
++#
++# Intel thermal drivers
++#
++# CONFIG_INTEL_SOC_DTS_THERMAL is not set
++
++#
++# ACPI INT340X thermal drivers
++#
++# CONFIG_INT340X_THERMAL is not set
++# end of ACPI INT340X thermal drivers
++
++# CONFIG_INTEL_PCH_THERMAL is not set
++# CONFIG_INTEL_TCC_COOLING is not set
++# CONFIG_INTEL_MENLOW is not set
++# end of Intel thermal drivers
++
++# CONFIG_WATCHDOG is not set
++CONFIG_SSB_POSSIBLE=y
++# CONFIG_SSB is not set
++CONFIG_BCMA_POSSIBLE=y
++# CONFIG_BCMA is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MFD_AS3711 is not set
++# CONFIG_PMIC_ADP5520 is not set
++# CONFIG_MFD_BCM590XX is not set
++# CONFIG_MFD_BD9571MWV is not set
++# CONFIG_MFD_AXP20X_I2C is not set
++# CONFIG_MFD_MADERA is not set
++# CONFIG_PMIC_DA903X is not set
++# CONFIG_MFD_DA9052_I2C is not set
++# CONFIG_MFD_DA9055 is not set
++# CONFIG_MFD_DA9062 is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_DA9150 is not set
++# CONFIG_MFD_DLN2 is not set
++# CONFIG_MFD_MC13XXX_I2C is not set
++# CONFIG_MFD_MP2629 is not set
++# CONFIG_HTC_PASIC3 is not set
++# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set
++# CONFIG_LPC_ICH is not set
++# CONFIG_LPC_SCH is not set
++# CONFIG_MFD_INTEL_LPSS_ACPI is not set
++# CONFIG_MFD_INTEL_LPSS_PCI is not set
++# CONFIG_MFD_INTEL_PMT is not set
++# CONFIG_MFD_IQS62X is not set
++# CONFIG_MFD_JANZ_CMODIO is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_88PM800 is not set
++# CONFIG_MFD_88PM805 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_MFD_MAX14577 is not set
++# CONFIG_MFD_MAX77693 is not set
++# CONFIG_MFD_MAX77843 is not set
++# CONFIG_MFD_MAX8907 is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_MAX8997 is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_MT6360 is not set
++# CONFIG_MFD_MT6397 is not set
++# CONFIG_MFD_MENF21BMC is not set
++# CONFIG_MFD_VIPERBOARD is not set
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_PCF50633 is not set
++# CONFIG_MFD_RDC321X is not set
++# CONFIG_MFD_RT4831 is not set
++# CONFIG_MFD_RT5033 is not set
++# CONFIG_MFD_RC5T583 is not set
++# CONFIG_MFD_SI476X_CORE is not set
++# CONFIG_MFD_SM501 is not set
++# CONFIG_MFD_SKY81452 is not set
++# CONFIG_MFD_SYSCON is not set
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++# CONFIG_MFD_LP3943 is not set
++# CONFIG_MFD_LP8788 is not set
++# CONFIG_MFD_TI_LMU is not set
++# CONFIG_MFD_PALMAS is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_MFD_TPS65086 is not set
++# CONFIG_MFD_TPS65090 is not set
++# CONFIG_MFD_TI_LP873X is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TPS65912_I2C is not set
++# CONFIG_MFD_TPS80031 is not set
++# CONFIG_TWL4030_CORE is not set
++# CONFIG_TWL6040_CORE is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_TQMX86 is not set
++# CONFIG_MFD_VX855 is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_MFD_ATC260X_I2C is not set
++# end of Multifunction device drivers
++
++# CONFIG_REGULATOR is not set
++# CONFIG_RC_CORE is not set
++CONFIG_MEDIA_CEC_SUPPORT=y
++# CONFIG_CEC_CH7322 is not set
++# CONFIG_CEC_SECO is not set
++# CONFIG_USB_PULSE8_CEC is not set
++# CONFIG_USB_RAINSHADOW_CEC is not set
++# CONFIG_MEDIA_SUPPORT is not set
++
++#
++# Graphics support
++#
++CONFIG_AGP=y
++CONFIG_AGP_AMD64=y
++# CONFIG_AGP_INTEL is not set
++# CONFIG_AGP_SIS is not set
++# CONFIG_AGP_VIA is not set
++CONFIG_VGA_ARB=y
++CONFIG_VGA_ARB_MAX_GPUS=2
++# CONFIG_VGA_SWITCHEROO is not set
++CONFIG_DRM=y
++# CONFIG_DRM_DP_AUX_CHARDEV is not set
++# CONFIG_DRM_DEBUG_MM is not set
++# CONFIG_DRM_DEBUG_SELFTEST is not set
++CONFIG_DRM_KMS_HELPER=y
++# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
++CONFIG_DRM_FBDEV_EMULATION=y
++CONFIG_DRM_FBDEV_OVERALLOC=100
++# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++# CONFIG_DRM_DP_CEC is not set
++CONFIG_DRM_TTM=y
++CONFIG_DRM_TTM_HELPER=y
++CONFIG_DRM_SCHED=y
++
++#
++# I2C encoder or helper chips
++#
++# CONFIG_DRM_I2C_CH7006 is not set
++# CONFIG_DRM_I2C_SIL164 is not set
++# CONFIG_DRM_I2C_NXP_TDA998X is not set
++# CONFIG_DRM_I2C_NXP_TDA9950 is not set
++# end of I2C encoder or helper chips
++
++#
++# ARM devices
++#
++# end of ARM devices
++
++# CONFIG_DRM_RADEON is not set
++CONFIG_DRM_AMDGPU=y
++# CONFIG_DRM_AMDGPU_SI is not set
++CONFIG_DRM_AMDGPU_CIK=y
++CONFIG_DRM_AMDGPU_USERPTR=y
++
++#
++# ACP (Audio CoProcessor) Configuration
++#
++# CONFIG_DRM_AMD_ACP is not set
++# end of ACP (Audio CoProcessor) Configuration
++
++#
++# Display Engine Configuration
++#
++CONFIG_DRM_AMD_DC=y
++CONFIG_DRM_AMD_DC_DCN=y
++CONFIG_DRM_AMD_DC_HDCP=y
++CONFIG_DRM_AMD_SECURE_DISPLAY=y
++# end of Display Engine Configuration
++
++# CONFIG_HSA_AMD is not set
++# CONFIG_DRM_NOUVEAU is not set
++# CONFIG_DRM_I915 is not set
++# CONFIG_DRM_VGEM is not set
++# CONFIG_DRM_VKMS is not set
++# CONFIG_DRM_VMWGFX is not set
++# CONFIG_DRM_GMA500 is not set
++# CONFIG_DRM_UDL is not set
++# CONFIG_DRM_AST is not set
++# CONFIG_DRM_MGAG200 is not set
++# CONFIG_DRM_QXL is not set
++CONFIG_DRM_PANEL=y
++
++#
++# Display Panels
++#
++# end of Display Panels
++
++CONFIG_DRM_BRIDGE=y
++CONFIG_DRM_PANEL_BRIDGE=y
++
++#
++# Display Interface Bridges
++#
++# CONFIG_DRM_ANALOGIX_ANX78XX is not set
++# end of Display Interface Bridges
++
++# CONFIG_DRM_ETNAVIV is not set
++# CONFIG_DRM_BOCHS is not set
++# CONFIG_DRM_CIRRUS_QEMU is not set
++# CONFIG_DRM_GM12U320 is not set
++# CONFIG_DRM_SIMPLEDRM is not set
++# CONFIG_DRM_VBOXVIDEO is not set
++# CONFIG_DRM_GUD is not set
++# CONFIG_DRM_LEGACY is not set
++CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
++
++#
++# Frame buffer Devices
++#
++CONFIG_FB_CMDLINE=y
++CONFIG_FB_NOTIFY=y
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++CONFIG_FB_BOOT_VESA_SUPPORT=y
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++CONFIG_FB_SYS_FILLRECT=y
++CONFIG_FB_SYS_COPYAREA=y
++CONFIG_FB_SYS_IMAGEBLIT=y
++# CONFIG_FB_FOREIGN_ENDIAN is not set
++CONFIG_FB_SYS_FOPS=y
++CONFIG_FB_DEFERRED_IO=y
++CONFIG_FB_MODE_HELPERS=y
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_CIRRUS is not set
++# CONFIG_FB_PM2 is not set
++# CONFIG_FB_CYBER2000 is not set
++# CONFIG_FB_ARC is not set
++# CONFIG_FB_ASILIANT is not set
++# CONFIG_FB_IMSTT is not set
++# CONFIG_FB_VGA16 is not set
++# CONFIG_FB_UVESA is not set
++CONFIG_FB_VESA=y
++# CONFIG_FB_N411 is not set
++# CONFIG_FB_HGA is not set
++# CONFIG_FB_OPENCORES is not set
++# CONFIG_FB_S1D13XXX is not set
++# CONFIG_FB_NVIDIA is not set
++# CONFIG_FB_RIVA is not set
++# CONFIG_FB_I740 is not set
++# CONFIG_FB_LE80578 is not set
++# CONFIG_FB_MATROX is not set
++# CONFIG_FB_RADEON is not set
++# CONFIG_FB_ATY128 is not set
++# CONFIG_FB_ATY is not set
++# CONFIG_FB_S3 is not set
++# CONFIG_FB_SAVAGE is not set
++# CONFIG_FB_SIS is not set
++# CONFIG_FB_NEOMAGIC is not set
++# CONFIG_FB_KYRO is not set
++# CONFIG_FB_3DFX is not set
++# CONFIG_FB_VOODOO1 is not set
++# CONFIG_FB_VT8623 is not set
++# CONFIG_FB_TRIDENT is not set
++# CONFIG_FB_ARK is not set
++# CONFIG_FB_PM3 is not set
++# CONFIG_FB_CARMINE is not set
++# CONFIG_FB_SMSCUFX is not set
++# CONFIG_FB_UDL is not set
++# CONFIG_FB_IBM_GXT4500 is not set
++# CONFIG_FB_VIRTUAL is not set
++# CONFIG_FB_METRONOME is not set
++# CONFIG_FB_MB862XX is not set
++CONFIG_FB_SIMPLE=y
++# CONFIG_FB_SM712 is not set
++# end of Frame buffer Devices
++
++#
++# Backlight & LCD device support
++#
++# CONFIG_LCD_CLASS_DEVICE is not set
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++# CONFIG_BACKLIGHT_APPLE is not set
++# CONFIG_BACKLIGHT_QCOM_WLED is not set
++# CONFIG_BACKLIGHT_SAHARA is not set
++# CONFIG_BACKLIGHT_ADP8860 is not set
++# CONFIG_BACKLIGHT_ADP8870 is not set
++# CONFIG_BACKLIGHT_LM3639 is not set
++# CONFIG_BACKLIGHT_LV5207LP is not set
++# CONFIG_BACKLIGHT_BD6107 is not set
++# CONFIG_BACKLIGHT_ARCXCNN is not set
++# end of Backlight & LCD device support
++
++CONFIG_HDMI=y
++
++#
++# Console display driver support
++#
++CONFIG_VGA_CONSOLE=y
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_DUMMY_CONSOLE_COLUMNS=80
++CONFIG_DUMMY_CONSOLE_ROWS=25
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
++# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
++# end of Console display driver support
++
++# CONFIG_LOGO is not set
++# end of Graphics support
++
++CONFIG_SOUND=y
++CONFIG_SOUND_OSS_CORE=y
++CONFIG_SOUND_OSS_CORE_PRECLAIM=y
++CONFIG_SND=y
++CONFIG_SND_TIMER=y
++CONFIG_SND_PCM=y
++CONFIG_SND_HWDEP=y
++CONFIG_SND_SEQ_DEVICE=y
++CONFIG_SND_JACK=y
++CONFIG_SND_JACK_INPUT_DEV=y
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++CONFIG_SND_PCM_TIMER=y
++CONFIG_SND_HRTIMER=y
++CONFIG_SND_DYNAMIC_MINORS=y
++CONFIG_SND_MAX_CARDS=16
++CONFIG_SND_SUPPORT_OLD_API=y
++CONFIG_SND_PROC_FS=y
++# CONFIG_SND_VERBOSE_PROCFS is not set
++# CONFIG_SND_VERBOSE_PRINTK is not set
++# CONFIG_SND_DEBUG is not set
++CONFIG_SND_VMASTER=y
++CONFIG_SND_DMA_SGBUF=y
++CONFIG_SND_CTL_LED=y
++CONFIG_SND_SEQUENCER=y
++# CONFIG_SND_SEQ_DUMMY is not set
++# CONFIG_SND_SEQUENCER_OSS is not set
++CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
++CONFIG_SND_DRIVERS=y
++# CONFIG_SND_DUMMY is not set
++# CONFIG_SND_ALOOP is not set
++# CONFIG_SND_VIRMIDI is not set
++# CONFIG_SND_MTPAV is not set
++# CONFIG_SND_SERIAL_U16550 is not set
++# CONFIG_SND_MPU401 is not set
++CONFIG_SND_PCI=y
++# CONFIG_SND_AD1889 is not set
++# CONFIG_SND_ALS300 is not set
++# CONFIG_SND_ALS4000 is not set
++# CONFIG_SND_ALI5451 is not set
++# CONFIG_SND_ASIHPI is not set
++# CONFIG_SND_ATIIXP is not set
++# CONFIG_SND_ATIIXP_MODEM is not set
++# CONFIG_SND_AU8810 is not set
++# CONFIG_SND_AU8820 is not set
++# CONFIG_SND_AU8830 is not set
++# CONFIG_SND_AW2 is not set
++# CONFIG_SND_AZT3328 is not set
++# CONFIG_SND_BT87X is not set
++# CONFIG_SND_CA0106 is not set
++# CONFIG_SND_CMIPCI is not set
++# CONFIG_SND_OXYGEN is not set
++# CONFIG_SND_CS4281 is not set
++# CONFIG_SND_CS46XX is not set
++# CONFIG_SND_CTXFI is not set
++# CONFIG_SND_DARLA20 is not set
++# CONFIG_SND_GINA20 is not set
++# CONFIG_SND_LAYLA20 is not set
++# CONFIG_SND_DARLA24 is not set
++# CONFIG_SND_GINA24 is not set
++# CONFIG_SND_LAYLA24 is not set
++# CONFIG_SND_MONA is not set
++# CONFIG_SND_MIA is not set
++# CONFIG_SND_ECHO3G is not set
++# CONFIG_SND_INDIGO is not set
++# CONFIG_SND_INDIGOIO is not set
++# CONFIG_SND_INDIGODJ is not set
++# CONFIG_SND_INDIGOIOX is not set
++# CONFIG_SND_INDIGODJX is not set
++# CONFIG_SND_EMU10K1 is not set
++# CONFIG_SND_EMU10K1X is not set
++# CONFIG_SND_ENS1370 is not set
++# CONFIG_SND_ENS1371 is not set
++# CONFIG_SND_ES1938 is not set
++# CONFIG_SND_ES1968 is not set
++# CONFIG_SND_FM801 is not set
++# CONFIG_SND_HDSP is not set
++# CONFIG_SND_HDSPM is not set
++# CONFIG_SND_ICE1712 is not set
++# CONFIG_SND_ICE1724 is not set
++# CONFIG_SND_INTEL8X0 is not set
++# CONFIG_SND_INTEL8X0M is not set
++# CONFIG_SND_KORG1212 is not set
++# CONFIG_SND_LOLA is not set
++# CONFIG_SND_LX6464ES is not set
++# CONFIG_SND_MAESTRO3 is not set
++# CONFIG_SND_MIXART is not set
++# CONFIG_SND_NM256 is not set
++# CONFIG_SND_PCXHR is not set
++# CONFIG_SND_RIPTIDE is not set
++# CONFIG_SND_RME32 is not set
++# CONFIG_SND_RME96 is not set
++# CONFIG_SND_RME9652 is not set
++# CONFIG_SND_SE6X is not set
++# CONFIG_SND_SONICVIBES is not set
++# CONFIG_SND_TRIDENT is not set
++# CONFIG_SND_VIA82XX is not set
++# CONFIG_SND_VIA82XX_MODEM is not set
++# CONFIG_SND_VIRTUOSO is not set
++# CONFIG_SND_VX222 is not set
++# CONFIG_SND_YMFPCI is not set
++
++#
++# HD-Audio
++#
++CONFIG_SND_HDA=y
++CONFIG_SND_HDA_GENERIC_LEDS=y
++CONFIG_SND_HDA_INTEL=y
++CONFIG_SND_HDA_HWDEP=y
++CONFIG_SND_HDA_RECONFIG=y
++CONFIG_SND_HDA_INPUT_BEEP=y
++CONFIG_SND_HDA_INPUT_BEEP_MODE=1
++CONFIG_SND_HDA_PATCH_LOADER=y
++CONFIG_SND_HDA_CODEC_REALTEK=y
++CONFIG_SND_HDA_CODEC_ANALOG=y
++CONFIG_SND_HDA_CODEC_SIGMATEL=y
++CONFIG_SND_HDA_CODEC_VIA=y
++CONFIG_SND_HDA_CODEC_HDMI=y
++CONFIG_SND_HDA_CODEC_CIRRUS=y
++# CONFIG_SND_HDA_CODEC_CS8409 is not set
++CONFIG_SND_HDA_CODEC_CONEXANT=y
++CONFIG_SND_HDA_CODEC_CA0110=y
++CONFIG_SND_HDA_CODEC_CA0132=y
++CONFIG_SND_HDA_CODEC_CA0132_DSP=y
++CONFIG_SND_HDA_CODEC_CMEDIA=y
++CONFIG_SND_HDA_CODEC_SI3054=y
++CONFIG_SND_HDA_GENERIC=y
++# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
++# end of HD-Audio
++
++CONFIG_SND_HDA_CORE=y
++CONFIG_SND_HDA_DSP_LOADER=y
++CONFIG_SND_HDA_COMPONENT=y
++CONFIG_SND_HDA_PREALLOC_SIZE=0
++CONFIG_SND_INTEL_NHLT=y
++CONFIG_SND_INTEL_DSP_CONFIG=y
++CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y
++# CONFIG_SND_USB is not set
++# CONFIG_SND_SOC is not set
++CONFIG_SND_X86=y
++
++#
++# HID support
++#
++CONFIG_HID=y
++# CONFIG_HID_BATTERY_STRENGTH is not set
++CONFIG_HIDRAW=y
++CONFIG_UHID=y
++CONFIG_HID_GENERIC=y
++
++#
++# Special HID drivers
++#
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_ACCUTOUCH is not set
++# CONFIG_HID_ACRUX is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_APPLEIR is not set
++# CONFIG_HID_ASUS is not set
++# CONFIG_HID_AUREAL is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_BETOP_FF is not set
++# CONFIG_HID_BIGBEN_FF is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CORSAIR is not set
++# CONFIG_HID_COUGAR is not set
++# CONFIG_HID_MACALLY is not set
++# CONFIG_HID_PRODIKEYS is not set
++# CONFIG_HID_CMEDIA is not set
++# CONFIG_HID_CREATIVE_SB0540 is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_DRAGONRISE is not set
++# CONFIG_HID_EMS_FF is not set
++# CONFIG_HID_ELAN is not set
++# CONFIG_HID_ELECOM is not set
++# CONFIG_HID_ELO is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_FT260 is not set
++# CONFIG_HID_GEMBIRD is not set
++# CONFIG_HID_GFRM is not set
++# CONFIG_HID_GLORIOUS is not set
++# CONFIG_HID_HOLTEK is not set
++# CONFIG_HID_VIVALDI is not set
++# CONFIG_HID_GT683R is not set
++# CONFIG_HID_KEYTOUCH is not set
++# CONFIG_HID_KYE is not set
++# CONFIG_HID_UCLOGIC is not set
++# CONFIG_HID_WALTOP is not set
++# CONFIG_HID_VIEWSONIC is not set
++# CONFIG_HID_GYRATION is not set
++# CONFIG_HID_ICADE is not set
++# CONFIG_HID_ITE is not set
++# CONFIG_HID_JABRA is not set
++# CONFIG_HID_TWINHAN is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LCPOWER is not set
++# CONFIG_HID_LED is not set
++# CONFIG_HID_LENOVO is not set
++CONFIG_HID_LOGITECH=y
++CONFIG_HID_LOGITECH_DJ=y
++CONFIG_HID_LOGITECH_HIDPP=y
++# CONFIG_LOGITECH_FF is not set
++# CONFIG_LOGIRUMBLEPAD2_FF is not set
++# CONFIG_LOGIG940_FF is not set
++# CONFIG_LOGIWHEELS_FF is not set
++# CONFIG_HID_MAGICMOUSE is not set
++# CONFIG_HID_MALTRON is not set
++# CONFIG_HID_MAYFLASH is not set
++# CONFIG_HID_REDRAGON is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++# CONFIG_HID_MULTITOUCH is not set
++# CONFIG_HID_NTI is not set
++# CONFIG_HID_NTRIG is not set
++# CONFIG_HID_ORTEK is not set
++# CONFIG_HID_PANTHERLORD is not set
++# CONFIG_HID_PENMOUNT is not set
++# CONFIG_HID_PETALYNX is not set
++# CONFIG_HID_PICOLCD is not set
++# CONFIG_HID_PLANTRONICS is not set
++CONFIG_HID_PLAYSTATION=y
++CONFIG_PLAYSTATION_FF=y
++# CONFIG_HID_PRIMAX is not set
++# CONFIG_HID_RETRODE is not set
++# CONFIG_HID_ROCCAT is not set
++# CONFIG_HID_SAITEK is not set
++# CONFIG_HID_SAMSUNG is not set
++# CONFIG_HID_SEMITEK is not set
++CONFIG_HID_SONY=y
++CONFIG_SONY_FF=y
++# CONFIG_HID_SPEEDLINK is not set
++# CONFIG_HID_STEAM is not set
++# CONFIG_HID_STEELSERIES is not set
++# CONFIG_HID_SUNPLUS is not set
++# CONFIG_HID_RMI is not set
++# CONFIG_HID_GREENASIA is not set
++# CONFIG_HID_SMARTJOYPLUS is not set
++# CONFIG_HID_TIVO is not set
++# CONFIG_HID_TOPSEED is not set
++# CONFIG_HID_THINGM is not set
++# CONFIG_HID_THRUSTMASTER is not set
++# CONFIG_HID_UDRAW_PS3 is not set
++# CONFIG_HID_U2FZERO is not set
++# CONFIG_HID_WACOM is not set
++CONFIG_HID_WIIMOTE=y
++# CONFIG_HID_XINMO is not set
++# CONFIG_HID_ZEROPLUS is not set
++# CONFIG_HID_ZYDACRON is not set
++# CONFIG_HID_SENSOR_HUB is not set
++# CONFIG_HID_ALPS is not set
++# end of Special HID drivers
++
++#
++# USB HID support
++#
++CONFIG_USB_HID=y
++# CONFIG_HID_PID is not set
++CONFIG_USB_HIDDEV=y
++# end of USB HID support
++
++#
++# I2C HID support
++#
++# CONFIG_I2C_HID_ACPI is not set
++# end of I2C HID support
++
++#
++# Intel ISH HID support
++#
++# CONFIG_INTEL_ISH_HID is not set
++# end of Intel ISH HID support
++
++#
++# AMD SFH HID Support
++#
++# CONFIG_AMD_SFH_HID is not set
++# end of AMD SFH HID Support
++# end of HID support
++
++CONFIG_USB_OHCI_LITTLE_ENDIAN=y
++CONFIG_USB_SUPPORT=y
++CONFIG_USB_COMMON=y
++# CONFIG_USB_LED_TRIG is not set
++# CONFIG_USB_ULPI_BUS is not set
++CONFIG_USB_ARCH_HAS_HCD=y
++CONFIG_USB=y
++CONFIG_USB_PCI=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++
++#
++# Miscellaneous USB options
++#
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_FEW_INIT_RETRIES is not set
++# CONFIG_USB_DYNAMIC_MINORS is not set
++# CONFIG_USB_OTG_PRODUCTLIST is not set
++# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
++# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
++CONFIG_USB_AUTOSUSPEND_DELAY=2
++# CONFIG_USB_MON is not set
++
++#
++# USB Host Controller Drivers
++#
++# CONFIG_USB_C67X00_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++# CONFIG_USB_XHCI_DBGCAP is not set
++CONFIG_USB_XHCI_PCI=y
++# CONFIG_USB_XHCI_PCI_RENESAS is not set
++# CONFIG_USB_XHCI_PLATFORM is not set
++CONFIG_USB_XHCI_AEOLIA=y
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_SL811_HCD is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++
++#
++# USB Device Class drivers
++#
++# CONFIG_USB_ACM is not set
++# CONFIG_USB_PRINTER is not set
++# CONFIG_USB_WDM is not set
++# CONFIG_USB_TMC is not set
++
++#
++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
++#
++
++#
++# also be needed; see USB_STORAGE Help for more info
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_STORAGE_DEBUG is not set
++# CONFIG_USB_STORAGE_REALTEK is not set
++# CONFIG_USB_STORAGE_DATAFAB is not set
++# CONFIG_USB_STORAGE_FREECOM is not set
++# CONFIG_USB_STORAGE_ISD200 is not set
++# CONFIG_USB_STORAGE_USBAT is not set
++# CONFIG_USB_STORAGE_SDDR09 is not set
++# CONFIG_USB_STORAGE_SDDR55 is not set
++# CONFIG_USB_STORAGE_JUMPSHOT is not set
++# CONFIG_USB_STORAGE_ALAUDA is not set
++# CONFIG_USB_STORAGE_ONETOUCH is not set
++# CONFIG_USB_STORAGE_KARMA is not set
++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
++# CONFIG_USB_STORAGE_ENE_UB6250 is not set
++CONFIG_USB_UAS=y
++
++#
++# USB Imaging devices
++#
++# CONFIG_USB_MDC800 is not set
++# CONFIG_USB_MICROTEK is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_USB_CDNS_SUPPORT is not set
++# CONFIG_USB_MUSB_HDRC is not set
++# CONFIG_USB_DWC3 is not set
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_ISP1760 is not set
++
++#
++# USB port drivers
++#
++# CONFIG_USB_SERIAL is not set
++
++#
++# USB Miscellaneous drivers
++#
++# CONFIG_USB_EMI62 is not set
++# CONFIG_USB_EMI26 is not set
++# CONFIG_USB_ADUTUX is not set
++# CONFIG_USB_SEVSEG is not set
++# CONFIG_USB_LEGOTOWER is not set
++# CONFIG_USB_LCD is not set
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++# CONFIG_USB_CYTHERM is not set
++# CONFIG_USB_IDMOUSE is not set
++# CONFIG_USB_FTDI_ELAN is not set
++# CONFIG_USB_APPLEDISPLAY is not set
++# CONFIG_APPLE_MFI_FASTCHARGE is not set
++# CONFIG_USB_LD is not set
++# CONFIG_USB_TRANCEVIBRATOR is not set
++# CONFIG_USB_IOWARRIOR is not set
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++# CONFIG_USB_ISIGHTFW is not set
++# CONFIG_USB_YUREX is not set
++# CONFIG_USB_EZUSB_FX2 is not set
++# CONFIG_USB_HUB_USB251XB is not set
++# CONFIG_USB_HSIC_USB3503 is not set
++# CONFIG_USB_HSIC_USB4604 is not set
++# CONFIG_USB_LINK_LAYER_TEST is not set
++# CONFIG_USB_CHAOSKEY is not set
++
++#
++# USB Physical Layer drivers
++#
++# CONFIG_NOP_USB_XCEIV is not set
++# CONFIG_USB_ISP1301 is not set
++# end of USB Physical Layer drivers
++
++# CONFIG_USB_GADGET is not set
++# CONFIG_TYPEC is not set
++# CONFIG_USB_ROLE_SWITCH is not set
++CONFIG_MMC=y
++# CONFIG_MMC_BLOCK is not set
++# CONFIG_SDIO_UART is not set
++# CONFIG_MMC_TEST is not set
++
++#
++# MMC/SD/SDIO Host Controller Drivers
++#
++# CONFIG_MMC_DEBUG is not set
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_IO_ACCESSORS=y
++CONFIG_MMC_SDHCI_PCI=y
++# CONFIG_MMC_RICOH_MMC is not set
++# CONFIG_MMC_SDHCI_ACPI is not set
++# CONFIG_MMC_SDHCI_PLTFM is not set
++# CONFIG_MMC_WBSD is not set
++# CONFIG_MMC_TIFM_SD is not set
++# CONFIG_MMC_CB710 is not set
++# CONFIG_MMC_VIA_SDMMC is not set
++# CONFIG_MMC_VUB300 is not set
++# CONFIG_MMC_USHC is not set
++# CONFIG_MMC_USDHI6ROL0 is not set
++CONFIG_MMC_CQHCI=y
++# CONFIG_MMC_HSQ is not set
++# CONFIG_MMC_TOSHIBA_PCI is not set
++# CONFIG_MMC_MTK is not set
++# CONFIG_MEMSTICK is not set
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++# CONFIG_LEDS_CLASS_FLASH is not set
++# CONFIG_LEDS_CLASS_MULTICOLOR is not set
++# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
++
++#
++# LED drivers
++#
++# CONFIG_LEDS_APU is not set
++# CONFIG_LEDS_LM3530 is not set
++# CONFIG_LEDS_LM3532 is not set
++# CONFIG_LEDS_LM3642 is not set
++# CONFIG_LEDS_PCA9532 is not set
++# CONFIG_LEDS_LP3944 is not set
++# CONFIG_LEDS_LP50XX is not set
++# CONFIG_LEDS_CLEVO_MAIL is not set
++# CONFIG_LEDS_PCA955X is not set
++# CONFIG_LEDS_PCA963X is not set
++# CONFIG_LEDS_BD2802 is not set
++# CONFIG_LEDS_INTEL_SS4200 is not set
++# CONFIG_LEDS_TCA6507 is not set
++# CONFIG_LEDS_TLC591XX is not set
++# CONFIG_LEDS_LM355x is not set
++
++#
++# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
++#
++# CONFIG_LEDS_BLINKM is not set
++# CONFIG_LEDS_MLXCPLD is not set
++# CONFIG_LEDS_MLXREG is not set
++# CONFIG_LEDS_USER is not set
++# CONFIG_LEDS_NIC78BX is not set
++# CONFIG_LEDS_TI_LMU_COMMON is not set
++
++#
++# Flash and Torch LED drivers
++#
++
++#
++# LED Triggers
++#
++CONFIG_LEDS_TRIGGERS=y
++# CONFIG_LEDS_TRIGGER_TIMER is not set
++# CONFIG_LEDS_TRIGGER_ONESHOT is not set
++# CONFIG_LEDS_TRIGGER_DISK is not set
++# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
++# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
++# CONFIG_LEDS_TRIGGER_CPU is not set
++# CONFIG_LEDS_TRIGGER_ACTIVITY is not set
++# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
++
++#
++# iptables trigger is under Netfilter config (LED target)
++#
++# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
++# CONFIG_LEDS_TRIGGER_CAMERA is not set
++# CONFIG_LEDS_TRIGGER_PANIC is not set
++# CONFIG_LEDS_TRIGGER_NETDEV is not set
++# CONFIG_LEDS_TRIGGER_PATTERN is not set
++CONFIG_LEDS_TRIGGER_AUDIO=y
++# CONFIG_LEDS_TRIGGER_TTY is not set
++# CONFIG_ACCESSIBILITY is not set
++# CONFIG_INFINIBAND is not set
++CONFIG_EDAC_ATOMIC_SCRUB=y
++CONFIG_EDAC_SUPPORT=y
++# CONFIG_EDAC is not set
++CONFIG_RTC_LIB=y
++CONFIG_RTC_MC146818_LIB=y
++# CONFIG_RTC_CLASS is not set
++CONFIG_DMADEVICES=y
++CONFIG_DMADEVICES_DEBUG=y
++CONFIG_DMADEVICES_VDEBUG=y
++
++#
++# DMA Devices
++#
++CONFIG_DMA_ACPI=y
++# CONFIG_ALTERA_MSGDMA is not set
++# CONFIG_INTEL_IDMA64 is not set
++# CONFIG_INTEL_IDXD is not set
++# CONFIG_INTEL_IDXD_COMPAT is not set
++# CONFIG_INTEL_IOATDMA is not set
++# CONFIG_PLX_DMA is not set
++# CONFIG_AMD_PTDMA is not set
++# CONFIG_QCOM_HIDMA_MGMT is not set
++# CONFIG_QCOM_HIDMA is not set
++# CONFIG_DW_DMAC is not set
++# CONFIG_DW_DMAC_PCI is not set
++# CONFIG_DW_EDMA is not set
++# CONFIG_DW_EDMA_PCIE is not set
++# CONFIG_SF_PDMA is not set
++# CONFIG_INTEL_LDMA is not set
++
++#
++# DMABUF options
++#
++CONFIG_SYNC_FILE=y
++# CONFIG_SW_SYNC is not set
++# CONFIG_UDMABUF is not set
++# CONFIG_DMABUF_MOVE_NOTIFY is not set
++# CONFIG_DMABUF_DEBUG is not set
++# CONFIG_DMABUF_SELFTESTS is not set
++# CONFIG_DMABUF_HEAPS is not set
++# CONFIG_DMABUF_SYSFS_STATS is not set
++# end of DMABUF options
++
++# CONFIG_AUXDISPLAY is not set
++CONFIG_UIO=y
++# CONFIG_UIO_CIF is not set
++CONFIG_UIO_PDRV_GENIRQ=y
++CONFIG_UIO_DMEM_GENIRQ=y
++# CONFIG_UIO_AEC is not set
++# CONFIG_UIO_SERCOS3 is not set
++CONFIG_UIO_PCI_GENERIC=y
++# CONFIG_UIO_NETX is not set
++# CONFIG_UIO_PRUSS is not set
++# CONFIG_UIO_MF624 is not set
++# CONFIG_VFIO is not set
++CONFIG_IRQ_BYPASS_MANAGER=y
++# CONFIG_VIRT_DRIVERS is not set
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VDPA is not set
++CONFIG_VHOST_MENU=y
++# CONFIG_VHOST_NET is not set
++# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
++
++#
++# Microsoft Hyper-V guest support
++#
++# end of Microsoft Hyper-V guest support
++
++# CONFIG_GREYBUS is not set
++# CONFIG_COMEDI is not set
++# CONFIG_STAGING is not set
++# CONFIG_X86_PLATFORM_DEVICES is not set
++CONFIG_PMC_ATOM=y
++# CONFIG_CHROME_PLATFORMS is not set
++# CONFIG_MELLANOX_PLATFORM is not set
++# CONFIG_SURFACE_PLATFORMS is not set
++CONFIG_HAVE_CLK=y
++CONFIG_HAVE_CLK_PREPARE=y
++CONFIG_COMMON_CLK=y
++
++#
++# Clock driver for ARM Reference designs
++#
++# CONFIG_ICST is not set
++# CONFIG_CLK_SP810 is not set
++# end of Clock driver for ARM Reference designs
++
++# CONFIG_COMMON_CLK_MAX9485 is not set
++# CONFIG_COMMON_CLK_SI5341 is not set
++# CONFIG_COMMON_CLK_SI5351 is not set
++# CONFIG_COMMON_CLK_SI544 is not set
++# CONFIG_COMMON_CLK_CDCE706 is not set
++# CONFIG_COMMON_CLK_CS2000_CP is not set
++# CONFIG_XILINX_VCU is not set
++# CONFIG_HWSPINLOCK is not set
++
++#
++# Clock Source drivers
++#
++CONFIG_CLKEVT_I8253=y
++CONFIG_CLKBLD_I8253=y
++# end of Clock Source drivers
++
++# CONFIG_MAILBOX is not set
++CONFIG_IOMMU_IOVA=y
++CONFIG_IOMMU_API=y
++CONFIG_IOMMU_SUPPORT=y
++
++#
++# Generic IOMMU Pagetable Support
++#
++CONFIG_IOMMU_IO_PGTABLE=y
++# end of Generic IOMMU Pagetable Support
++
++# CONFIG_IOMMU_DEBUGFS is not set
++# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
++# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
++CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
++CONFIG_IOMMU_DMA=y
++CONFIG_AMD_IOMMU=y
++# CONFIG_AMD_IOMMU_V2 is not set
++CONFIG_DMAR_TABLE=y
++# CONFIG_INTEL_IOMMU is not set
++CONFIG_IRQ_REMAP=y
++
++#
++# Remoteproc drivers
++#
++# CONFIG_REMOTEPROC is not set
++# end of Remoteproc drivers
++
++#
++# Rpmsg drivers
++#
++# CONFIG_RPMSG_VIRTIO is not set
++# end of Rpmsg drivers
++
++# CONFIG_SOUNDWIRE is not set
++
++#
++# SOC (System On Chip) specific Drivers
++#
++
++#
++# Amlogic SoC drivers
++#
++# end of Amlogic SoC drivers
++
++#
++# Broadcom SoC drivers
++#
++# end of Broadcom SoC drivers
++
++#
++# NXP/Freescale QorIQ SoC drivers
++#
++# end of NXP/Freescale QorIQ SoC drivers
++
++#
++# i.MX SoC drivers
++#
++# end of i.MX SoC drivers
++
++#
++# Enable LiteX SoC Builder specific drivers
++#
++# end of Enable LiteX SoC Builder specific drivers
++
++#
++# Qualcomm SoC drivers
++#
++# end of Qualcomm SoC drivers
++
++# CONFIG_SOC_TI is not set
++
++#
++# Xilinx SoC drivers
++#
++# end of Xilinx SoC drivers
++# end of SOC (System On Chip) specific Drivers
++
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_EXTCON is not set
++# CONFIG_MEMORY is not set
++# CONFIG_IIO is not set
++# CONFIG_NTB is not set
++# CONFIG_VME_BUS is not set
++# CONFIG_PWM is not set
++
++#
++# IRQ chip support
++#
++# end of IRQ chip support
++
++# CONFIG_IPACK_BUS is not set
++# CONFIG_RESET_CONTROLLER is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_GENERIC_PHY=y
++# CONFIG_USB_LGM_PHY is not set
++# CONFIG_PHY_CAN_TRANSCEIVER is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++# CONFIG_PHY_PXA_28NM_HSIC is not set
++# CONFIG_PHY_PXA_28NM_USB2 is not set
++# CONFIG_PHY_INTEL_LGM_EMMC is not set
++# end of PHY Subsystem
++
++# CONFIG_POWERCAP is not set
++# CONFIG_MCB is not set
++
++#
++# Performance monitor support
++#
++# end of Performance monitor support
++
++CONFIG_RAS=y
++# CONFIG_USB4 is not set
++
++#
++# Android
++#
++# CONFIG_ANDROID is not set
++# end of Android
++
++# CONFIG_LIBNVDIMM is not set
++CONFIG_DAX=y
++# CONFIG_DEV_DAX is not set
++CONFIG_NVMEM=y
++CONFIG_NVMEM_SYSFS=y
++# CONFIG_NVMEM_RMEM is not set
++
++#
++# HW tracing support
++#
++# CONFIG_STM is not set
++# CONFIG_INTEL_TH is not set
++# end of HW tracing support
++
++# CONFIG_FPGA is not set
++# CONFIG_TEE is not set
++# CONFIG_UNISYS_VISORBUS is not set
++# CONFIG_SIOX is not set
++# CONFIG_SLIMBUS is not set
++# CONFIG_INTERCONNECT is not set
++# CONFIG_COUNTER is not set
++# CONFIG_MOST is not set
++# end of Device Drivers
++
++#
++# File systems
++#
++CONFIG_DCACHE_WORD_ACCESS=y
++# CONFIG_VALIDATE_FS_PARSER is not set
++CONFIG_FS_IOMAP=y
++# CONFIG_EXT2_FS is not set
++# CONFIG_EXT3_FS is not set
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_USE_FOR_EXT2=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++# CONFIG_EXT4_DEBUG is not set
++CONFIG_JBD2=y
++# CONFIG_JBD2_DEBUG is not set
++CONFIG_FS_MBCACHE=y
++# CONFIG_REISERFS_FS is not set
++# CONFIG_JFS_FS is not set
++# CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
++# CONFIG_BTRFS_FS is not set
++# CONFIG_NILFS2_FS is not set
++# CONFIG_F2FS_FS is not set
++# CONFIG_FS_DAX is not set
++CONFIG_FS_POSIX_ACL=y
++CONFIG_EXPORTFS=y
++# CONFIG_EXPORTFS_BLOCK_OPS is not set
++CONFIG_FILE_LOCKING=y
++# CONFIG_FS_ENCRYPTION is not set
++# CONFIG_FS_VERITY is not set
++CONFIG_FSNOTIFY=y
++CONFIG_DNOTIFY=y
++CONFIG_INOTIFY_USER=y
++CONFIG_FANOTIFY=y
++# CONFIG_QUOTA is not set
++CONFIG_AUTOFS4_FS=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_CUSE=y
++# CONFIG_VIRTIO_FS is not set
++# CONFIG_OVERLAY_FS is not set
++
++#
++# Caches
++#
++# CONFIG_FSCACHE is not set
++# end of Caches
++
++#
++# CD-ROM/DVD Filesystems
++#
++CONFIG_ISO9660_FS=y
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=y
++# end of CD-ROM/DVD Filesystems
++
++#
++# DOS/FAT/EXFAT/NT Filesystems
++#
++CONFIG_FAT_FS=y
++# CONFIG_MSDOS_FS is not set
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_CODEPAGE=850
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_FAT_DEFAULT_UTF8 is not set
++CONFIG_EXFAT_FS=y
++CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
++CONFIG_NTFS_FS=y
++# CONFIG_NTFS_DEBUG is not set
++CONFIG_NTFS_RW=y
++CONFIG_NTFS3_FS=y
++CONFIG_NTFS3_64BIT_CLUSTER=y
++# CONFIG_NTFS3_LZX_XPRESS is not set
++# CONFIG_NTFS3_FS_POSIX_ACL is not set
++# end of DOS/FAT/EXFAT/NT Filesystems
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++# CONFIG_PROC_KCORE is not set
++CONFIG_PROC_SYSCTL=y
++CONFIG_PROC_PAGE_MONITOR=y
++# CONFIG_PROC_CHILDREN is not set
++CONFIG_PROC_PID_ARCH_STATUS=y
++CONFIG_KERNFS=y
++CONFIG_SYSFS=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_TMPFS_XATTR=y
++# CONFIG_TMPFS_INODE64 is not set
++CONFIG_HUGETLBFS=y
++CONFIG_HUGETLB_PAGE=y
++CONFIG_HUGETLB_PAGE_FREE_VMEMMAP=y
++# CONFIG_HUGETLB_PAGE_FREE_VMEMMAP_DEFAULT_ON is not set
++CONFIG_MEMFD_CREATE=y
++CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
++CONFIG_CONFIGFS_FS=y
++# end of Pseudo filesystems
++
++CONFIG_MISC_FILESYSTEMS=y
++# CONFIG_ORANGEFS_FS is not set
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_ECRYPT_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++# CONFIG_CRAMFS is not set
++# CONFIG_SQUASHFS is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_OMFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_PSTORE is not set
++# CONFIG_SYSV_FS is not set
++CONFIG_UFS_FS=y
++CONFIG_UFS_FS_WRITE=y
++CONFIG_UFS_DEBUG=y
++# CONFIG_EROFS_FS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V2 is not set
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++# CONFIG_NFS_V4 is not set
++CONFIG_NFS_SWAP=y
++CONFIG_ROOT_NFS=y
++CONFIG_NFS_DISABLE_UDP_SUPPORT=y
++# CONFIG_NFSD is not set
++CONFIG_GRACE_PERIOD=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_ACL_SUPPORT=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++CONFIG_SUNRPC_SWAP=y
++# CONFIG_SUNRPC_DEBUG is not set
++# CONFIG_CEPH_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_SMB_SERVER is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++CONFIG_NLS_CODEPAGE_850=y
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++CONFIG_NLS_ISO8859_15=y
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_MAC_ROMAN is not set
++# CONFIG_NLS_MAC_CELTIC is not set
++# CONFIG_NLS_MAC_CENTEURO is not set
++# CONFIG_NLS_MAC_CROATIAN is not set
++# CONFIG_NLS_MAC_CYRILLIC is not set
++# CONFIG_NLS_MAC_GAELIC is not set
++# CONFIG_NLS_MAC_GREEK is not set
++# CONFIG_NLS_MAC_ICELAND is not set
++# CONFIG_NLS_MAC_INUIT is not set
++# CONFIG_NLS_MAC_ROMANIAN is not set
++# CONFIG_NLS_MAC_TURKISH is not set
++CONFIG_NLS_UTF8=y
++# CONFIG_DLM is not set
++# CONFIG_UNICODE is not set
++# end of File systems
++
++#
++# Security options
++#
++CONFIG_KEYS=y
++# CONFIG_KEYS_REQUEST_CACHE is not set
++# CONFIG_PERSISTENT_KEYRINGS is not set
++# CONFIG_BIG_KEYS is not set
++# CONFIG_ENCRYPTED_KEYS is not set
++# CONFIG_KEY_DH_OPERATIONS is not set
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++# CONFIG_SECURITY is not set
++# CONFIG_SECURITYFS is not set
++# CONFIG_PAGE_TABLE_ISOLATION is not set
++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
++# CONFIG_HARDENED_USERCOPY is not set
++# CONFIG_FORTIFY_SOURCE is not set
++# CONFIG_STATIC_USERMODEHELPER is not set
++CONFIG_DEFAULT_SECURITY_DAC=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity"
++
++#
++# Kernel hardening options
++#
++
++#
++# Memory initialization
++#
++CONFIG_INIT_STACK_NONE=y
++# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
++# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
++# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
++# CONFIG_GCC_PLUGIN_STACKLEAK is not set
++# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
++# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
++CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
++# CONFIG_ZERO_CALL_USED_REGS is not set
++# end of Memory initialization
++# end of Kernel hardening options
++# end of Security options
++
++CONFIG_CRYPTO=y
++
++#
++# Crypto core or helper
++#
++CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_ALGAPI2=y
++CONFIG_CRYPTO_AEAD=y
++CONFIG_CRYPTO_AEAD2=y
++CONFIG_CRYPTO_SKCIPHER=y
++CONFIG_CRYPTO_SKCIPHER2=y
++CONFIG_CRYPTO_HASH=y
++CONFIG_CRYPTO_HASH2=y
++CONFIG_CRYPTO_RNG=y
++CONFIG_CRYPTO_RNG2=y
++CONFIG_CRYPTO_RNG_DEFAULT=y
++CONFIG_CRYPTO_AKCIPHER2=y
++CONFIG_CRYPTO_AKCIPHER=y
++CONFIG_CRYPTO_KPP2=y
++CONFIG_CRYPTO_KPP=y
++CONFIG_CRYPTO_ACOMP2=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++# CONFIG_CRYPTO_USER is not set
++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
++CONFIG_CRYPTO_GF128MUL=y
++CONFIG_CRYPTO_NULL=y
++CONFIG_CRYPTO_NULL2=y
++# CONFIG_CRYPTO_PCRYPT is not set
++CONFIG_CRYPTO_CRYPTD=y
++CONFIG_CRYPTO_AUTHENC=y
++# CONFIG_CRYPTO_TEST is not set
++CONFIG_CRYPTO_SIMD=y
++
++#
++# Public-key cryptography
++#
++CONFIG_CRYPTO_RSA=y
++# CONFIG_CRYPTO_DH is not set
++CONFIG_CRYPTO_ECC=y
++CONFIG_CRYPTO_ECDH=y
++# CONFIG_CRYPTO_ECDSA is not set
++# CONFIG_CRYPTO_ECRDSA is not set
++# CONFIG_CRYPTO_SM2 is not set
++# CONFIG_CRYPTO_CURVE25519 is not set
++CONFIG_CRYPTO_CURVE25519_X86=y
++
++#
++# Authenticated Encryption with Associated Data
++#
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
++# CONFIG_CRYPTO_AEGIS128 is not set
++# CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set
++CONFIG_CRYPTO_SEQIV=y
++# CONFIG_CRYPTO_ECHAINIV is not set
++
++#
++# Block modes
++#
++CONFIG_CRYPTO_CBC=y
++# CONFIG_CRYPTO_CFB is not set
++CONFIG_CRYPTO_CTR=y
++# CONFIG_CRYPTO_CTS is not set
++CONFIG_CRYPTO_ECB=y
++CONFIG_CRYPTO_LRW=y
++# CONFIG_CRYPTO_OFB is not set
++# CONFIG_CRYPTO_PCBC is not set
++CONFIG_CRYPTO_XTS=y
++# CONFIG_CRYPTO_KEYWRAP is not set
++# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set
++# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set
++# CONFIG_CRYPTO_ADIANTUM is not set
++CONFIG_CRYPTO_ESSIV=y
++
++#
++# Hash modes
++#
++CONFIG_CRYPTO_CMAC=y
++CONFIG_CRYPTO_HMAC=y
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_VMAC is not set
++
++#
++# Digest
++#
++CONFIG_CRYPTO_CRC32C=y
++CONFIG_CRYPTO_CRC32C_INTEL=y
++CONFIG_CRYPTO_CRC32=y
++CONFIG_CRYPTO_CRC32_PCLMUL=y
++# CONFIG_CRYPTO_XXHASH is not set
++# CONFIG_CRYPTO_BLAKE2B is not set
++# CONFIG_CRYPTO_BLAKE2S is not set
++CONFIG_CRYPTO_BLAKE2S_X86=y
++# CONFIG_CRYPTO_CRCT10DIF is not set
++CONFIG_CRYPTO_GHASH=y
++# CONFIG_CRYPTO_POLY1305 is not set
++CONFIG_CRYPTO_POLY1305_X86_64=y
++# CONFIG_CRYPTO_MD4 is not set
++CONFIG_CRYPTO_MD5=y
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_RMD160 is not set
++CONFIG_CRYPTO_SHA1=y
++CONFIG_CRYPTO_SHA1_SSSE3=y
++CONFIG_CRYPTO_SHA256_SSSE3=y
++CONFIG_CRYPTO_SHA512_SSSE3=y
++CONFIG_CRYPTO_SHA256=y
++CONFIG_CRYPTO_SHA512=y
++# CONFIG_CRYPTO_SHA3 is not set
++# CONFIG_CRYPTO_SM3 is not set
++# CONFIG_CRYPTO_STREEBOG is not set
++CONFIG_CRYPTO_WP512=y
++# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set
++
++#
++# Ciphers
++#
++CONFIG_CRYPTO_AES=y
++# CONFIG_CRYPTO_AES_TI is not set
++CONFIG_CRYPTO_AES_NI_INTEL=y
++# CONFIG_CRYPTO_ANUBIS is not set
++CONFIG_CRYPTO_ARC4=y
++# CONFIG_CRYPTO_BLOWFISH is not set
++CONFIG_CRYPTO_BLOWFISH_COMMON=y
++CONFIG_CRYPTO_BLOWFISH_X86_64=y
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set
++# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set
++# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_DES3_EDE_X86_64=y
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_CHACHA20 is not set
++CONFIG_CRYPTO_CHACHA20_X86_64=y
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set
++# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set
++# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set
++# CONFIG_CRYPTO_SM4 is not set
++# CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64 is not set
++# CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64 is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++CONFIG_CRYPTO_TWOFISH_COMMON=y
++CONFIG_CRYPTO_TWOFISH_X86_64=y
++CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=y
++CONFIG_CRYPTO_TWOFISH_AVX_X86_64=y
++
++#
++# Compression
++#
++CONFIG_CRYPTO_DEFLATE=y
++# CONFIG_CRYPTO_LZO is not set
++# CONFIG_CRYPTO_842 is not set
++# CONFIG_CRYPTO_LZ4 is not set
++# CONFIG_CRYPTO_LZ4HC is not set
++# CONFIG_CRYPTO_ZSTD is not set
++
++#
++# Random Number Generation
++#
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_DRBG_MENU=y
++CONFIG_CRYPTO_DRBG_HMAC=y
++# CONFIG_CRYPTO_DRBG_HASH is not set
++# CONFIG_CRYPTO_DRBG_CTR is not set
++CONFIG_CRYPTO_DRBG=y
++CONFIG_CRYPTO_JITTERENTROPY=y
++CONFIG_CRYPTO_USER_API=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_USER_API_RNG=y
++# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
++# CONFIG_CRYPTO_USER_API_AEAD is not set
++CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
++CONFIG_CRYPTO_HASH_INFO=y
++
++#
++# Crypto library routines
++#
++CONFIG_CRYPTO_LIB_AES=y
++CONFIG_CRYPTO_LIB_ARC4=y
++CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
++CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
++CONFIG_CRYPTO_LIB_BLAKE2S=y
++CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
++CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
++CONFIG_CRYPTO_LIB_CHACHA=y
++CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=y
++CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
++CONFIG_CRYPTO_LIB_CURVE25519=y
++CONFIG_CRYPTO_LIB_DES=y
++CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
++CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
++CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
++CONFIG_CRYPTO_LIB_POLY1305=y
++CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
++CONFIG_CRYPTO_LIB_SHA256=y
++CONFIG_CRYPTO_HW=y
++# CONFIG_CRYPTO_DEV_PADLOCK is not set
++# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
++# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
++CONFIG_CRYPTO_DEV_CCP=y
++# CONFIG_CRYPTO_DEV_CCP_DD is not set
++# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
++# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
++# CONFIG_CRYPTO_DEV_QAT_C62X is not set
++# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
++# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
++# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set
++# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
++# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
++# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
++# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
++CONFIG_ASYMMETRIC_KEY_TYPE=y
++CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
++CONFIG_X509_CERTIFICATE_PARSER=y
++# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
++CONFIG_PKCS7_MESSAGE_PARSER=y
++# CONFIG_PKCS7_TEST_KEY is not set
++# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
++
++#
++# Certificates for signature checking
++#
++CONFIG_SYSTEM_TRUSTED_KEYRING=y
++CONFIG_SYSTEM_TRUSTED_KEYS=""
++# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
++# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
++# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
++# end of Certificates for signature checking
++
++#
++# Library routines
++#
++# CONFIG_PACKING is not set
++CONFIG_BITREVERSE=y
++CONFIG_GENERIC_STRNCPY_FROM_USER=y
++CONFIG_GENERIC_STRNLEN_USER=y
++CONFIG_GENERIC_NET_UTILS=y
++CONFIG_GENERIC_FIND_FIRST_BIT=y
++# CONFIG_CORDIC is not set
++# CONFIG_PRIME_NUMBERS is not set
++CONFIG_RATIONAL=y
++CONFIG_GENERIC_PCI_IOMAP=y
++CONFIG_GENERIC_IOMAP=y
++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
++CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
++CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC16=y
++# CONFIG_CRC_T10DIF is not set
++CONFIG_CRC_ITU_T=y
++CONFIG_CRC32=y
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC32_SLICEBY8=y
++# CONFIG_CRC32_SLICEBY4 is not set
++# CONFIG_CRC32_SARWATE is not set
++# CONFIG_CRC32_BIT is not set
++# CONFIG_CRC64 is not set
++# CONFIG_CRC4 is not set
++CONFIG_CRC7=y
++CONFIG_LIBCRC32C=y
++# CONFIG_CRC8 is not set
++CONFIG_XXHASH=y
++CONFIG_RANDOM32_SELFTEST=y
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
++CONFIG_LZO_DECOMPRESS=y
++CONFIG_LZ4_DECOMPRESS=y
++CONFIG_XZ_DEC=y
++CONFIG_XZ_DEC_X86=y
++# CONFIG_XZ_DEC_POWERPC is not set
++# CONFIG_XZ_DEC_IA64 is not set
++# CONFIG_XZ_DEC_ARM is not set
++# CONFIG_XZ_DEC_ARMTHUMB is not set
++# CONFIG_XZ_DEC_SPARC is not set
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_DECOMPRESS_GZIP=y
++CONFIG_DECOMPRESS_BZIP2=y
++CONFIG_DECOMPRESS_LZMA=y
++CONFIG_DECOMPRESS_XZ=y
++CONFIG_DECOMPRESS_LZO=y
++CONFIG_DECOMPRESS_LZ4=y
++CONFIG_GENERIC_ALLOCATOR=y
++CONFIG_INTERVAL_TREE=y
++CONFIG_XARRAY_MULTI=y
++CONFIG_ASSOCIATIVE_ARRAY=y
++CONFIG_HAS_IOMEM=y
++CONFIG_HAS_IOPORT_MAP=y
++CONFIG_HAS_DMA=y
++CONFIG_DMA_OPS=y
++CONFIG_NEED_SG_DMA_LENGTH=y
++CONFIG_NEED_DMA_MAP_STATE=y
++CONFIG_ARCH_DMA_ADDR_T_64BIT=y
++CONFIG_SWIOTLB=y
++# CONFIG_DMA_API_DEBUG is not set
++# CONFIG_DMA_MAP_BENCHMARK is not set
++CONFIG_SGL_ALLOC=y
++CONFIG_IOMMU_HELPER=y
++CONFIG_CPU_RMAP=y
++CONFIG_DQL=y
++CONFIG_GLOB=y
++# CONFIG_GLOB_SELFTEST is not set
++CONFIG_NLATTR=y
++CONFIG_CLZ_TAB=y
++# CONFIG_IRQ_POLL is not set
++CONFIG_MPILIB=y
++CONFIG_OID_REGISTRY=y
++CONFIG_HAVE_GENERIC_VDSO=y
++CONFIG_GENERIC_GETTIMEOFDAY=y
++CONFIG_GENERIC_VDSO_TIME_NS=y
++CONFIG_FONT_SUPPORT=y
++CONFIG_FONTS=y
++# CONFIG_FONT_8x8 is not set
++# CONFIG_FONT_8x16 is not set
++CONFIG_FONT_6x11=y
++# CONFIG_FONT_7x14 is not set
++# CONFIG_FONT_PEARL_8x8 is not set
++# CONFIG_FONT_ACORN_8x8 is not set
++# CONFIG_FONT_MINI_4x6 is not set
++CONFIG_FONT_6x10=y
++CONFIG_FONT_10x18=y
++CONFIG_FONT_SUN8x16=y
++# CONFIG_FONT_SUN12x22 is not set
++# CONFIG_FONT_TER16x32 is not set
++# CONFIG_FONT_6x8 is not set
++CONFIG_SG_POOL=y
++CONFIG_ARCH_HAS_PMEM_API=y
++CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y
++CONFIG_ARCH_HAS_COPY_MC=y
++CONFIG_ARCH_STACKWALK=y
++CONFIG_SBITMAP=y
++# end of Library routines
++
++#
++# Kernel hacking
++#
++
++#
++# printk and dmesg options
++#
++CONFIG_PRINTK_TIME=y
++# CONFIG_PRINTK_CALLER is not set
++# CONFIG_STACKTRACE_BUILD_ID is not set
++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
++CONFIG_CONSOLE_LOGLEVEL_QUIET=4
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=5
++# CONFIG_BOOT_PRINTK_DELAY is not set
++# CONFIG_DYNAMIC_DEBUG is not set
++# CONFIG_DYNAMIC_DEBUG_CORE is not set
++CONFIG_SYMBOLIC_ERRNAME=y
++CONFIG_DEBUG_BUGVERBOSE=y
++# end of printk and dmesg options
++
++#
++# Compile-time checks and compiler options
++#
++# CONFIG_DEBUG_INFO is not set
++CONFIG_FRAME_WARN=2048
++# CONFIG_STRIP_ASM_SYMS is not set
++# CONFIG_READABLE_ASM is not set
++# CONFIG_HEADERS_INSTALL is not set
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
++# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
++CONFIG_STACK_VALIDATION=y
++# CONFIG_VMLINUX_MAP is not set
++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
++# end of Compile-time checks and compiler options
++
++#
++# Generic Kernel Debugging Instruments
++#
++# CONFIG_MAGIC_SYSRQ is not set
++CONFIG_DEBUG_FS=y
++# CONFIG_DEBUG_FS_ALLOW_ALL is not set
++# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
++CONFIG_DEBUG_FS_ALLOW_NONE=y
++CONFIG_HAVE_ARCH_KGDB=y
++# CONFIG_KGDB is not set
++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
++# CONFIG_UBSAN is not set
++CONFIG_HAVE_ARCH_KCSAN=y
++CONFIG_HAVE_KCSAN_COMPILER=y
++# CONFIG_KCSAN is not set
++# end of Generic Kernel Debugging Instruments
++
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_DEBUG_MISC is not set
++
++#
++# Memory Debugging
++#
++# CONFIG_PAGE_EXTENSION is not set
++# CONFIG_DEBUG_PAGEALLOC is not set
++# CONFIG_PAGE_OWNER is not set
++# CONFIG_PAGE_POISONING is not set
++CONFIG_DEBUG_RODATA_TEST=y
++CONFIG_ARCH_HAS_DEBUG_WX=y
++# CONFIG_DEBUG_WX is not set
++CONFIG_GENERIC_PTDUMP=y
++# CONFIG_PTDUMP_DEBUGFS is not set
++# CONFIG_DEBUG_OBJECTS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
++CONFIG_HAVE_DEBUG_KMEMLEAK=y
++# CONFIG_DEBUG_KMEMLEAK is not set
++# CONFIG_DEBUG_STACK_USAGE is not set
++# CONFIG_SCHED_STACK_END_CHECK is not set
++CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_VM_PGTABLE is not set
++CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
++# CONFIG_DEBUG_VIRTUAL is not set
++# CONFIG_DEBUG_MEMORY_INIT is not set
++# CONFIG_DEBUG_PER_CPU_MAPS is not set
++CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y
++# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set
++CONFIG_HAVE_ARCH_KASAN=y
++CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
++CONFIG_CC_HAS_KASAN_GENERIC=y
++CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
++# CONFIG_KASAN is not set
++CONFIG_HAVE_ARCH_KFENCE=y
++# CONFIG_KFENCE is not set
++# end of Memory Debugging
++
++# CONFIG_DEBUG_SHIRQ is not set
++
++#
++# Debug Oops, Lockups and Hangs
++#
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_ON_OOPS_VALUE=0
++CONFIG_PANIC_TIMEOUT=10
++# CONFIG_SOFTLOCKUP_DETECTOR is not set
++CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y
++# CONFIG_HARDLOCKUP_DETECTOR is not set
++# CONFIG_DETECT_HUNG_TASK is not set
++# CONFIG_WQ_WATCHDOG is not set
++# CONFIG_TEST_LOCKUP is not set
++# end of Debug Oops, Lockups and Hangs
++
++#
++# Scheduler Debugging
++#
++# CONFIG_SCHED_DEBUG is not set
++CONFIG_SCHED_INFO=y
++# CONFIG_SCHEDSTATS is not set
++# end of Scheduler Debugging
++
++# CONFIG_DEBUG_TIMEKEEPING is not set
++
++#
++# Lock Debugging (spinlocks, mutexes, etc...)
++#
++CONFIG_LOCK_DEBUGGING_SUPPORT=y
++# CONFIG_PROVE_LOCKING is not set
++# CONFIG_LOCK_STAT is not set
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
++# CONFIG_DEBUG_RWSEMS is not set
++# CONFIG_DEBUG_LOCK_ALLOC is not set
++# CONFIG_DEBUG_ATOMIC_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++# CONFIG_LOCK_TORTURE_TEST is not set
++# CONFIG_WW_MUTEX_SELFTEST is not set
++# CONFIG_SCF_TORTURE_TEST is not set
++# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
++# end of Lock Debugging (spinlocks, mutexes, etc...)
++
++# CONFIG_DEBUG_IRQFLAGS is not set
++# CONFIG_STACKTRACE is not set
++# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
++# CONFIG_DEBUG_KOBJECT is not set
++
++#
++# Debug kernel data structures
++#
++# CONFIG_DEBUG_LIST is not set
++# CONFIG_DEBUG_PLIST is not set
++# CONFIG_DEBUG_SG is not set
++# CONFIG_DEBUG_NOTIFIERS is not set
++# CONFIG_BUG_ON_DATA_CORRUPTION is not set
++# end of Debug kernel data structures
++
++# CONFIG_DEBUG_CREDENTIALS is not set
++
++#
++# RCU Debugging
++#
++# CONFIG_RCU_SCALE_TEST is not set
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_REF_SCALE_TEST is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++# CONFIG_RCU_TRACE is not set
++# CONFIG_RCU_EQS_DEBUG is not set
++# end of RCU Debugging
++
++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
++# CONFIG_LATENCYTOP is not set
++CONFIG_USER_STACKTRACE_SUPPORT=y
++CONFIG_HAVE_FUNCTION_TRACER=y
++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
++CONFIG_HAVE_DYNAMIC_FTRACE=y
++CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
++CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
++CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y
++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
++CONFIG_HAVE_FENTRY=y
++CONFIG_HAVE_OBJTOOL_MCOUNT=y
++CONFIG_HAVE_C_RECORDMCOUNT=y
++CONFIG_TRACING_SUPPORT=y
++# CONFIG_FTRACE is not set
++# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
++# CONFIG_SAMPLES is not set
++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
++# CONFIG_STRICT_DEVMEM is not set
++
++#
++# x86 Debugging
++#
++CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
++CONFIG_X86_VERBOSE_BOOTUP=y
++CONFIG_EARLY_PRINTK=y
++# CONFIG_EARLY_PRINTK_DBGP is not set
++# CONFIG_EARLY_PRINTK_USB_XDBC is not set
++# CONFIG_DEBUG_TLBFLUSH is not set
++CONFIG_IOMMU_DEBUG=y
++CONFIG_HAVE_MMIOTRACE_SUPPORT=y
++# CONFIG_X86_DECODER_SELFTEST is not set
++CONFIG_IO_DELAY_0X80=y
++# CONFIG_IO_DELAY_0XED is not set
++# CONFIG_IO_DELAY_UDELAY is not set
++# CONFIG_IO_DELAY_NONE is not set
++CONFIG_DEBUG_BOOT_PARAMS=y
++# CONFIG_CPA_DEBUG is not set
++# CONFIG_DEBUG_ENTRY is not set
++# CONFIG_DEBUG_NMI_SELFTEST is not set
++# CONFIG_X86_DEBUG_FPU is not set
++# CONFIG_PUNIT_ATOM_DEBUG is not set
++CONFIG_UNWINDER_ORC=y
++# CONFIG_UNWINDER_FRAME_POINTER is not set
++# CONFIG_UNWINDER_GUESS is not set
++# end of x86 Debugging
++
++#
++# Kernel Testing and Coverage
++#
++# CONFIG_KUNIT is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_FAULT_INJECTION is not set
++CONFIG_ARCH_HAS_KCOV=y
++CONFIG_CC_HAS_SANCOV_TRACE_PC=y
++# CONFIG_KCOV is not set
++# CONFIG_RUNTIME_TESTING_MENU is not set
++CONFIG_ARCH_USE_MEMTEST=y
++# CONFIG_MEMTEST is not set
++# end of Kernel Testing and Coverage
++# end of Kernel hacking
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0009-feat-trying-to-modernize-ps4-apcie-so-it-works-with-.patch b/device/testing/linux-sony-ps4/0009-feat-trying-to-modernize-ps4-apcie-so-it-works-with-.patch
new file mode 100644
index 0000000000000000000000000000000000000000..d1e8d64112faea8fe57b2be66ded5787ca463f09
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0009-feat-trying-to-modernize-ps4-apcie-so-it-works-with-.patch
@@ -0,0 +1,158 @@
+From 0bd681355cbd557d93a6cc62e0b816ed661095c9 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Tue, 21 Dec 2021 19:22:42 +0100
+Subject: [PATCH 09/22] feat: trying to modernize ps4-apcie so it works with
+ kernel 5.15
+
+---
+ arch/x86/include/asm/irqdomain.h | 1 +
+ arch/x86/kernel/apic/vector.c | 11 ++++++++-
+ drivers/iommu/amd/iommu.c | 2 ++
+ drivers/pci/probe.c | 6 +++++
+ drivers/ps4/ps4-apcie.c | 40 ++++++++++++++++++++++++--------
+ 5 files changed, 49 insertions(+), 11 deletions(-)
+
+diff --git a/arch/x86/include/asm/irqdomain.h b/arch/x86/include/asm/irqdomain.h
+index 125c23b7bad3..2f8410292efc 100644
+--- a/arch/x86/include/asm/irqdomain.h
++++ b/arch/x86/include/asm/irqdomain.h
+@@ -14,6 +14,7 @@ enum {
+
+ extern int x86_fwspec_is_ioapic(struct irq_fwspec *fwspec);
+ extern int x86_fwspec_is_hpet(struct irq_fwspec *fwspec);
++extern int x86_fwspec_is_aeolia(struct irq_fwspec *fwspec);
+
+ extern struct irq_domain *x86_vector_domain;
+
+diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c
+index c132daabe615..af7339aaa843 100644
+--- a/arch/x86/kernel/apic/vector.c
++++ b/arch/x86/kernel/apic/vector.c
+@@ -676,6 +676,15 @@ int x86_fwspec_is_hpet(struct irq_fwspec *fwspec)
+ return 0;
+ }
+
++int x86_fwspec_is_aeolia(struct irq_fwspec *fwspec)
++{
++ if (is_fwnode_irqchip(fwspec->fwnode)) {
++ const char *fwname = fwnode_get_name(fwspec->fwnode);
++ return fwname && !strncmp(fwname, "Aeolia-MSI", 10);
++ }
++ return 0;
++}
++
+ static int x86_vector_select(struct irq_domain *d, struct irq_fwspec *fwspec,
+ enum irq_domain_bus_token bus_token)
+ {
+@@ -687,7 +696,7 @@ static int x86_vector_select(struct irq_domain *d, struct irq_fwspec *fwspec,
+ if (apic->apic_id_valid(32768))
+ return 0;
+
+- return x86_fwspec_is_ioapic(fwspec) || x86_fwspec_is_hpet(fwspec);
++ return x86_fwspec_is_ioapic(fwspec) || x86_fwspec_is_hpet(fwspec) || x86_fwspec_is_aeolia(fwspec);
+ }
+
+ static const struct irq_domain_ops x86_vector_domain_ops = {
+diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
+index 5ceaaabb4f9d..f20dc0c7b78f 100644
+--- a/drivers/iommu/amd/iommu.c
++++ b/drivers/iommu/amd/iommu.c
+@@ -3294,6 +3294,8 @@ static int irq_remapping_select(struct irq_domain *d, struct irq_fwspec *fwspec,
+ devid = get_ioapic_devid(fwspec->param[0]);
+ else if (x86_fwspec_is_hpet(fwspec))
+ devid = get_hpet_devid(fwspec->param[0]);
++ else if(x86_fwspec_is_aeolia(fwspec))
++ devid = fwspec->param[0];
+
+ if (devid < 0)
+ return 0;
+diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
+index 5fe5e84fab40..288b49cc49a5 100644
+--- a/drivers/pci/probe.c
++++ b/drivers/pci/probe.c
+@@ -2638,6 +2638,12 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
+ nr++;
+
+ for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
++ if (PCI_SLOT(devfn) != AEOLIA_SLOT_NUM &&
++ pci_bus_read_dev_vendor_id(bus, devfn + fn, &l, 60*1000) &&
++ (l & 0xffff) == PCI_VENDOR_ID_SONY) {
++ continue;
++ }
++
+ dev = pci_scan_single_device(bus, devfn + fn);
+ if (dev) {
+ if (!pci_dev_is_added(dev))
+diff --git a/drivers/ps4/ps4-apcie.c b/drivers/ps4/ps4-apcie.c
+index d5e87d1ee74e..d9c36f7715bb 100644
+--- a/drivers/ps4/ps4-apcie.c
++++ b/drivers/ps4/ps4-apcie.c
+@@ -219,28 +219,47 @@ static struct msi_domain_info apcie_msi_domain_info = {
+
+ static struct irq_domain *apcie_create_irq_domain(struct apcie_dev *sc)
+ {
+- struct irq_domain *domain;
++ struct msi_domain_info *domain_info;
++ struct irq_domain *domain, *parent;
+ struct fwnode_handle *fn;
++ struct irq_fwspec fwspec;
+
+ sc_dbg("apcie_create_irq_domain\n");
+ if (x86_vector_domain == NULL)
+ return NULL;
+
+- apcie_msi_domain_info.chip_data = (void *)sc;
+- apcie_msi_domain_info.flags |= MSI_FLAG_MULTI_PCI_MSI;
+- apcie_msi_controller.name = "IR-Aeolia-MSI";
++ domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
++ if (!domain_info)
++ return NULL;
++
++ *domain_info = apcie_msi_domain_info;
++ domain_info->chip_data = (void *)sc;
+
+- fn = irq_domain_alloc_named_fwnode(apcie_msi_controller.name);
+- if (!fn)
++ fn = irq_domain_alloc_named_id_fwnode(apcie_msi_controller.name, pci_dev_id(sc->pdev));
++ if (!fn) {
++ kfree(domain_info);
+ return NULL;
+- domain = pci_msi_create_irq_domain(fn, &apcie_msi_domain_info,
+- x86_vector_domain);
++ }
++
++ fwspec.fwnode = fn;
++ fwspec.param_count = 1;
++
++ // It should be correct to put the pci device id in here
++ fwspec.param[0] = pci_dev_id(sc->pdev);
+
++ parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_ANY);
++ if (!parent) {
++ parent = x86_vector_domain;
++ } else {
++ apcie_msi_domain_info.flags |= MSI_FLAG_MULTI_PCI_MSI;
++ apcie_msi_controller.name = "IR-Aeolia-MSI";
++ }
++
++ domain = msi_create_irq_domain(fn, domain_info, parent);
+ if (!domain) {
+ irq_domain_free_fwnode(fn);
++ kfree(domain_info);
+ pr_warn("Failed to initialize IR-Aeolia-MSI irqdomain.\n");
+- } else {
+- domain->flags |= IRQ_DOMAIN_MSI_NOMASK_QUIRK;
+ }
+
+ return domain;
+@@ -283,6 +302,7 @@ int apcie_assign_irqs(struct pci_dev *dev, int nvec)
+ info.type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
+ /* IRQs "come from" function 4 as far as the IOMMU/system see */
+ //info.msi_dev = sc->pdev;
++ info.desc = alloc_msi_entry(&dev->dev, nvec, NULL);
+ /* Our hwirq number is function << 8 plus subfunction.
+ * Subfunction is usually 0 and implicitly increments per hwirq,
+ * but can also be 0xff to indicate that this is a shared IRQ. */
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0010-feat-working-state-broken-gpu.patch b/device/testing/linux-sony-ps4/0010-feat-working-state-broken-gpu.patch
new file mode 100644
index 0000000000000000000000000000000000000000..9ab7f79dd84fef826d557be39f891e9c1827fc1f
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0010-feat-working-state-broken-gpu.patch
@@ -0,0 +1,680 @@
+From 92a4a84d51795f0a765a0dc6b3db08ca60b74805 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Fri, 24 Dec 2021 22:40:25 +0100
+Subject: [PATCH 10/22] feat: working state, broken gpu
+
+---
+ drivers/ata/ahci.c | 289 ++++++++++++++++++++++++++
+ drivers/ata/ahci.h | 28 +++
+ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 6 +
+ drivers/iommu/amd/iommu.c | 1 +
+ drivers/ps4/aeolia.h | 8 +-
+ drivers/ps4/ps4-apcie.c | 95 ++++++---
+ 6 files changed, 392 insertions(+), 35 deletions(-)
+
+diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
+index 149ee16fd022..5ba41c18b295 100644
+--- a/drivers/ata/ahci.c
++++ b/drivers/ata/ahci.c
+@@ -34,6 +34,10 @@
+ #include <linux/io-64-nonatomic-lo-hi.h>
+ #include "ahci.h"
+
++#ifdef CONFIG_X86_PS4
++#include <asm/ps4.h>
++#endif
++
+ #define DRV_NAME "ahci"
+ #define DRV_VERSION "3.0"
+
+@@ -605,6 +609,11 @@ static const struct pci_device_id ahci_pci_tbl[] = {
+ /* Enmotus */
+ { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
+
++ /* Sony (PS4) */
++ { PCI_VDEVICE(SONY, PCI_DEVICE_ID_SONY_AEOLIA_AHCI), board_ahci },
++ { PCI_VDEVICE(SONY, PCI_DEVICE_ID_SONY_BELIZE_AHCI), board_ahci },
++ { PCI_VDEVICE(SONY, PCI_DEVICE_ID_SONY_BAIKAL_AHCI), board_ahci },
++
+ /* Loongson */
+ { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
+
+@@ -954,6 +963,23 @@ static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
+ if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
+ return 0;
+
++ #ifdef CONFIG_X86_PS4
++ if (pdev->vendor == PCI_VENDOR_ID_SONY) {
++ rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(31));
++ if (rc) {
++ dev_err(&pdev->dev, "31-bit DMA enable failed\n");
++ return rc;
++ }
++ rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(31));
++ if (rc) {
++ dev_err(&pdev->dev,
++ "31-bit consistent DMA enable failed\n");
++ return rc;
++ }
++ return 0;
++ }
++ #endif
++
+ rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
+ if (rc)
+ dev_err(&pdev->dev, "DMA enable failed\n");
+@@ -1574,6 +1600,12 @@ static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
+ {
+ int nvec;
+
++ #ifdef CONFIG_X86_PS4
++ if (pdev->vendor == PCI_VENDOR_ID_SONY) {
++ return apcie_assign_irqs(pdev, n_ports);
++ }
++ #endif
++
+ if (hpriv->flags & AHCI_HFLAG_NO_MSI)
+ return -ENODEV;
+
+@@ -1700,6 +1732,13 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
+
+ WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
+
++
++ #ifdef CONFIG_X86_PS4
++ /* This will return negative on non-PS4 platforms */
++ if (apcie_status() == 0)
++ return -EPROBE_DEFER;
++ #endif
++
+ ata_print_version_once(&pdev->dev, DRV_VERSION);
+
+ /* The AHCI driver can only drive the SATA ports, the PATA driver
+@@ -1947,8 +1986,258 @@ static void ahci_remove_one(struct pci_dev *pdev)
+ NULL);
+ pm_runtime_get_noresume(&pdev->dev);
+ ata_pci_remove_one(pdev);
++
++ #ifdef CONFIG_X86_PS4
++ if (pdev->vendor == PCI_VENDOR_ID_SONY) {
++ apcie_free_irqs(pdev->irq, 1);
++ }
++ #endif
++}
++
++#ifdef CONFIG_X86_PS4
++void bpcie_sata_phy_init(struct device *dev, struct ahci_controller *ctlr)
++{
++ int i;
++ u32 v;
++ u32 v2;
++ bool is_phy_gen_3;
++ unsigned int trace_length;
++
++ dev_info(dev, "Belize SATA PHY init\n");
++
++ for (i = 0; i < 100; i++) {
++ udelay(10000);
++ }
++
++ //step 1
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x81);
++
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffff00) | 1);
++
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0xa5);
++
++ //step 2
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++
++ if (ctlr->dev_id == 0x90ca104d || ctlr->dev_id == 0x909f104d || ctlr->dev_id == 0x90d9104d) {
++ is_phy_gen_3 = false;
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, v & 0xfffff3ff);
++ } else {
++ u32 v2 = bpcie_ahci_read(ctlr->r_mem, 0);
++ if ((v2 & 0xf00000) != 0x300000) {
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff3ff) | 0x400);
++ is_phy_gen_3 = false;
++ } else {
++ dev_info(dev,"PHY SET GEN3\n");
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff3ff) | 0x800);
++ is_phy_gen_3 = true;
++ }
++ }
++
++ //--- step 3 ---
++ if (ctlr->trace_len == 0) {
++ trace_length = 6;
++ } else {
++ trace_length = ctlr->trace_len & 0x1f;
++ if (trace_length >= 0x13) {
++ trace_length = 6;
++ }
++ }
++
++ dev_info(dev,"Belize SATA PHY Trace length : %d\n",trace_length);
++
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0xa3);
++
++ //--- step 4 ---
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff3ff) | 0x800);
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0xd0);
++
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff800) | 0x441);
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0xe1);
++
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffff8f) | 0x60);
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0xd0);
++
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffff3fff) | 0x8000);
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0xf1);
++
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff3ff) | 0x400);
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x48);
++
++ //--- step 5 ---
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, 0x62d8);
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0xe);
++
++ //--- step 6 ---
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, v & 0xffffdfff);
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8d);
++
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, v | 1);
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8f);
++
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, v | 1);
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x91);
++
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, v | 1);
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8d);
++
++ //--- step 7 ---
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ if (trace_length >= 0xe) {
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffffc1) | 0x28);
++ } else {
++ if (trace_length < 0xb) {
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffffc1) | 8);
++ } else {
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffffc1) | 0x10);
++ }
++ }
++
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8f);
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffffc1) | 0x12);
++
++ //--- step 8 ---
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x91);
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ if (trace_length < 5) {
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffffc1) | 0x24);
++ } else {
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffffc1) | 0x2a);
++ }
++
++ //--- step 9 ---
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0xff);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, 1);
++
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x97);
++
++ //--- step 10 ---
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ if (is_phy_gen_3) {
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffff80) | 0xd3);
++ } else {
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffff80) | 0xee);
++ }
++
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x95);
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffff00) | 0xee);
++
++ //--- step 11 ---
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0xff);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, 0);
++
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8d);
++
++ //--- step 12 ---
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ if (trace_length < 0xe) {
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff87f) | 0x900);
++ } else {
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff87f) | 0xe00);
++ }
++
++ //--- step 13 ---
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8f);
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff07f) | 0x900);
++
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x91);
++
++ //--- step 14 ---
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ if (is_phy_gen_3) {
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff87f) | 0xd00);
++ } else {
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xfffff87f) | 0xe80);
++ }
++
++ //--- step 15 ---
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 200);
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, v & 0xffffefff);
++
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 10);
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, v & 0xffffefff);
++
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x82);
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, v | 0x1000);
++
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0xc9);
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, v | 0x1000);
++
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x84);
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffffffc0) | 0xc);
++
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8d);
++
++ //--- step 16 ---
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ v = v & 0xffff0fff;
++ if (trace_length < 0xe) {
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, v | 0x8000);
++ } else {
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, v);
++ }
++
++ //--- step 17 ---
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0x8f);
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++ bpcie_ahci_write(ctlr->r_mem, 0x17c, (v & 0xffff0fff) | 0x8000);
++
++ //--- step 18 ---
++ bpcie_ahci_write(ctlr->r_mem, 0xa0, 0);
++ v = bpcie_ahci_read(ctlr->r_mem, 0xa4);
++ bpcie_ahci_write(ctlr->r_mem, 0xa4, v | 0x40);
++
++ //--- step 19 ---
++ if (ctlr->dev_id != 0x909f104d && ctlr->dev_id != 0x90ca104d && ctlr->dev_id != 0x90d9104d) {
++ v2 = 0x73000000;
++ } else {
++ v2 = 0x30000000;
++ }
++
++ //--- step 20 ---
++ bpcie_ahci_write(ctlr->r_mem, 0xa0, 4);
++ v = bpcie_ahci_read(ctlr->r_mem, 0xa4);
++ bpcie_ahci_write(ctlr->r_mem, 0xa4, (v & 0x88ffffff) | v2);
++
++ //--- step 21 ---
++ v = bpcie_ahci_read(ctlr->r_mem, 0xa4);
++
++ //--- step 22 ---
++ for (i = 0; i < 100; i++) {
++ udelay(10000);
++ }
++
++ //--- step 23 ---
++ bpcie_ahci_write(ctlr->r_mem, 0x178, 0xf9);
++ v = bpcie_ahci_read(ctlr->r_mem, 0x17c);
++
++ if (is_phy_gen_3) {
++ dev_info(dev,"Align 90=0x%02x\n",v & 0x7f);
++ }
++ //done!
+ }
+
++EXPORT_SYMBOL_GPL(bpcie_sata_phy_init);
++#endif
++
+ module_pci_driver(ahci_pci_driver);
+
+ MODULE_AUTHOR("Jeff Garzik");
+diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
+index 60ae707a88cc..efdfac788727 100644
+--- a/drivers/ata/ahci.h
++++ b/drivers/ata/ahci.h
+@@ -447,4 +447,32 @@ static inline int ahci_nr_ports(u32 cap)
+ return (cap & 0x1f) + 1;
+ }
+
++#ifdef CONFIG_X86_PS4
++struct f_resource{
++ u64 resource_i_ptr;
++ u64 r_bustag;
++ void __iomem * r_bushandle;
++};
++
++struct ahci_controller{
++ void *dev;
++ int dev_id;
++ struct f_resource *r_mem;
++ u32 trace_len;
++};
++
++void bpcie_sata_phy_init(struct device *dev, struct ahci_controller *ctlr);
++
++static inline void bpcie_ahci_write(struct f_resource *r_mem, u32 offset, u32 val) {
++ iowrite32(val, r_mem->r_bushandle + offset);
++}
++
++static inline u32 bpcie_ahci_read(struct f_resource *r_mem, u32 offset) {
++ return ioread32(r_mem->r_bushandle + offset);
++}
++#endif
++
++
++
++
+ #endif /* _AHCI_H */
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+index 752b66d7d0df..5e249922a72a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+@@ -1068,6 +1068,10 @@ static int gmc_v7_0_sw_init(void *handle)
+ if (r)
+ return r;
+
++
++ dev_info(adev->dev, "Done gart\n");
++
++
+ /*
+ * number of VMs
+ * VMID 0 is reserved for System
+@@ -1093,6 +1097,8 @@ static int gmc_v7_0_sw_init(void *handle)
+ return -ENOMEM;
+ atomic_set(&adev->gmc.vm_fault_info_updated, 0);
+
++ dev_info(adev->dev, "Done init\n");
++
+ return 0;
+ }
+
+diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
+index f20dc0c7b78f..4d36261e88a9 100644
+--- a/drivers/iommu/amd/iommu.c
++++ b/drivers/iommu/amd/iommu.c
+@@ -3300,6 +3300,7 @@ static int irq_remapping_select(struct irq_domain *d, struct irq_fwspec *fwspec,
+ if (devid < 0)
+ return 0;
+
++ pr_err("Remapping Selected: %x\n", devid);
+ iommu = amd_iommu_rlookup_table[devid];
+ return iommu && iommu->ir_domain == d;
+ }
+diff --git a/drivers/ps4/aeolia.h b/drivers/ps4/aeolia.h
+index 13df4b9a4fef..5319822ca818 100644
+--- a/drivers/ps4/aeolia.h
++++ b/drivers/ps4/aeolia.h
+@@ -151,11 +151,11 @@ struct apcie_dev {
+ struct apcie_icc_dev icc;
+ };
+
+-#define sc_err(...) dev_err(&sc->pdev->dev, __VA_ARGS__)
+-#define sc_warn(...) dev_warn(&sc->pdev->dev, __VA_ARGS__)
+-#define sc_notice(...) dev_notice(&sc->pdev->dev, __VA_ARGS__)
++#define sc_err(...) dev_info(&sc->pdev->dev, __VA_ARGS__)
++#define sc_warn(...) dev_info(&sc->pdev->dev, __VA_ARGS__)
++#define sc_notice(...) dev_info(&sc->pdev->dev, __VA_ARGS__)
+ #define sc_info(...) dev_info(&sc->pdev->dev, __VA_ARGS__)
+-#define sc_dbg(...) dev_dbg(&sc->pdev->dev, __VA_ARGS__)
++#define sc_dbg(...) dev_info(&sc->pdev->dev, __VA_ARGS__)
+
+ static inline int apcie_irqnum(struct apcie_dev *sc, int index)
+ {
+diff --git a/drivers/ps4/ps4-apcie.c b/drivers/ps4/ps4-apcie.c
+index d9c36f7715bb..f4e3a380d591 100644
+--- a/drivers/ps4/ps4-apcie.c
++++ b/drivers/ps4/ps4-apcie.c
+@@ -18,6 +18,11 @@
+
+ #include "aeolia.h"
+
++
++#define MSI_DATA_VECTOR_SHIFT 0
++#define MSI_DATA_VECTOR(v) (((u8)v) << MSI_DATA_VECTOR_SHIFT)
++#define MSI_DATA_VECTOR_MASK 0xffffff00
++
+ /* #define QEMU_HACK_NO_IOMMU */
+
+ /* Number of implemented MSI registers per function */
+@@ -63,12 +68,20 @@ static void apcie_config_msi(struct apcie_dev *sc, u32 func, u32 subfunc,
+
+ glue_clear_mask(sc, APCIE_REG_MSI_CONTROL, APCIE_REG_MSI_CONTROL_ENABLE);
+ /* Unknown */
++ sc_dbg("glue_write32 to offset, value (%08x, %08x, %08x)\n", sc->bar4, APCIE_REG_MSI(0x8), 0xffffffff);
+ glue_write32(sc, APCIE_REG_MSI(0x8), 0xffffffff);
+ /* Unknown */
++ sc_dbg("glue_write32 to offset, value (%08x, %08x, %08x)\n", sc->bar4, APCIE_REG_MSI(0xc + (func << 2)), 0xB7FFFF00 + func * 16);
+ glue_write32(sc, APCIE_REG_MSI(0xc + (func << 2)), 0xB7FFFF00 + func * 16);
++
++ sc_dbg("glue_write32 to offset, value (%08x, %08x, %08x)\n", sc->bar4, APCIE_REG_MSI_ADDR(func), addr);
+ glue_write32(sc, APCIE_REG_MSI_ADDR(func), addr);
+ /* Unknown */
++
++ sc_dbg("glue_write32 to offset, value (%08x, %08x, %08x)\n", sc->bar4, APCIE_REG_MSI(0xcc + (func << 2)), 0);
+ glue_write32(sc, APCIE_REG_MSI(0xcc + (func << 2)), 0);
++
++ sc_dbg("glue_write32 to offset, value (%08x, %08x, %08x)\n", sc->bar4, APCIE_REG_MSI_DATA_HI(func), data & 0xffe0);
+ glue_write32(sc, APCIE_REG_MSI_DATA_HI(func), data & 0xffe0);
+
+ if (func < 4) {
+@@ -84,6 +97,8 @@ static void apcie_config_msi(struct apcie_dev *sc, u32 func, u32 subfunc,
+ } else {
+ offset = 0xa0 + ((func - 5) << 4) + (subfunc << 2);
+ }
++
++ sc_dbg("glue_write32 to offset, value (%08x, %08x, %08x)\n", sc->bar4, APCIE_REG_MSI_DATA_LO(offset), data & 0x1f);
+ glue_write32(sc, APCIE_REG_MSI_DATA_LO(offset), data & 0x1f);
+
+ if (func == AEOLIA_FUNC_ID_PCIE)
+@@ -149,9 +164,17 @@ static void apcie_msi_calc_mask(struct irq_data *data) {
+ static void apcie_irq_msi_compose_msg(struct irq_data *data,
+ struct msi_msg *msg)
+ {
+- __irq_msi_compose_msg(irqd_cfg(data), msg, false);
+-}
++ struct irq_cfg *cfg = irqd_cfg(data);
+
++ memset(msg, 0, sizeof(*msg));
++ msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
++ msg->address_lo = 0xfee00000;// Just do it like this for now
++
++ // I know this is absolute horseshit, but it matches a known working kernel
++ msg->data = data->irq - 1;
++
++ pr_err("apcie_irq_msi_compose_msg\n");
++}
+
+ static struct irq_chip apcie_msi_controller = {
+ .name = "Aeolia-MSI",
+@@ -162,7 +185,7 @@ static struct irq_chip apcie_msi_controller = {
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
+ .irq_compose_msi_msg = apcie_irq_msi_compose_msg,
+ .irq_write_msi_msg = apcie_msi_write_msg,
+- .flags = IRQCHIP_SKIP_SET_WAKE,
++ .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_AFFINITY_PRE_STARTUP,
+ };
+
+ static irq_hw_number_t apcie_msi_get_hwirq(struct msi_domain_info *info,
+@@ -176,7 +199,7 @@ static int apcie_msi_init(struct irq_domain *domain,
+ irq_hw_number_t hwirq, msi_alloc_info_t *arg)
+ {
+ struct irq_data *data;
+- pr_devel("apcie_msi_init(%p, %p, %d, 0x%lx, %p)\n", domain, info, virq, hwirq, arg);
++ pr_err("apcie_msi_init(%p, %p, %d, 0x%lx, %p)\n", domain, info, virq, hwirq, arg);
+
+ data = irq_domain_get_irq_data(domain, virq);
+ irq_domain_set_info(domain, virq, hwirq, info->chip, info->chip_data,
+@@ -188,23 +211,25 @@ static int apcie_msi_init(struct irq_domain *domain,
+ static void apcie_msi_free(struct irq_domain *domain,
+ struct msi_domain_info *info, unsigned int virq)
+ {
+- pr_devel("apcie_msi_free(%d)\n", virq);
++ pr_err("apcie_msi_free(%d)\n", virq);
+ }
+
+-int apcie_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
+- msi_alloc_info_t *arg)
++
++static void apcie_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
+ {
+- init_irq_alloc_info(arg, NULL);
++ arg->desc = desc;
++ struct pci_dev* device = msi_desc_to_pci_dev(desc);
+
+- arg->type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
+- arg->flags |= MSI_FLAG_MULTI_PCI_MSI;
++ arg->hwirq = PCI_FUNC(device->devfn) << 8;
+
+- return 0;
++#ifndef QEMU_HACK_NO_IOMMU
++ arg->hwirq |= 0xFF;
++#endif
+ }
+
+ static struct msi_domain_ops apcie_msi_domain_ops = {
+ .get_hwirq = apcie_msi_get_hwirq,
+- .msi_prepare = apcie_msi_prepare,
++ .set_desc = apcie_set_desc,
+ .msi_init = apcie_msi_init,
+ .msi_free = apcie_msi_free,
+ };
+@@ -219,7 +244,6 @@ static struct msi_domain_info apcie_msi_domain_info = {
+
+ static struct irq_domain *apcie_create_irq_domain(struct apcie_dev *sc)
+ {
+- struct msi_domain_info *domain_info;
+ struct irq_domain *domain, *parent;
+ struct fwnode_handle *fn;
+ struct irq_fwspec fwspec;
+@@ -228,19 +252,15 @@ static struct irq_domain *apcie_create_irq_domain(struct apcie_dev *sc)
+ if (x86_vector_domain == NULL)
+ return NULL;
+
+- domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
+- if (!domain_info)
+- return NULL;
+-
+- *domain_info = apcie_msi_domain_info;
+- domain_info->chip_data = (void *)sc;
++ apcie_msi_domain_info.chip_data = (void *)sc;
+
+ fn = irq_domain_alloc_named_id_fwnode(apcie_msi_controller.name, pci_dev_id(sc->pdev));
+ if (!fn) {
+- kfree(domain_info);
+ return NULL;
+ }
+
++ sc_dbg("devid = %d\n", pci_dev_id(sc->pdev));
++
+ fwspec.fwnode = fn;
+ fwspec.param_count = 1;
+
+@@ -249,17 +269,19 @@ static struct irq_domain *apcie_create_irq_domain(struct apcie_dev *sc)
+
+ parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_ANY);
+ if (!parent) {
++ sc_dbg("no parent \n");
+ parent = x86_vector_domain;
++ } else if (parent == x86_vector_domain) {
++ sc_dbg("no parent \n");
+ } else {
+ apcie_msi_domain_info.flags |= MSI_FLAG_MULTI_PCI_MSI;
+ apcie_msi_controller.name = "IR-Aeolia-MSI";
+ }
+
+- domain = msi_create_irq_domain(fn, domain_info, parent);
++ domain = msi_create_irq_domain(fn, &apcie_msi_domain_info, parent);
+ if (!domain) {
+ irq_domain_free_fwnode(fn);
+- kfree(domain_info);
+- pr_warn("Failed to initialize IR-Aeolia-MSI irqdomain.\n");
++ pr_warn("Failed to initialize Aeolia-MSI irqdomain.\n");
+ }
+
+ return domain;
+@@ -302,15 +324,17 @@ int apcie_assign_irqs(struct pci_dev *dev, int nvec)
+ info.type = X86_IRQ_ALLOC_TYPE_PCI_MSI;
+ /* IRQs "come from" function 4 as far as the IOMMU/system see */
+ //info.msi_dev = sc->pdev;
+- info.desc = alloc_msi_entry(&dev->dev, nvec, NULL);
++ info.devid = pci_dev_id(sc->pdev);
++
++ int i, base = 0;
++ struct msi_desc *desc;
++ struct device* bare_dev = &sc->pdev->dev;
++
+ /* Our hwirq number is function << 8 plus subfunction.
+ * Subfunction is usually 0 and implicitly increments per hwirq,
+ * but can also be 0xff to indicate that this is a shared IRQ. */
+- //https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=3b9c1d377d67072d1d8a2373b4969103cca00dab
+ info.hwirq = PCI_FUNC(dev->devfn) << 8;
+
+- dev_dbg(&dev->dev, "apcie_assign_irqs(%d)\n", nvec);
+-
+ #ifndef QEMU_HACK_NO_IOMMU
+ info.flags = X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
+ if (!(apcie_msi_domain_info.flags & MSI_FLAG_MULTI_PCI_MSI)) {
+@@ -319,14 +343,23 @@ int apcie_assign_irqs(struct pci_dev *dev, int nvec)
+ }
+ #endif
+
++ desc = alloc_msi_entry(bare_dev, 1, NULL);
++
++ info.desc = desc;
++ info.data = sc;
++
++ dev_info(&dev->dev, "apcie_assign_irqs(%d) (%d)\n", nvec, info.hwirq);
++
+ ret = irq_domain_alloc_irqs(sc->irqdomain, nvec, NUMA_NO_NODE, &info);
+ if (ret >= 0) {
++ dev_info(&dev->dev, "irq_domain_alloc_irqs = %x\n", ret);
+ dev->irq = ret;
++ desc->irq = ret;
+ ret = nvec;
+ }
+
+ fail:
+- dev_dbg(&dev->dev, "apcie_assign_irqs returning %d\n", ret);
++ dev_info(&dev->dev, "apcie_assign_irqs returning %d\n", ret);
+ if (sc_dev)
+ pci_dev_put(sc_dev);
+ return ret;
+@@ -494,10 +527,10 @@ static int apcie_probe(struct pci_dev *dev, const struct pci_device_id *id) {
+
+ if ((ret = apcie_glue_init(sc)) < 0)
+ goto free_bars;
+- if ((ret = apcie_uart_init(sc)) < 0)
+- goto remove_glue;
++ //if ((ret = apcie_uart_init(sc)) < 0)
++ // goto remove_glue;
+ if ((ret = apcie_icc_init(sc)) < 0)
+- goto remove_uart;
++ goto remove_glue;
+
+ apcie_initialized = true;
+ return 0;
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0011-fix-incorrectly-applied-patches-and-missing-patches.patch b/device/testing/linux-sony-ps4/0011-fix-incorrectly-applied-patches-and-missing-patches.patch
new file mode 100644
index 0000000000000000000000000000000000000000..f841971d2a19c4582d068f036774efaba7163a91
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0011-fix-incorrectly-applied-patches-and-missing-patches.patch
@@ -0,0 +1,126 @@
+From ed61a42f4a35bf12c7a78642f7d814f50b936f57 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Sat, 25 Dec 2021 16:13:58 +0100
+Subject: [PATCH 11/22] fix: incorrectly applied patches and missing patches
+
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 +++
+ .../gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 ++
+ drivers/gpu/drm/radeon/cik.c | 14 +++++++-------
+ drivers/ps4/ps4-apcie.c | 1 +
+ 4 files changed, 13 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index d81187445ebe..8513dd006ad5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -1400,11 +1400,14 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
+ (adev->asic_type == CHIP_GLADIUS)) {
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
+ err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
++ if (err)
+ {
+ pr_err("gfx7: Failed to open firmware \"%s\"\n", fw_name);
+ goto out;
+ }
++
+ err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
++ if (err)
+ {
+ pr_err("gfx7: Failed to validate ucode firmware \"%s\"\n", fw_name);
+ goto out;
+diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+index d88513d0aca0..0ddcd498a68b 100644
+--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
++++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+@@ -1860,6 +1860,8 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
+
+ switch (dev->device_info->asic_family) {
+ /* HWS is not available on Hawaii. */
++ case CHIP_LIVERPOOL:
++ case CHIP_GLADIUS:
+ case CHIP_HAWAII:
+ /* HWS depends on CWSR for timely dequeue. CWSR is not
+ * available on Tonga.
+diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
+index f6ca400c006f..a0b83b91fdac 100644
+--- a/drivers/gpu/drm/radeon/cik.c
++++ b/drivers/gpu/drm/radeon/cik.c
+@@ -8251,7 +8251,7 @@ int cik_irq_process(struct radeon_device *rdev)
+ return IRQ_NONE;
+
+ rptr = rdev->ih.rptr;
+- DRM_DEBUG("cik_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
++ //DRM_DEBUG("cik_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
+
+ /* Order reading of wptr vs. reading of IH ring data */
+ rmb();
+@@ -8294,7 +8294,7 @@ int cik_irq_process(struct radeon_device *rdev)
+
+ break;
+ default:
+- DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
++ //DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+ break;
+ }
+ break;
+@@ -8324,7 +8324,7 @@ int cik_irq_process(struct radeon_device *rdev)
+
+ break;
+ default:
+- DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
++ //DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+ break;
+ }
+ break;
+@@ -8354,7 +8354,7 @@ int cik_irq_process(struct radeon_device *rdev)
+
+ break;
+ default:
+- DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
++ //DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+ break;
+ }
+ break;
+@@ -8384,7 +8384,7 @@ int cik_irq_process(struct radeon_device *rdev)
+
+ break;
+ default:
+- DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
++ //DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+ break;
+ }
+ break;
+@@ -8414,7 +8414,7 @@ int cik_irq_process(struct radeon_device *rdev)
+
+ break;
+ default:
+- DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
++ //DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+ break;
+ }
+ break;
+@@ -8444,7 +8444,7 @@ int cik_irq_process(struct radeon_device *rdev)
+
+ break;
+ default:
+- DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
++ //DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+ break;
+ }
+ break;
+diff --git a/drivers/ps4/ps4-apcie.c b/drivers/ps4/ps4-apcie.c
+index f4e3a380d591..fd27a4f38e61 100644
+--- a/drivers/ps4/ps4-apcie.c
++++ b/drivers/ps4/ps4-apcie.c
+@@ -527,6 +527,7 @@ static int apcie_probe(struct pci_dev *dev, const struct pci_device_id *id) {
+
+ if ((ret = apcie_glue_init(sc)) < 0)
+ goto free_bars;
++ // TODO (ps4patches): figure out why this dies a horrible and painful death.
+ //if ((ret = apcie_uart_init(sc)) < 0)
+ // goto remove_glue;
+ if ((ret = apcie_icc_init(sc)) < 0)
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0012-fix-radeon-drivers.patch b/device/testing/linux-sony-ps4/0012-fix-radeon-drivers.patch
new file mode 100644
index 0000000000000000000000000000000000000000..b1869b838ad0a8349106e16d07496f30cdd4e6eb
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0012-fix-radeon-drivers.patch
@@ -0,0 +1,188 @@
+From b009aedae1dd07fa3c761e7ddcc92071dd792853 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Tue, 28 Dec 2021 17:53:53 +0100
+Subject: [PATCH 12/22] fix: radeon drivers
+
+---
+ drivers/gpu/drm/radeon/cik.c | 30 +++++++++++++--------------
+ drivers/gpu/drm/radeon/ps4_bridge.c | 23 +++++++++++---------
+ drivers/gpu/drm/radeon/radeon.h | 2 +-
+ drivers/gpu/drm/radeon/radeon_audio.c | 2 +-
+ 4 files changed, 30 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
+index a0b83b91fdac..ce9799517ff4 100644
+--- a/drivers/gpu/drm/radeon/cik.c
++++ b/drivers/gpu/drm/radeon/cik.c
+@@ -1038,7 +1038,20 @@ static const u32 kalindi_rlc_save_restore_register_list[] =
+ (0x0e00 << 16) | (0x9600 >> 2),
+ };
+
+-static const u32 liverpool_rlc_save_restore_register_li
++static const u32 bonaire_golden_spm_registers[] =
++{
++ 0x30800, 0xe0ffffff, 0xe0000000
++};
++
++static const u32 bonaire_golden_common_registers[] =
++{
++ 0xc770, 0xffffffff, 0x00000800,
++ 0xc774, 0xffffffff, 0x00000800,
++ 0xc798, 0xffffffff, 0x00007fbf,
++ 0xc79c, 0xffffffff, 0x00007faf
++};
++
++static const u32 liverpool_rlc_save_restore_register_list[] =
+ {
+ (0x0600 << 16) | 0x263d,
+ 0x00000000,
+@@ -1453,19 +1466,6 @@ static const u32 liverpool_rlc_save_restore_register_li
+ (0x0e00 << 16) | 0x230d,
+ };
+
+-static const u32 bonaire_golden_spm_registers[] =
+-{
+- 0x30800, 0xe0ffffff, 0xe0000000
+-};
+-
+-static const u32 bonaire_golden_common_registers[] =
+-{
+- 0xc770, 0xffffffff, 0x00000800,
+- 0xc774, 0xffffffff, 0x00000800,
+- 0xc798, 0xffffffff, 0x00007fbf,
+- 0xc79c, 0xffffffff, 0x00007faf
+-};
+-
+ static const u32 bonaire_golden_registers[] =
+ {
+ 0x3354, 0x00000333, 0x00000333,
+@@ -1616,7 +1616,7 @@ static const u32 liverpool_golden_common_registers[] =
+ 0x5004, 0x00002000, 0x00002000, /* GARLIC_FLUSH_CNTL */
+ };
+
+-onst u32 liverpool_golden_registers[] =
++static const u32 liverpool_golden_registers[] =
+ {
+ 0xc420, 0xffffffff, 0xfffffffc, /* RLC_CGTT_MGCG_OVERRIDE */
+ 0x30800, 0xffffffff, 0xe0000000, /* GRBM_GFX_INDEX */
+diff --git a/drivers/gpu/drm/radeon/ps4_bridge.c b/drivers/gpu/drm/radeon/ps4_bridge.c
+index 1c1cb0b4dabb..6f6e354e182d 100644
+--- a/drivers/gpu/drm/radeon/ps4_bridge.c
++++ b/drivers/gpu/drm/radeon/ps4_bridge.c
+@@ -13,11 +13,14 @@
+
+ #include <asm/ps4.h>
+
++#include <drm/drm_bridge.h>
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_crtc_helper.h>
+ #include <drm/drm_atomic_helper.h>
+ #include <drm/drm_edid.h>
+-#include <drm/drmP.h>
++#include <drm/drm_print.h>
++
++#include <linux/pci.h>
+
+ #include "radeon_mode.h"
+ #include "ObjectID.h"
+@@ -95,7 +98,6 @@
+ # define HDCPEN_ENC_EN 0x03
+ # define HDCPEN_ENC_DIS 0x05
+
+-#define PCI_VENDOR_ID_AMD 0x1002
+ #define PCI_DEVICE_ID_CUH_11XX 0x9920
+ #define PCI_DEVICE_ID_CUH_12XX 0x9922
+ #define PCI_DEVICE_ID_CUH_2XXX 0x9923
+@@ -269,8 +271,8 @@ static inline struct radeon_ps4_bridge *
+ }
+
+ static void radeon_ps4_bridge_mode_set(struct drm_bridge *bridge,
+- struct drm_display_mode *mode,
+- struct drm_display_mode *adjusted_mode)
++ const struct drm_display_mode *mode,
++ const struct drm_display_mode *adjusted_mode)
+ {
+ struct radeon_ps4_bridge *mn_bridge = bridge_to_radeon_ps4_bridge(bridge);
+
+@@ -357,7 +359,7 @@ static void radeon_ps4_bridge_enable(struct drm_bridge *bridge)
+ struct radeon_ps4_bridge *mn_bridge = bridge_to_radeon_ps4_bridge(bridge);
+ struct drm_connector *connector = mn_bridge->connector;
+ struct drm_device *dev = connector->dev;
+- struct pci_dev *pdev = dev->pdev;
++ struct pci_dev *pdev = to_pci_dev(dev->dev);
+ u8 dp[3];
+
+ if (!mn_bridge->mode) {
+@@ -638,21 +640,21 @@ static const struct drm_display_mode mode_480p = {
+ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
+ 752, 800, 0, 480, 490, 492, 525, 0,
+ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
+- .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3
++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3
+ };
+ /* 4 - 1280x720@60Hz */
+ static const struct drm_display_mode mode_720p = {
+ DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
+ 1430, 1650, 0, 720, 725, 730, 750, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+- .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9
++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9
+ };
+ /* 16 - 1920x1080@60Hz */
+ static const struct drm_display_mode mode_1080p = {
+ DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
+ 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+- .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9
++ .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9
+ };
+
+ int radeon_ps4_bridge_get_modes(struct drm_connector *connector)
+@@ -669,7 +671,7 @@ int radeon_ps4_bridge_get_modes(struct drm_connector *connector)
+ //newmode = drm_mode_duplicate(dev, &mode_480p);
+ //drm_mode_probed_add(connector, newmode);
+
+- drm_mode_connector_update_edid_property(connector, NULL);
++ drm_connector_update_edid_property(connector, NULL);
+
+ return 0;
+ }
+@@ -718,7 +720,8 @@ int radeon_ps4_bridge_mode_valid(struct drm_connector *connector,
+ return MODE_OK;
+ }
+
+-static int radeon_ps4_bridge_attach(struct drm_bridge *bridge)
++static int radeon_ps4_bridge_attach(struct drm_bridge *bridge,
++ enum drm_bridge_attach_flags flags)
+ {
+ /* struct radeon_ps4_bridge *mn_bridge = bridge_to_radeon_ps4_bridge(bridge); */
+
+diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
+index 314fd436f3c9..05cbdf9e6dfe 100644
+--- a/drivers/gpu/drm/radeon/radeon.h
++++ b/drivers/gpu/drm/radeon/radeon.h
+@@ -2679,7 +2679,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
+ #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
+ #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
+ #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
+- (rdev->family == CHIP_MULLINS || \
++ (rdev->family == CHIP_MULLINS) || \
+ (rdev->family == CHIP_LIVERPOOL))
+
+ #define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \
+diff --git a/drivers/gpu/drm/radeon/radeon_audio.c b/drivers/gpu/drm/radeon/radeon_audio.c
+index ba877d0b73fd..3bca01e82835 100644
+--- a/drivers/gpu/drm/radeon/radeon_audio.c
++++ b/drivers/gpu/drm/radeon/radeon_audio.c
+@@ -244,7 +244,7 @@ int radeon_audio_init(struct radeon_device *rdev)
+
+ rdev->audio.enabled = true;
+
+- if (ASIC_IS_DCE83(rdev)) /* KB: 2 streams, 3 endpoints */
++ if (ASIC_IS_DCE83(rdev)) /* KB: 2 streams, 3 endpoints */
+ rdev->audio.num_pins = 3;
+ else if (ASIC_IS_DCE81(rdev)) /* KV: 4 streams, 7 endpoints */
+ rdev->audio.num_pins = 7;
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0013-fix-amdgpu-drivers.patch b/device/testing/linux-sony-ps4/0013-fix-amdgpu-drivers.patch
new file mode 100644
index 0000000000000000000000000000000000000000..d9ea4ab07b540d8af401142510b3de263cd1717d
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0013-fix-amdgpu-drivers.patch
@@ -0,0 +1,53 @@
+From 1b9c84e8afd63df84109a717f6fe3076f2990841 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Tue, 28 Dec 2021 18:49:46 +0100
+Subject: [PATCH 13/22] fix: amdgpu drivers
+
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 2 +-
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
+index 619d4c771176..dc517dc8ae94 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
+@@ -41,7 +41,7 @@ static void amdgpu_maybe_add_bridge(struct drm_connector *connector,
+ struct drm_encoder *encoder)
+ {
+ struct drm_device *dev = connector->dev;
+- struct amdgpu_device *adev = dev->dev_private;
++ struct amdgpu_device *adev = drm_to_adev(dev);
+
+ if (adev->asic_type == CHIP_LIVERPOOL || adev->asic_type == CHIP_GLADIUS) {
+ ps4_bridge_register(connector, encoder);
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+index 33987ecdc517..a41352dbe298 100644
+--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+@@ -262,7 +262,7 @@ static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector
+ unsigned lane_num, i, max_pix_clock;
+ struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ struct drm_device *dev = amdgpu_connector->base.dev;
+- struct amdgpu_device *adev = dev->dev_private;
++ struct amdgpu_device *adev = drm_to_adev(dev);
+
+ /* Liverpool is always connected to an encoder that needs 4 lanes */
+ if (adev->asic_type == CHIP_LIVERPOOL)
+diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+index 5bd8a782feb5..801178479719 100644
+--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
++++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+@@ -446,7 +446,7 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder)
+ struct amdgpu_connector_atom_dig *dig_connector;
+
+ struct drm_device *dev = encoder->dev;
+- struct amdgpu_device *adev = dev->dev_private;
++ struct amdgpu_device *adev = drm_to_adev(dev);
+
+ /* dp bridges are always DP */
+ if ((amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) ||
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0014-fix-re-add-legacy-bridge-functions.patch b/device/testing/linux-sony-ps4/0014-fix-re-add-legacy-bridge-functions.patch
new file mode 100644
index 0000000000000000000000000000000000000000..48df40352b52242c7e96f70dda8b60980274f168
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0014-fix-re-add-legacy-bridge-functions.patch
@@ -0,0 +1,191 @@
+From 3b2f7c502e713f75cd73793657eb58b55121d8c6 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Wed, 29 Dec 2021 14:16:57 +0100
+Subject: [PATCH 14/22] fix: re-add legacy bridge functions
+
+---
+ config | 2 +-
+ drivers/gpu/drm/amd/amdgpu/ps4_bridge.c | 20 +++++++------
+ drivers/gpu/drm/drm_crtc_helper.c | 37 +++++++++++++++++++++++++
+ 3 files changed, 50 insertions(+), 9 deletions(-)
+
+diff --git a/config b/config
+index 9b3e8c78ecf1..ceaac7d2d935 100644
+--- a/config
++++ b/config
+@@ -2262,7 +2262,7 @@ CONFIG_DRM_SCHED=y
+ CONFIG_DRM_AMDGPU=y
+ # CONFIG_DRM_AMDGPU_SI is not set
+ CONFIG_DRM_AMDGPU_CIK=y
+-CONFIG_DRM_AMDGPU_USERPTR=y
++# CONFIG_DRM_AMDGPU_USERPTR is not set
+
+ #
+ # ACP (Audio CoProcessor) Configuration
+diff --git a/drivers/gpu/drm/amd/amdgpu/ps4_bridge.c b/drivers/gpu/drm/amd/amdgpu/ps4_bridge.c
+index 86af15c134c4..d63ae6dddbb2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/ps4_bridge.c
++++ b/drivers/gpu/drm/amd/amdgpu/ps4_bridge.c
+@@ -11,6 +11,10 @@
+ * GNU General Public License for more details.
+ */
+
++
++// TODO (ps4patches): Make functions atomic,
++// https://lore.kernel.org/linux-arm-kernel/20211020181901.2114645-5-sam@ravnborg.org/
++
+ #include <asm/ps4.h>
+
+ #include <drm/drm_crtc.h>
+@@ -676,7 +680,7 @@ int ps4_bridge_get_modes(struct drm_connector *connector)
+ {
+ struct drm_device *dev = connector->dev;
+ struct drm_display_mode *newmode;
+- DRM_DEBUG_KMS("ps4_bridge_get_modes\n");
++ pr_info("ps4_bridge_get_modes\n");
+
+ newmode = drm_mode_duplicate(dev, &mode_1080p);
+ drm_mode_probed_add(connector, newmode);
+@@ -687,7 +691,7 @@ int ps4_bridge_get_modes(struct drm_connector *connector)
+ //drm_mode_probed_add(connector, newmode);
+
+ drm_connector_update_edid_property(connector, NULL);
+-
++
+ return 0;
+ }
+
+@@ -738,7 +742,6 @@ int ps4_bridge_mode_valid(struct drm_connector *connector,
+ static int ps4_bridge_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+ {
+- // TODO (ps4patches): Why is this in comments?
+ /* struct ps4_bridge *mn_bridge = bridge_to_ps4_bridge(bridge); */
+
+ return 0;
+@@ -761,16 +764,17 @@ int ps4_bridge_register(struct drm_connector *connector,
+
+ mn_bridge->encoder = encoder;
+ mn_bridge->connector = connector;
++ mn_bridge->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
+ mn_bridge->bridge.funcs = &ps4_bridge_funcs;
+- ret = drm_bridge_attach(mn_bridge->encoder, &mn_bridge->bridge, NULL, 0);
++
++ // TODO (ps4patches): This seems to be the new way of adding bridges
++ drm_bridge_add(&mn_bridge->bridge);
++
++ ret = drm_bridge_attach(mn_bridge->encoder, &mn_bridge->bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+ if (ret) {
+ DRM_ERROR("Failed to initialize bridge with drm\n");
+ return -EINVAL;
+ }
+
+- //encoder->bridge = &mn_bridge->bridge;
+- // TODO (ps4patches): This seems to be the new way of adding bridges
+- drm_bridge_add(&mn_bridge->bridge);
+-
+ return 0;
+ }
+diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
+index bff917531f33..17bf9a7ff546 100644
+--- a/drivers/gpu/drm/drm_crtc_helper.c
++++ b/drivers/gpu/drm/drm_crtc_helper.c
+@@ -162,10 +162,15 @@ drm_encoder_disable(struct drm_encoder *encoder)
+ if (!encoder_funcs)
+ return;
+
++ struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder);
++ drm_bridge_chain_disable(bridge);
++
+ if (encoder_funcs->disable)
+ (*encoder_funcs->disable)(encoder);
+ else if (encoder_funcs->dpms)
+ (*encoder_funcs->dpms)(encoder, DRM_MODE_DPMS_OFF);
++
++ drm_bridge_chain_post_disable(bridge);
+ }
+
+ static void __drm_helper_disable_unused_functions(struct drm_device *dev)
+@@ -322,6 +327,14 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
+ if (!encoder_funcs)
+ continue;
+
++ struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder);
++ ret = drm_bridge_chain_mode_fixup(bridge,
++ mode, adjusted_mode);
++ if (!ret) {
++ DRM_DEBUG_KMS("Bridge fixup failed\n");
++ goto done;
++ }
++
+ encoder_funcs = encoder->helper_private;
+ if (encoder_funcs->mode_fixup) {
+ if (!(ret = encoder_funcs->mode_fixup(encoder, mode,
+@@ -353,9 +366,14 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
+ if (!encoder_funcs)
+ continue;
+
++ struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder);
++ drm_bridge_chain_disable(bridge);
++
+ /* Disable the encoders as the first thing we do. */
+ if (encoder_funcs->prepare)
+ encoder_funcs->prepare(encoder);
++
++ drm_bridge_chain_post_disable(bridge);
+ }
+
+ drm_crtc_prepare_encoders(dev);
+@@ -382,6 +400,9 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
+ encoder->base.id, encoder->name, mode->name);
+ if (encoder_funcs->mode_set)
+ encoder_funcs->mode_set(encoder, mode, adjusted_mode);
++
++ struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder);
++ drm_bridge_chain_mode_set(bridge, mode, adjusted_mode);
+ }
+
+ /* Now enable the clocks, plane, pipe, and connectors that we set up. */
+@@ -396,8 +417,13 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
+ if (!encoder_funcs)
+ continue;
+
++ struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder);
++ drm_bridge_chain_pre_enable(bridge);
++
+ if (encoder_funcs->commit)
+ encoder_funcs->commit(encoder);
++
++ drm_bridge_chain_enable(bridge);
+ }
+
+ /* Calculate and store various constants which
+@@ -816,14 +842,25 @@ static int drm_helper_choose_encoder_dpms(struct drm_encoder *encoder)
+ /* Helper which handles bridge ordering around encoder dpms */
+ static void drm_helper_encoder_dpms(struct drm_encoder *encoder, int mode)
+ {
++ struct drm_bridge* bridge = drm_bridge_chain_get_first_bridge(encoder);
+ const struct drm_encoder_helper_funcs *encoder_funcs;
+
+ encoder_funcs = encoder->helper_private;
+ if (!encoder_funcs)
+ return;
+
++ if (mode == DRM_MODE_DPMS_ON)
++ drm_bridge_chain_pre_enable(bridge);
++ else
++ drm_bridge_chain_disable(bridge);
++
+ if (encoder_funcs->dpms)
+ encoder_funcs->dpms(encoder, mode);
++
++ if (mode == DRM_MODE_DPMS_ON)
++ drm_bridge_chain_enable(bridge);
++ else
++ drm_bridge_chain_post_disable(bridge);
+ }
+
+ static int drm_helper_choose_crtc_dpms(struct drm_crtc *crtc)
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0015-feat-potentially-added-belize-ahci-support-in-a-univ.patch b/device/testing/linux-sony-ps4/0015-feat-potentially-added-belize-ahci-support-in-a-univ.patch
new file mode 100644
index 0000000000000000000000000000000000000000..5841b97ae7835fee7c5bb6e81326c5d4cbad20d8
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0015-feat-potentially-added-belize-ahci-support-in-a-univ.patch
@@ -0,0 +1,644 @@
+From 00879e27dddefbe1c062f53b4eec0e9166780a2a Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Wed, 29 Dec 2021 15:43:55 +0100
+Subject: [PATCH 15/22] feat: potentially added belize ahci support in a
+ universal way
+
+---
+ drivers/usb/host/xhci-aeolia.c | 543 ++++++++++++++++-----------------
+ 1 file changed, 268 insertions(+), 275 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-aeolia.c b/drivers/usb/host/xhci-aeolia.c
+index a9b345284495..1401af61430c 100644
+--- a/drivers/usb/host/xhci-aeolia.c
++++ b/drivers/usb/host/xhci-aeolia.c
+@@ -25,8 +25,7 @@ static struct hc_driver __read_mostly xhci_aeolia_hc_driver;
+ #define NR_DEVICES 3
+
+ struct aeolia_xhci {
+- // TODO (ps4patches): Belize, enable in ahci commit
+- // struct ata_host *host;
++ struct ata_host *host;
+ int nr_irqs;
+ struct usb_hcd *hcd[NR_DEVICES];
+ };
+@@ -75,14 +74,8 @@ static int xhci_aeolia_probe_one(struct pci_dev *dev, int index)
+ hcd->rsrc_start = pci_resource_start(dev, 2 * index);
+ hcd->rsrc_len = pci_resource_len(dev, 2 * index);
+
+- /*
+- * TODO (ps4patches): Belize, enable in ahci commit
+ if (!devm_request_mem_region(&dev->dev, hcd->rsrc_start, hcd->rsrc_len,
+ driver->description)) {
+- */
+-
+- if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
+- driver->description)) {
+ dev_dbg(&dev->dev, "controller already in use\n");
+ retval = -EBUSY;
+ goto put_hcd;
+@@ -124,9 +117,7 @@ static int xhci_aeolia_probe_one(struct pci_dev *dev, int index)
+ unmap_registers:
+ iounmap(hcd->regs);
+ release_mem_region:
+- //
+- // devm_release_mem_region(&dev->dev, hcd->rsrc_start, hcd->rsrc_len);
+- release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
++ devm_release_mem_region(&dev->dev, hcd->rsrc_start, hcd->rsrc_len);
+ put_hcd:
+ usb_put_hcd(hcd);
+ dev_err(&dev->dev, "init %s(%d) fail, %d\n",
+@@ -147,226 +138,225 @@ static void xhci_aeolia_remove_one(struct pci_dev *dev, int index)
+ usb_remove_hcd(xhci->shared_hcd);
+ usb_remove_hcd(hcd);
+ usb_put_hcd(xhci->shared_hcd);
+- iounmap(hcd->regs);
++
++ // TODO (ps4patches): Does this really need to be disabled?
++ if(dev->device == PCI_DEVICE_ID_SONY_BELIZE_XHCI) {
++ iounmap(hcd->regs);
++ }
+ usb_put_hcd(hcd);
+ axhci->hcd[index] = NULL;
+ }
+
+-// TODO (ps4patches): Belize, enable in ahci commit
+-//#define DRV_VERSION "3.0"
+-//#define DRV_NAME "ahci"
+-//static const struct ata_port_info ahci_port_info = {
+-// .flags = AHCI_FLAG_COMMON,
+-// .pio_mask = ATA_PIO4,
+-// .udma_mask = ATA_UDMA6,
+-// .port_ops = &ahci_ops,
+-//};
+-//
+-//static struct scsi_host_template ahci_sht = {
+-// AHCI_SHT(DRV_NAME),
+-//};
+-//
+-//static bool bus_master;
+-//static int ahci_init_one(struct pci_dev *pdev)
+-//{
+-// struct f_resource* r_mem;
+-// struct ahci_controller* ctlr;
+-// struct aeolia_xhci *axhci = pci_get_drvdata(pdev);
+-// struct ata_port_info pi = ahci_port_info;
+-// const struct ata_port_info *ppi[] = { &pi, NULL };
+-// struct ahci_host_priv *hpriv;
+-// struct ata_host *host;
+-// int n_ports, i, rc;
+-// int ahci_pci_bar = 2;
+-// resource_size_t rsrc_start;
+-// resource_size_t rsrc_len;
+-//
+-// VPRINTK("ENTER\n");
+-//
+-// WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
+-//
+-// ata_print_version_once(&pdev->dev, DRV_VERSION);
+-//
+-// /*
+-// rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
+-// if (rc == -EBUSY)
+-// pcim_pin_device(pdev);
+-// if (rc)
+-// return rc;
+-// */
+-//
+-// hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
+-// //hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
+-// if (!hpriv)
+-// return -ENOMEM;
+-// hpriv->flags |= (unsigned long)pi.private_data;
+-//
+-// //hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
+-// rsrc_start = pci_resource_start(pdev, ahci_pci_bar);
+-// rsrc_len = pci_resource_len(pdev, ahci_pci_bar);
+-// //if (!request_mem_region(rsrc_start, rsrc_len, "xhci-ahci.mem")) {
+-// if (!devm_request_mem_region(&pdev->dev, rsrc_start, rsrc_len, "xhci-ahci.mem")) {
+-// dev_dbg(&pdev->dev, "controller already in use\n");
+-// rc = -EBUSY;
+-// goto put_hpriv;
+-// }
+-//
+-//
+-// hpriv->mmio = pci_ioremap_bar(pdev, ahci_pci_bar);
+-// if (hpriv->mmio == NULL) {
+-// dev_dbg(&pdev->dev, "error mapping memory\n");
+-// rc = -EFAULT;
+-// goto release_mem_region;
+-// }
+-//
+-// r_mem = kzalloc(sizeof(*r_mem), GFP_KERNEL);
+-// if (r_mem) {
+-// r_mem->r_bustag = 1;//mem
+-// r_mem->r_bushandle = hpriv->mmio;
+-//
+-// ctlr = kzalloc(sizeof(*ctlr), GFP_KERNEL);
+-// if (ctlr) {
+-// ctlr->r_mem = r_mem;
+-// ctlr->dev_id = 0; //or 0x90ca104d;
+-// ctlr->trace_len = 6;
+-// bpcie_sata_phy_init(&pdev->dev, ctlr);
+-// kfree(ctlr);
+-// }
+-// kfree(r_mem);
+-// }
+-// device_wakeup_enable(&pdev->dev);
+-//
+-// /* save initial config */
+-// ahci_save_initial_config(&pdev->dev, hpriv);
+-//
+-// /* prepare host */
+-// if (hpriv->cap & HOST_CAP_NCQ) {
+-// pi.flags |= ATA_FLAG_NCQ;
+-// /*
+-// * Auto-activate optimization is supposed to be
+-// * supported on all AHCI controllers indicating NCQ
+-// * capability, but it seems to be broken on some
+-// * chipsets including NVIDIAs.
+-// */
+-// if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
+-// pi.flags |= ATA_FLAG_FPDMA_AA;
+-//
+-// /*
+-// * All AHCI controllers should be forward-compatible
+-// * with the new auxiliary field. This code should be
+-// * conditionalized if any buggy AHCI controllers are
+-// * encountered.
+-// */
+-// pi.flags |= ATA_FLAG_FPDMA_AUX;
+-// }
+-//
+-// if (hpriv->cap & HOST_CAP_PMP)
+-// pi.flags |= ATA_FLAG_PMP;
+-//
+-// ahci_set_em_messages(hpriv, &pi);
+-//
+-// /* CAP.NP sometimes indicate the index of the last enabled
+-// * port, at other times, that of the last possible port, so
+-// * determining the maximum port number requires looking at
+-// * both CAP.NP and port_map.
+-// */
+-// n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
+-//
+-// host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
+-// if (!host) {
+-// rc = -ENOMEM;
+-// goto unmap_registers;
+-// }
+-// axhci->host = host;
+-// pci_set_drvdata(pdev, axhci);
+-//
+-// host->private_data = hpriv;
+-//
+-// {
+-// int index = 1;
+-// int irq = (axhci->nr_irqs > 1) ? (pdev->irq + index) : pdev->irq;
+-// hpriv->irq = irq;
+-// }
+-//
+-// if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
+-// host->flags |= ATA_HOST_PARALLEL_SCAN;
+-// else
+-// dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
+-//
+-// if (pi.flags & ATA_FLAG_EM)
+-// ahci_reset_em(host);
+-//
+-// for (i = 0; i < host->n_ports; i++) {
+-// struct ata_port *ap = host->ports[i];
+-//
+-// ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
+-// ata_port_pbar_desc(ap, ahci_pci_bar,
+-// 0x100 + ap->port_no * 0x80, "port");
+-//
+-// /* set enclosure management message type */
+-// if (ap->flags & ATA_FLAG_EM)
+-// ap->em_message_type = hpriv->em_msg_type;
+-//
+-//
+-// /* disabled/not-implemented port */
+-// if (!(hpriv->port_map & (1 << i)))
+-// ap->ops = &ata_dummy_port_ops;
+-// }
+-//
+-// rc = ahci_reset_controller(host);
+-// dev_dbg(&pdev->dev, "ahci_reset_controller returned %d\n", rc);
+-// if (rc)
+-// goto release_host;
+-//
+-// ahci_init_controller(host);
+-// ahci_print_info(host, "ATA");
+-//
+-// if (!bus_master) {
+-// pci_set_master(pdev);
+-// bus_master = true;
+-// }
+-//
+-// rc = ahci_host_activate(host, &ahci_sht);
+-// dev_dbg(&pdev->dev, "ahci_host_activate returned %d\n", rc);
+-// if (rc) {
+-// goto host_deactivate;
+-// }
+-//
+-// pm_runtime_put_noidle(&pdev->dev);
+-// return 0;
+-//
+-// host_deactivate:
+-// release_host:
+-// unmap_registers:
+-// iounmap(hpriv->mmio);
+-// release_mem_region:
+-//
+-// release_mem_region(rsrc_start, rsrc_len);
+-//
+-// // TODO (ps4patches): Belize, enable in ahci commit
+-// //devm_release_mem_region(&pdev->dev, rsrc_start, rsrc_len);
+-// put_hpriv:
+-// //kfree(hpriv);
+-// devm_kfree(&pdev->dev, hpriv);
+-// dev_err(&pdev->dev, "init %s fail, %d\n",
+-// pci_name(pdev), rc);
+-// return rc;
+-//}
+-//
+-//static void ahci_remove_one(struct pci_dev *pdev)
+-//{
+-// pm_runtime_get_noresume(&pdev->dev);
+-//
+-// struct aeolia_xhci *axhci = pci_get_drvdata(pdev);
+-// if (axhci && axhci->host) {
+-// ata_host_detach(axhci->host);
+-// struct ahci_host_priv *hpriv = axhci->host->private_data;
+-// if (hpriv) {
+-// iounmap(hpriv->mmio);
+-// }
+-// axhci->host = NULL;
+-// }
+-//}
++#define DRV_VERSION "3.0"
++#define DRV_NAME "ahci"
++static const struct ata_port_info ahci_port_info = {
++ .flags = AHCI_FLAG_COMMON,
++ .pio_mask = ATA_PIO4,
++ .udma_mask = ATA_UDMA6,
++ .port_ops = &ahci_ops,
++};
++
++static struct scsi_host_template ahci_sht = {
++ AHCI_SHT(DRV_NAME),
++};
++
++static bool bus_master;
++static int ahci_init_one(struct pci_dev *pdev)
++{
++ struct f_resource* r_mem;
++ struct ahci_controller* ctlr;
++ struct aeolia_xhci *axhci = pci_get_drvdata(pdev);
++ struct ata_port_info pi = ahci_port_info;
++ const struct ata_port_info *ppi[] = { &pi, NULL };
++ struct ahci_host_priv *hpriv;
++ struct ata_host *host;
++ int n_ports, i, rc;
++ int ahci_pci_bar = 2;
++ resource_size_t rsrc_start;
++ resource_size_t rsrc_len;
++
++ VPRINTK("ENTER\n");
++
++ WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
++
++ ata_print_version_once(&pdev->dev, DRV_VERSION);
++
++ /*
++ rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
++ if (rc == -EBUSY)
++ pcim_pin_device(pdev);
++ if (rc)
++ return rc;
++ */
++
++ hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
++ //hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
++ if (!hpriv)
++ return -ENOMEM;
++ hpriv->flags |= (unsigned long)pi.private_data;
++
++ //hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
++ rsrc_start = pci_resource_start(pdev, ahci_pci_bar);
++ rsrc_len = pci_resource_len(pdev, ahci_pci_bar);
++ //if (!request_mem_region(rsrc_start, rsrc_len, "xhci-ahci.mem")) {
++ if (!devm_request_mem_region(&pdev->dev, rsrc_start, rsrc_len, "xhci-ahci.mem")) {
++ dev_dbg(&pdev->dev, "controller already in use\n");
++ rc = -EBUSY;
++ goto put_hpriv;
++ }
++
++
++ hpriv->mmio = pci_ioremap_bar(pdev, ahci_pci_bar);
++ if (hpriv->mmio == NULL) {
++ dev_dbg(&pdev->dev, "error mapping memory\n");
++ rc = -EFAULT;
++ goto release_mem_region;
++ }
++
++ r_mem = kzalloc(sizeof(*r_mem), GFP_KERNEL);
++ if (r_mem) {
++ r_mem->r_bustag = 1;//mem
++ r_mem->r_bushandle = hpriv->mmio;
++
++ ctlr = kzalloc(sizeof(*ctlr), GFP_KERNEL);
++ if (ctlr) {
++ ctlr->r_mem = r_mem;
++ ctlr->dev_id = 0; //or 0x90ca104d;
++ ctlr->trace_len = 6;
++ bpcie_sata_phy_init(&pdev->dev, ctlr);
++ kfree(ctlr);
++ }
++ kfree(r_mem);
++ }
++ device_wakeup_enable(&pdev->dev);
++
++ /* save initial config */
++ ahci_save_initial_config(&pdev->dev, hpriv);
++
++ /* prepare host */
++ if (hpriv->cap & HOST_CAP_NCQ) {
++ pi.flags |= ATA_FLAG_NCQ;
++ /*
++ * Auto-activate optimization is supposed to be
++ * supported on all AHCI controllers indicating NCQ
++ * capability, but it seems to be broken on some
++ * chipsets including NVIDIAs.
++ */
++ if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
++ pi.flags |= ATA_FLAG_FPDMA_AA;
++
++ /*
++ * All AHCI controllers should be forward-compatible
++ * with the new auxiliary field. This code should be
++ * conditionalized if any buggy AHCI controllers are
++ * encountered.
++ */
++ pi.flags |= ATA_FLAG_FPDMA_AUX;
++ }
++
++ if (hpriv->cap & HOST_CAP_PMP)
++ pi.flags |= ATA_FLAG_PMP;
++
++ ahci_set_em_messages(hpriv, &pi);
++
++ /* CAP.NP sometimes indicate the index of the last enabled
++ * port, at other times, that of the last possible port, so
++ * determining the maximum port number requires looking at
++ * both CAP.NP and port_map.
++ */
++ n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
++
++ host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
++ if (!host) {
++ rc = -ENOMEM;
++ goto unmap_registers;
++ }
++ axhci->host = host;
++ pci_set_drvdata(pdev, axhci);
++
++ host->private_data = hpriv;
++
++ {
++ int index = 1;
++ int irq = (axhci->nr_irqs > 1) ? (pdev->irq + index) : pdev->irq;
++ hpriv->irq = irq;
++ }
++
++ if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
++ host->flags |= ATA_HOST_PARALLEL_SCAN;
++ else
++ dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
++
++ if (pi.flags & ATA_FLAG_EM)
++ ahci_reset_em(host);
++
++ for (i = 0; i < host->n_ports; i++) {
++ struct ata_port *ap = host->ports[i];
++
++ ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
++ ata_port_pbar_desc(ap, ahci_pci_bar,
++ 0x100 + ap->port_no * 0x80, "port");
++
++ /* set enclosure management message type */
++ if (ap->flags & ATA_FLAG_EM)
++ ap->em_message_type = hpriv->em_msg_type;
++
++
++ /* disabled/not-implemented port */
++ if (!(hpriv->port_map & (1 << i)))
++ ap->ops = &ata_dummy_port_ops;
++ }
++
++ rc = ahci_reset_controller(host);
++ dev_dbg(&pdev->dev, "ahci_reset_controller returned %d\n", rc);
++ if (rc)
++ goto release_host;
++
++ ahci_init_controller(host);
++ ahci_print_info(host, "ATA");
++
++ if (!bus_master) {
++ pci_set_master(pdev);
++ bus_master = true;
++ }
++
++ rc = ahci_host_activate(host, &ahci_sht);
++ dev_dbg(&pdev->dev, "ahci_host_activate returned %d\n", rc);
++ if (rc) {
++ goto host_deactivate;
++ }
++
++ pm_runtime_put_noidle(&pdev->dev);
++ return 0;
++
++ host_deactivate:
++ release_host:
++ unmap_registers:
++ iounmap(hpriv->mmio);
++ release_mem_region:
++ devm_release_mem_region(&pdev->dev, rsrc_start, rsrc_len);
++ put_hpriv:
++ //kfree(hpriv);
++ devm_kfree(&pdev->dev, hpriv);
++ dev_err(&pdev->dev, "init %s fail, %d\n",
++ pci_name(pdev), rc);
++ return rc;
++}
++
++static void ahci_remove_one(struct pci_dev *pdev)
++{
++ pm_runtime_get_noresume(&pdev->dev);
++
++ struct aeolia_xhci *axhci = pci_get_drvdata(pdev);
++ if (axhci && axhci->host) {
++ ata_host_detach(axhci->host);
++ struct ahci_host_priv *hpriv = axhci->host->private_data;
++ if (hpriv) {
++ iounmap(hpriv->mmio);
++ }
++ axhci->host = NULL;
++ }
++}
+
+ static int xhci_aeolia_probe(struct pci_dev *dev, const struct pci_device_id *id)
+ {
+@@ -380,9 +370,7 @@ static int xhci_aeolia_probe(struct pci_dev *dev, const struct pci_device_id *id
+ if (pci_enable_device(dev) < 0)
+ return -ENODEV;
+
+- axhci = kzalloc(sizeof(*axhci), GFP_KERNEL);
+- // TODO (ps4patches): Belize, enable in ahci commit
+- // axhci = devm_kzalloc(&dev->dev, sizeof(*axhci), GFP_KERNEL);
++ axhci = devm_kzalloc(&dev->dev, sizeof(*axhci), GFP_KERNEL);
+ if (!axhci) {
+ retval = -ENOMEM;
+ goto disable_device;
+@@ -394,21 +382,23 @@ static int xhci_aeolia_probe(struct pci_dev *dev, const struct pci_device_id *id
+ goto free_axhci;
+ }
+
+- // TODO (ps4patches): Belize, disable in ahci commit
+- pci_set_master(dev);
++ if(dev->device != PCI_DEVICE_ID_SONY_BELIZE_XHCI) {
++ pci_set_master(dev);
++ }
+
+ if (pci_set_dma_mask(dev, DMA_BIT_MASK(31)) ||
+ pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(31))) {
+ return -ENODEV;
+ }
+
+- // TODO (ps4patches): Belize, enable in ahci commit
+-// retval = ahci_init_one(dev);
+-// dev_dbg(&dev->dev, "ahci_init_one returned %d", retval);
+-// if (!bus_master) {
+-// pci_set_master(dev);
+-// bus_master = true;
+-// }
++ if(dev->device == PCI_DEVICE_ID_SONY_BELIZE_XHCI) {
++ retval = ahci_init_one(dev);
++ dev_dbg(&dev->dev, "ahci_init_one returned %d", retval);
++ if (!bus_master) {
++ pci_set_master(dev);
++ bus_master = true;
++ }
++ }
+
+ for (idx = 0; idx < NR_DEVICES; idx++) {
+ if(dev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI && idx == 1){ //this is for Belize and Baikal
+@@ -426,11 +416,12 @@ static int xhci_aeolia_probe(struct pci_dev *dev, const struct pci_device_id *id
+ xhci_aeolia_remove_one(dev, idx);
+ apcie_free_irqs(dev->irq, axhci->nr_irqs);
+ free_axhci:
+- kfree(axhci);
++ devm_kfree(&dev->dev, axhci);
+
+- // TODO (ps4patches): Belize, disable in ahci commit
+- // devm_kfree(&dev->dev, axhci);
+- // pci_set_drvdata(dev, NULL);
++ // TODO (ps4patches): Don't aeolia and baikal also need this?
++ if(dev->device == PCI_DEVICE_ID_SONY_BELIZE_XHCI) {
++ pci_set_drvdata(dev, NULL);
++ }
+ disable_device:
+ pci_disable_device(dev);
+ return retval;
+@@ -447,9 +438,8 @@ static void xhci_aeolia_remove(struct pci_dev *dev)
+ if(dev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI) {
+ if(idx != 1)
+ xhci_aeolia_remove_one(dev, idx);
+- // TODO (ps4patches): Belize, enable in ahci commit
+- // else
+- // ahci_remove_one(dev);
++ else if (dev->device == PCI_DEVICE_ID_SONY_BELIZE_XHCI)
++ ahci_remove_one(dev);
+ }
+ else
+ xhci_aeolia_remove_one(dev, idx);
+@@ -463,32 +453,38 @@ static void xhci_aeolia_remove(struct pci_dev *dev)
+ pci_disable_device(dev);
+ }
+
+-// TODO (ps4patches): Belize, enable in ahci commit
+-//static void xhci_hcd_pci_shutdown(struct pci_dev *dev){
+-// struct aeolia_xhci *axhci;
+-// struct usb_hcd *hcd;
+-// int idx;
+-//
+-// axhci = pci_get_drvdata(dev);
+-// if (!axhci)
+-// return;
+-//
+-// for (idx = 0; idx < NR_DEVICES; idx++) {
+-// if(dev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI) {
+-// if(idx != 1) {
+-// hcd = axhci->hcd[idx];
+-// if (hcd) {
+-// if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) && hcd->driver->shutdown) {
+-// hcd->driver->shutdown(hcd);
+-// if (usb_hcd_is_primary_hcd(hcd) && hcd->irq > 0)
+-// free_irq(hcd->irq, hcd);
+-// }
+-// }
+-// }
+-// }
+-// }
+-//}
++static void xhci_hcd_pci_shutdown(struct pci_dev *dev){
++
++ // We want to use the normal shutdown if we aren't belize
++ if (dev->device != PCI_DEVICE_ID_SONY_BELIZE_XHCI)
++ {
++ usb_hcd_pci_shutdown(dev);
++ return;
++ }
++
++ struct aeolia_xhci *axhci;
++ struct usb_hcd *hcd;
++ int idx;
++
++ axhci = pci_get_drvdata(dev);
++ if (!axhci)
++ return;
+
++ for (idx = 0; idx < NR_DEVICES; idx++) {
++ if(dev->device != PCI_DEVICE_ID_SONY_AEOLIA_XHCI) {
++ if(idx != 1) {
++ hcd = axhci->hcd[idx];
++ if (hcd) {
++ if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) && hcd->driver->shutdown) {
++ hcd->driver->shutdown(hcd);
++ if (usb_hcd_is_primary_hcd(hcd) && hcd->irq > 0)
++ free_irq(hcd->irq, hcd);
++ }
++ }
++ }
++ }
++ }
++}
+
+ static const struct pci_device_id pci_ids[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_SONY, PCI_DEVICE_ID_SONY_AEOLIA_XHCI) },
+@@ -557,10 +553,7 @@ static struct pci_driver xhci_aeolia_driver = {
+ .probe = xhci_aeolia_probe,
+ .remove = xhci_aeolia_remove,
+ /* suspend and resume implemented later */
+-
+- .shutdown = usb_hcd_pci_shutdown,
+- // TODO (ps4patches): Belize, enable in ahci commit
+- //.shutdown = xhci_hcd_pci_shutdown,
++ .shutdown = xhci_hcd_pci_shutdown,
+ #ifdef CONFIG_PM_SLEEP
+ .driver = {
+ .pm = &xhci_aeolia_pm_ops
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0016-fix-this-probably-needs-to-be-the-amount-of-interrup.patch b/device/testing/linux-sony-ps4/0016-fix-this-probably-needs-to-be-the-amount-of-interrup.patch
new file mode 100644
index 0000000000000000000000000000000000000000..6ae63275947fc91c78bab31be2856ccc3c44e801
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0016-fix-this-probably-needs-to-be-the-amount-of-interrup.patch
@@ -0,0 +1,25 @@
+From f94cfdd446ab433ba0e9a0cb074372025de283eb Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Wed, 29 Dec 2021 16:15:26 +0100
+Subject: [PATCH 16/22] fix: this probably needs to be the amount of interrupts
+
+---
+ drivers/ps4/ps4-apcie.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/ps4/ps4-apcie.c b/drivers/ps4/ps4-apcie.c
+index fd27a4f38e61..b0bbc3f9891c 100644
+--- a/drivers/ps4/ps4-apcie.c
++++ b/drivers/ps4/ps4-apcie.c
+@@ -343,7 +343,7 @@ int apcie_assign_irqs(struct pci_dev *dev, int nvec)
+ }
+ #endif
+
+- desc = alloc_msi_entry(bare_dev, 1, NULL);
++ desc = alloc_msi_entry(bare_dev, nvec, NULL);
+
+ info.desc = desc;
+ info.data = sc;
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0017-Also-on-liverpool-num_crtc-is-6.patch b/device/testing/linux-sony-ps4/0017-Also-on-liverpool-num_crtc-is-6.patch
new file mode 100644
index 0000000000000000000000000000000000000000..c7645f8e0fb7512ec5f44bb8512751a8cafc66c4
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0017-Also-on-liverpool-num_crtc-is-6.patch
@@ -0,0 +1,24 @@
+From 62b05b54178ecba3e2d42fbe78b97da94b0fec81 Mon Sep 17 00:00:00 2001
+From: Ps3ita Team <ps3ita-team@ps3ita.it>
+Date: Wed, 13 Feb 2019 14:09:55 +0100
+Subject: [PATCH 17/22] Also on liverpool num_crtc is 6
+
+---
+ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+index aaa6893d8e51..bd9d32217d25 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+@@ -404,6 +404,7 @@ static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
+ case CHIP_BONAIRE:
+ case CHIP_HAWAII:
+ case CHIP_GLADIUS:
++ case CHIP_LIVERPOOL:
+ num_crtc = 6;
+ break;
+ case CHIP_KAVERI:
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0018-fix-cherrypick-doubled-CHIP_LIVERPOOL.patch b/device/testing/linux-sony-ps4/0018-fix-cherrypick-doubled-CHIP_LIVERPOOL.patch
new file mode 100644
index 0000000000000000000000000000000000000000..30b2fc46e83fa701118250d891dcafaf0d926c42
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0018-fix-cherrypick-doubled-CHIP_LIVERPOOL.patch
@@ -0,0 +1,24 @@
+From 0bf01d7fb8556417ca16ce96b230dd2741de8d48 Mon Sep 17 00:00:00 2001
+From: codedwrench <rick.04.1996@gmail.com>
+Date: Thu, 30 Dec 2021 15:05:26 +0100
+Subject: [PATCH 18/22] fix: cherrypick doubled CHIP_LIVERPOOL
+
+---
+ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+index bd9d32217d25..e54b86bd6d99 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+@@ -408,7 +408,6 @@ static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev)
+ num_crtc = 6;
+ break;
+ case CHIP_KAVERI:
+- case CHIP_LIVERPOOL:
+ num_crtc = 4;
+ break;
+ case CHIP_KABINI:
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0019-Missing-break.patch b/device/testing/linux-sony-ps4/0019-Missing-break.patch
new file mode 100644
index 0000000000000000000000000000000000000000..fa6842d5d56b600a2eb902c5b6a84c6f21df9c9e
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0019-Missing-break.patch
@@ -0,0 +1,25 @@
+From 4e2075413f8a4232857f9a87905f8afc28e74267 Mon Sep 17 00:00:00 2001
+From: Ps3ita Team <psxitateam@psxita.it>
+Date: Sat, 30 May 2020 12:04:24 +0200
+Subject: [PATCH 19/22] Missing break;
+
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+index 8513dd006ad5..3c2e63c2d32b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+@@ -4956,7 +4956,7 @@ static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
+ adev->gfx.config.max_tile_pipes = 8; // Verified
+ adev->gfx.config.max_cu_per_sh = 9; // Probably OK
+ adev->gfx.config.max_sh_per_se = 1; // Verified
+- adev->gfx.config.max_backends_per_se = 1; // Probably OK?
++ adev->gfx.config.max_backends_per_se = 2; // Probably OK?
+ adev->gfx.config.max_texture_channel_caches = 4; // ??
+ adev->gfx.config.max_gprs = 256;
+ adev->gfx.config.max_gs_threads = 32; // ??
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0020-fix-needed-for-video-codec-support.patch b/device/testing/linux-sony-ps4/0020-fix-needed-for-video-codec-support.patch
new file mode 100644
index 0000000000000000000000000000000000000000..cbb87055d67740244f430f404ecc13e1ab3541e6
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0020-fix-needed-for-video-codec-support.patch
@@ -0,0 +1,25 @@
+From 9dbe4ba89c9f330e27257ad50b9da4cf9ff1ac9a Mon Sep 17 00:00:00 2001
+From: Rick de Bondt <rick_1996@hotmail.com>
+Date: Fri, 31 Dec 2021 15:19:08 +0100
+Subject: [PATCH 20/22] fix: needed for video codec support
+
+---
+ drivers/gpu/drm/amd/amdgpu/cik.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+index 353899a95424..147db89444fd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -136,6 +136,8 @@ static int cik_query_video_codecs(struct amdgpu_device *adev, bool encode,
+ case CHIP_KAVERI:
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
++ case CHIP_LIVERPOOL:
++ case CHIP_GLADIUS:
+ if (encode)
+ *codecs = &cik_video_codecs_encode;
+ else
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0021-fix-gcc-newer-than-11.patch b/device/testing/linux-sony-ps4/0021-fix-gcc-newer-than-11.patch
new file mode 100644
index 0000000000000000000000000000000000000000..81b3778be1a345e460f5a9eba780bc74310bd9d2
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0021-fix-gcc-newer-than-11.patch
@@ -0,0 +1,36 @@
+From dc139fd452cfa78583a695b0d4fc2cdec39b31da Mon Sep 17 00:00:00 2001
+From: crashniels <39709384+crashniels@users.noreply.github.com>
+Date: Fri, 24 May 2024 19:47:37 +0200
+Subject: [PATCH 21/22] fix: gcc newer than 11
+
+https://lore.kernel.org/lkml/20220129010215.781601-1-jforbes@fedoraproject.org/t/
+---
+ tools/lib/subcmd/subcmd-util.h | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/tools/lib/subcmd/subcmd-util.h b/tools/lib/subcmd/subcmd-util.h
+index b2aec04fce8f..7009fc176636 100644
+--- a/tools/lib/subcmd/subcmd-util.h
++++ b/tools/lib/subcmd/subcmd-util.h
+@@ -49,9 +49,15 @@ static NORETURN inline void die(const char *err, ...)
+
+ static inline void *xrealloc(void *ptr, size_t size)
+ {
+- void *ret = realloc(ptr, size);
+- if (!ret)
+- die("Out of memory, realloc failed");
++ void *ret;
++ if (!size)
++ size = 1;
++ ret = realloc(ptr, size);
++ if (!ret) {
++ ret = realloc(ptr, size);
++ if (!ret)
++ die("Out of memory, realloc failed");
++ }
+ return ret;
+ }
+
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/0022-fix-use-upstream-values.patch b/device/testing/linux-sony-ps4/0022-fix-use-upstream-values.patch
new file mode 100644
index 0000000000000000000000000000000000000000..6724f9803079871207397e0f9a98c1635f51e9ea
--- /dev/null
+++ b/device/testing/linux-sony-ps4/0022-fix-use-upstream-values.patch
@@ -0,0 +1,39 @@
+From 77961812e981b14669eb51cfa67181149a9bb64a Mon Sep 17 00:00:00 2001
+From: crashniels <39709384+crashniels@users.noreply.github.com>
+Date: Sat, 25 May 2024 19:32:05 +0200
+Subject: [PATCH 22/22] fix: use upstream values
+
+---
+ drivers/usb/host/xhci-aeolia.c | 2 +-
+ drivers/usb/host/xhci.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-aeolia.c b/drivers/usb/host/xhci-aeolia.c
+index 1401af61430c..9ab0be144f42 100644
+--- a/drivers/usb/host/xhci-aeolia.c
++++ b/drivers/usb/host/xhci-aeolia.c
+@@ -43,7 +43,7 @@ static void xhci_aeolia_quirks(struct device *dev, struct xhci_hcd *xhci)
+ * Do not try to enable MSIs, we provide the MSIs ourselves
+ * Do not touch DMA mask, we need a custom one
+ */
+- xhci->quirks |= XHCI_PLAT | XHCI_PLAT_DMA;
++ xhci->quirks |= XHCI_PLAT | XHCI_SUSPEND_RESUME_CLKS;
+ }
+
+ /* called during probe() after chip reset completes */
+diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
+index 1c8fb48c7095..a79e9dc827e4 100644
+--- a/drivers/usb/host/xhci.c
++++ b/drivers/usb/host/xhci.c
+@@ -5373,7 +5373,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
+
+ /* Set dma_mask and coherent_dma_mask to 64-bits,
+ * if xHC supports 64-bit addressing */
+- if (!(xhci->quirks & XHCI_PLAT_DMA)) {
++ if (!(xhci->quirks & XHCI_SUSPEND_RESUME_CLKS)) {
+ if (HCC_64BIT_ADDR(xhci->hcc_params) &&
+ !dma_set_mask(dev, DMA_BIT_MASK(64))) {
+ xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
+--
+2.45.1
+
diff --git a/device/testing/linux-sony-ps4/APKBUILD b/device/testing/linux-sony-ps4/APKBUILD
new file mode 100644
index 0000000000000000000000000000000000000000..b2d6083cd8d23f69d0dc1a366b1e6ff168dfe98b
--- /dev/null
+++ b/device/testing/linux-sony-ps4/APKBUILD
@@ -0,0 +1,112 @@
+pkgname=linux-sony-ps4
+pkgver=5.15.110
+pkgrel=0
+pkgdesc="Sony Playstation 4 kernel fork"
+arch="x86_64"
+_flavor="sony-ps4"
+_carch="x86"
+url="https://kernel.org"
+license="GPL-2.0-only"
+options="!strip !check !tracedeps
+ pmb:cross-native
+ pmb:kconfigcheck-community
+ "
+makedepends="
+ bash
+ bison
+ elfutils-dev
+ findutils
+ flex
+ linux-headers
+ openssl-dev
+ perl
+ postmarketos-installkernel
+ linux-firmware-mrvl
+"
+
+# Source
+_config="config-$_flavor.$arch"
+case $pkgver in
+ *.*.*) _kernver=${pkgver%.0};;
+ *.*) _kernver=$pkgver;;
+esac
+
+source="
+ https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/snapshot/linux-${_kernver//_/-}.tar.gz
+ $_config
+
+ 0001-feat-very-basic-platform-support.patch
+ 0002-feat-amdgpu-patches.patch
+ 0003-feat-radeon-patches.patch
+ 0004-feat-temperature-sensors.patch
+ 0005-feat-sdhci-support.patch
+ 0006-feat-ethernet-support.patch
+ 0007-feat-usb-support.patch
+ 0008-feat-configuration.patch
+ 0009-feat-trying-to-modernize-ps4-apcie-so-it-works-with-.patch
+ 0010-feat-working-state-broken-gpu.patch
+ 0011-fix-incorrectly-applied-patches-and-missing-patches.patch
+ 0012-fix-radeon-drivers.patch
+ 0013-fix-amdgpu-drivers.patch
+ 0014-fix-re-add-legacy-bridge-functions.patch
+ 0015-feat-potentially-added-belize-ahci-support-in-a-univ.patch
+ 0016-fix-this-probably-needs-to-be-the-amount-of-interrup.patch
+ 0017-Also-on-liverpool-num_crtc-is-6.patch
+ 0018-fix-cherrypick-doubled-CHIP_LIVERPOOL.patch
+ 0019-Missing-break.patch
+ 0020-fix-needed-for-video-codec-support.patch
+ 0021-fix-gcc-newer-than-11.patch
+ 0022-fix-use-upstream-values.patch
+"
+builddir="$srcdir/linux-${_kernver//_/-}"
+
+prepare() {
+ default_prepare
+ cp "$srcdir/$_config" .config
+}
+
+build() {
+ unset LDFLAGS
+ make ARCH="$_carch" CC="${CC:-gcc}" \
+ KBUILD_BUILD_VERSION="$((pkgrel + 1 ))-$_flavor"
+}
+
+package() {
+ mkdir -p "$pkgdir"/boot
+ make install modules_install \
+ ARCH="$_carch" \
+ INSTALL_PATH="$pkgdir"/boot \
+ INSTALL_MOD_PATH="$pkgdir" \
+ INSTALL_MOD_STRIP=1
+ rm -f "$pkgdir"/lib/modules/*/build "$pkgdir"/lib/modules/*/source
+
+ install -D "$builddir"/include/config/kernel.release \
+ "$pkgdir"/usr/share/kernel/$_flavor/kernel.release
+}
+
+sha512sums="
+405be3edf5855e45b50fd163542e00f58fab0d80c9e93e9605100107eba79ce4b49b83d5ddda3226665bdbdd1c31ac06b4ef05cf87b31f7cf1ff8adf662f2178 linux-5.15.110.tar.gz
+1632c7eb73a7341b8fa1981a66bb59fe21aa6d04cad11bbbf85823950451240d942c40c8eb0b7a1301beec00f3375ae84cbb50594cca4f5fa9983fca56f09dae config-sony-ps4.x86_64
+7d4e6ab0d273b4d121bfb485334ea949abc4466a914ac596edfae716f3f1d5dde896d27b2b29efd77115d732a0256db3b395ab7cf8d91a47d4a3c45778dc753e 0001-feat-very-basic-platform-support.patch
+e69400cbc1772bc247868004f874c174289747fc36f5df6002664a6813fd24b7fe2dae3b6f6e0647466f89735454914d49316bbb996dd41863bcca1424c5191c 0002-feat-amdgpu-patches.patch
+cffb257874c4e746c82a06be9b9442df9c2deb897e479c7d75a7d73883a64e0d9f00812e1468d8e3fdd15eda0bcfe92668c96bee2f7e2de57c1088f467b329b4 0003-feat-radeon-patches.patch
+262b0934845d9c8bc92c6cacf8cbb1fb697830ac386380c27de586766b801c52ce0230755b62f4abd44c39fc0559446749a212d666636102c35d34299d8cf6c5 0004-feat-temperature-sensors.patch
+536daa2a900ae214a2a1cde277c1ae1b9c4d5a740ddf4a8d2d23e5a4578eeb2e274d89ce917d9705495814580ceceb9cbf69ccb81e14d88ac932f84f1bb4fcad 0005-feat-sdhci-support.patch
+1f960d7bcb8805f2c86e71125a73e28ba8b6b1dcf230a0994ae140f7874ed3e4d8e6ec867d4bff8fdccbfc94b432ccaf6c01e8774a702984f57bd323bf72c208 0006-feat-ethernet-support.patch
+7856b33b05a090009dde83a03ec74044ae64100469ac004c94913a895ccd91c1b7c4623bcc08217e04110a79ef599018a9925c308d8f7e9e89791704675dfc0b 0007-feat-usb-support.patch
+2b28e8059c6845ab3e7b64bc84469936f9d5620331b8738b335fdf11b2fc03d83a06c68b323ebe79d374b23f0264bd9a51e2fd6a323119c68d8edce0ec8fcf25 0008-feat-configuration.patch
+5ce3347dabc35b419ee71fa1c29ebb1ece570c048439c8cdb43f7503863619c70c2c5af79383bbae23eb7f63e58ac1d4690bd9bced0bb103967392ca19d9f328 0009-feat-trying-to-modernize-ps4-apcie-so-it-works-with-.patch
+a57142aa46e698e147f1527383006f77c2b6f62a52520dbcdc9da19782ff89252be841dfe6e2b5b9566c396ec15693a8b54c1ea98ae85d514b844642e1456d31 0010-feat-working-state-broken-gpu.patch
+f922606e57a194dbde0bbf702f328b2bcc4116b7a6bf34eda6781414f5685dfad9a48e21af4c33af154c680a9093085432ccc71d3e083b1aec1c0fbfb5ef8b43 0011-fix-incorrectly-applied-patches-and-missing-patches.patch
+cb22e3f401178b2801605db766f372a08322248b013f51ede908d0d1ca008c780c98cc53b8252fd473d1def043f44ab8b44530aa9a43d749480517e8e7f33226 0012-fix-radeon-drivers.patch
+c8c6a9af6de9324ca66be658be59063c85e579420832e5394a778b8af0119894cc5ac2483a11d6dd1f714d6ac15f719f50de841b896b1c9f153a982dd28d307d 0013-fix-amdgpu-drivers.patch
+1e8af016a999f18ca64d09a2dcf55d4dc961c9b5c78f45c5c5b09e22e97d2c76d65dcf4742c1da2dd557e8c995c23237161553946a9622adf51c4d99c59d9d2d 0014-fix-re-add-legacy-bridge-functions.patch
+4de5a19976bfcfd6d290256f1ab5eb270d60e037341b8a998d8026751b2d55c911045b6b7034446258a677db668229516995585b8ce8d2ea1a1a49e333ac3164 0015-feat-potentially-added-belize-ahci-support-in-a-univ.patch
+e18c4f277793181625c3769f3b5d5f264a6c7c2f562ab4e1638e7f8b3a57cc547ee5bc71f44ec182f1c9609b9d848267370fa85531ff483c9a0a5cb52db4bdcc 0016-fix-this-probably-needs-to-be-the-amount-of-interrup.patch
+aa2d70a0dd8cef198d60de66446deead4b1b1a408f975bff2e733c3f554f555a99c1aca4b02ed58abbc609dc90e7711789dd396d1129bd6f96c30d569485acba 0017-Also-on-liverpool-num_crtc-is-6.patch
+563b5c3cf8df1f82724b4dd0f21d5231a80c79a7cef5c93de73c6008ff7bd140313b0d7d0f92d4fd95c556ab18087967735c4eade1a98974efa2d3536f2ca01a 0018-fix-cherrypick-doubled-CHIP_LIVERPOOL.patch
+38da37f52b3c1a77d80f70accc12351ee4c5e8d1302294d523741724d17a62e22cdf64c6dcbc1b472e3967b417d37754ea6faa5c8d5b4218bf731deeaef6e5e5 0019-Missing-break.patch
+ada724aa09e1b29525e1c6bda38cf68fd4c72b9d6b8f45b1f9000e06e67e2c7806f81c53efce246396b5e7dc0d745dead599fce8b3c4108189fa77b40accaff0 0020-fix-needed-for-video-codec-support.patch
+70d9dfd868e4da14c0b164f6a3c8450eda733c59b81d19341b54e38ba4faca7943ac3240c5872e08932ffd0b51b0884893d90bec20cd522ce5c0e4c7f37c187a 0021-fix-gcc-newer-than-11.patch
+1c166aba9d18171b0a610ea8ed4798f0bb32a6f2d73f70d2fb32aa98ed93437b7bc1f264e8c50e9668e77dc85bd5b1128ead9810bfbb082f5cae919cd32e772a 0022-fix-use-upstream-values.patch
+"
diff --git a/device/testing/linux-sony-ps4/config-sony-ps4.x86_64 b/device/testing/linux-sony-ps4/config-sony-ps4.x86_64
new file mode 100644
index 0000000000000000000000000000000000000000..4b7412653202b57b94907fbba04710b96367a3dc
--- /dev/null
+++ b/device/testing/linux-sony-ps4/config-sony-ps4.x86_64
@@ -0,0 +1,3989 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/x86 5.15.10 Kernel Configuration
+#
+CONFIG_CC_VERSION_TEXT="gcc (GCC) 11.1.0"
+CONFIG_CC_IS_GCC=y
+CONFIG_GCC_VERSION=110100
+CONFIG_CLANG_VERSION=0
+CONFIG_AS_IS_GNU=y
+CONFIG_AS_VERSION=23601
+CONFIG_LD_IS_BFD=y
+CONFIG_LD_VERSION=23601
+CONFIG_LLD_VERSION=0
+CONFIG_CC_CAN_LINK=y
+CONFIG_CC_CAN_LINK_STATIC=y
+CONFIG_CC_HAS_ASM_GOTO=y
+CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y
+CONFIG_CC_HAS_ASM_INLINE=y
+CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_TABLE_SORT=y
+CONFIG_THREAD_INFO_IN_TASK=y
+
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+# CONFIG_COMPILE_TEST is not set
+# CONFIG_WERROR is not set
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_BUILD_SALT=""
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_HAVE_KERNEL_LZ4=y
+CONFIG_HAVE_KERNEL_ZSTD=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+CONFIG_KERNEL_XZ=y
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_KERNEL_LZ4 is not set
+# CONFIG_KERNEL_ZSTD is not set
+CONFIG_DEFAULT_INIT=""
+CONFIG_DEFAULT_HOSTNAME="ps4"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_WATCH_QUEUE is not set
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_USELIB=y
+CONFIG_AUDIT=y
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_AUDITSYSCALL=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_PENDING_IRQ=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
+CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_SPARSE_IRQ=y
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
+# end of IRQ subsystem
+
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+CONFIG_ARCH_CLOCKSOURCE_INIT=y
+CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+# CONFIG_NO_HZ_FULL is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+# end of Timers subsystem
+
+CONFIG_BPF=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y
+
+#
+# BPF subsystem
+#
+# CONFIG_BPF_SYSCALL is not set
+# CONFIG_BPF_JIT is not set
+# end of BPF subsystem
+
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+# CONFIG_SCHED_CORE is not set
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set
+# CONFIG_IRQ_TIME_ACCOUNTING is not set
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+# CONFIG_PSI is not set
+# end of CPU/Task time and stats accounting
+
+# CONFIG_CPU_ISOLATION is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_RCU_EXPERT is not set
+CONFIG_SRCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RCU_NEED_SEGCBLIST=y
+# end of RCU Subsystem
+
+CONFIG_BUILD_BIN2C=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_IKHEADERS is not set
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_LOG_CPU_MAX_BUF_SHIFT=16
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13
+# CONFIG_PRINTK_INDEX is not set
+CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
+
+#
+# Scheduler features
+#
+# end of Scheduler features
+
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
+CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y
+CONFIG_CC_HAS_INT128=y
+CONFIG_ARCH_SUPPORTS_INT128=y
+# CONFIG_NUMA_BALANCING is not set
+CONFIG_CGROUPS=y
+CONFIG_PAGE_COUNTER=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_MEMCG_KMEM=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_WRITEBACK=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+CONFIG_RT_GROUP_SCHED=y
+# CONFIG_CGROUP_PIDS is not set
+# CONFIG_CGROUP_RDMA is not set
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+# CONFIG_CPUSETS is not set
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_CGROUP_PERF is not set
+# CONFIG_CGROUP_MISC is not set
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_TIME_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+# CONFIG_CHECKPOINT_RESTORE is not set
+CONFIG_SCHED_AUTOGROUP=y
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+# CONFIG_RD_ZSTD is not set
+# CONFIG_BOOT_CONFIG is not set
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LD_ORPHAN_WARN=y
+CONFIG_SYSCTL=y
+CONFIG_HAVE_UID16=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_HAVE_PCSPKR_PLATFORM=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+CONFIG_MULTIUSER=y
+CONFIG_SGETMASK_SYSCALL=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_FHANDLE=y
+CONFIG_POSIX_TIMERS=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_PCSPKR_PLATFORM is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_FUTEX_PI=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+# CONFIG_IO_URING is not set
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_MEMBARRIER=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_USERFAULTFD is not set
+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
+CONFIG_KCMP=y
+# CONFIG_RSEQ is not set
+# CONFIG_EMBEDDED is not set
+CONFIG_HAVE_PERF_EVENTS=y
+# CONFIG_PC104 is not set
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+# end of Kernel Performance Events And Counters
+
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_SLAB_MERGE_DEFAULT=y
+# CONFIG_SLAB_FREELIST_RANDOM is not set
+# CONFIG_SLAB_FREELIST_HARDENED is not set
+# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set
+# CONFIG_SLUB_CPU_PARTIAL is not set
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+# CONFIG_PROFILING is not set
+# end of General setup
+
+CONFIG_64BIT=y
+CONFIG_X86_64=y
+CONFIG_X86=y
+CONFIG_INSTRUCTION_DECODER=y
+CONFIG_OUTPUT_FORMAT="elf64-x86-64"
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_MMU=y
+CONFIG_ARCH_MMAP_RND_BITS_MIN=28
+CONFIG_ARCH_MMAP_RND_BITS_MAX=32
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_HAS_CPU_RELAX=y
+CONFIG_ARCH_HAS_FILTER_PGPROT=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_NR_GPIO=1024
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_AUDIT_ARCH=y
+CONFIG_X86_64_SMP=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_CC_HAS_SANE_STACKPROTECTOR=y
+
+#
+# Processor type and features
+#
+CONFIG_SMP=y
+CONFIG_X86_FEATURE_NAMES=y
+CONFIG_X86_X2APIC=y
+CONFIG_X86_MPPARSE=y
+# CONFIG_GOLDFISH is not set
+# CONFIG_RETPOLINE is not set
+# CONFIG_X86_CPU_RESCTRL is not set
+CONFIG_X86_EXTENDED_PLATFORM=y
+# CONFIG_X86_NUMACHIP is not set
+CONFIG_X86_PS4=y
+# CONFIG_X86_VSMP is not set
+# CONFIG_X86_GOLDFISH is not set
+# CONFIG_X86_INTEL_LPSS is not set
+# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
+CONFIG_IOSF_MBI=y
+# CONFIG_IOSF_MBI_DEBUG is not set
+CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+# CONFIG_HYPERVISOR_GUEST is not set
+CONFIG_MK8=y
+# CONFIG_MPSC is not set
+# CONFIG_MCORE2 is not set
+# CONFIG_MATOM is not set
+# CONFIG_GENERIC_CPU is not set
+CONFIG_X86_INTERNODE_CACHE_SHIFT=6
+CONFIG_X86_L1_CACHE_SHIFT=6
+CONFIG_X86_INTEL_USERCOPY=y
+CONFIG_X86_USE_PPRO_CHECKSUM=y
+CONFIG_X86_TSC=y
+CONFIG_X86_CMPXCHG64=y
+CONFIG_X86_CMOV=y
+CONFIG_X86_MINIMUM_CPU_FAMILY=64
+CONFIG_X86_DEBUGCTLMSR=y
+CONFIG_PROCESSOR_SELECT=y
+# CONFIG_CPU_SUP_INTEL is not set
+CONFIG_CPU_SUP_AMD=y
+# CONFIG_CPU_SUP_HYGON is not set
+# CONFIG_CPU_SUP_CENTAUR is not set
+# CONFIG_CPU_SUP_ZHAOXIN is not set
+CONFIG_HPET_TIMER=y
+CONFIG_DMI=y
+CONFIG_GART_IOMMU=y
+# CONFIG_MAXSMP is not set
+CONFIG_NR_CPUS_RANGE_BEGIN=2
+CONFIG_NR_CPUS_RANGE_END=512
+CONFIG_NR_CPUS_DEFAULT=64
+CONFIG_NR_CPUS=8
+CONFIG_SCHED_SMT=y
+CONFIG_SCHED_MC=y
+CONFIG_X86_LOCAL_APIC=y
+CONFIG_X86_IO_APIC=y
+# CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set
+CONFIG_X86_MCE=y
+# CONFIG_X86_MCELOG_LEGACY is not set
+# CONFIG_X86_MCE_INTEL is not set
+CONFIG_X86_MCE_AMD=y
+CONFIG_X86_MCE_THRESHOLD=y
+# CONFIG_X86_MCE_INJECT is not set
+
+#
+# Performance monitoring
+#
+# CONFIG_PERF_EVENTS_INTEL_RAPL is not set
+# CONFIG_PERF_EVENTS_AMD_POWER is not set
+# CONFIG_PERF_EVENTS_AMD_UNCORE is not set
+# end of Performance monitoring
+
+CONFIG_X86_VSYSCALL_EMULATION=y
+CONFIG_X86_IOPL_IOPERM=y
+# CONFIG_I8K is not set
+CONFIG_MICROCODE=y
+# CONFIG_MICROCODE_INTEL is not set
+CONFIG_MICROCODE_AMD=y
+CONFIG_MICROCODE_OLD_INTERFACE=y
+CONFIG_X86_MSR=y
+CONFIG_X86_CPUID=y
+# CONFIG_X86_5LEVEL is not set
+CONFIG_X86_DIRECT_GBPAGES=y
+# CONFIG_X86_CPA_STATISTICS is not set
+# CONFIG_AMD_MEM_ENCRYPT is not set
+CONFIG_NUMA=y
+CONFIG_AMD_NUMA=y
+CONFIG_X86_64_ACPI_NUMA=y
+# CONFIG_NUMA_EMU is not set
+CONFIG_NODES_SHIFT=6
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+# CONFIG_X86_PMEM_LEGACY is not set
+# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set
+CONFIG_MTRR=y
+CONFIG_MTRR_SANITIZER=y
+CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0
+CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1
+CONFIG_X86_PAT=y
+CONFIG_ARCH_USES_PG_UNCACHED=y
+CONFIG_ARCH_RANDOM=y
+# CONFIG_X86_SMAP is not set
+CONFIG_X86_UMIP=y
+CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y
+# CONFIG_EFI is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+CONFIG_HZ_1000=y
+CONFIG_HZ=1000
+CONFIG_SCHED_HRTICK=y
+CONFIG_KEXEC=y
+CONFIG_KEXEC_FILE=y
+CONFIG_ARCH_HAS_KEXEC_PURGATORY=y
+# CONFIG_KEXEC_SIG is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_PHYSICAL_START=0x1000000
+CONFIG_RELOCATABLE=y
+# CONFIG_RANDOMIZE_BASE is not set
+CONFIG_PHYSICAL_ALIGN=0x200000
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set
+# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
+# CONFIG_COMPAT_VDSO is not set
+CONFIG_LEGACY_VSYSCALL_EMULATE=y
+# CONFIG_LEGACY_VSYSCALL_XONLY is not set
+# CONFIG_LEGACY_VSYSCALL_NONE is not set
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_MODIFY_LDT_SYSCALL is not set
+CONFIG_HAVE_LIVEPATCH=y
+# end of Processor type and features
+
+CONFIG_ARCH_HAS_ADD_PAGES=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+
+#
+# Power management and ACPI options
+#
+# CONFIG_SUSPEND is not set
+# CONFIG_HIBERNATION is not set
+# CONFIG_PM is not set
+CONFIG_ARCH_SUPPORTS_ACPI=y
+CONFIG_ACPI=y
+CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
+CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
+CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_SPCR_TABLE is not set
+# CONFIG_ACPI_FPDT is not set
+CONFIG_ACPI_LPIT=y
+CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
+# CONFIG_ACPI_EC_DEBUGFS is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_BATTERY is not set
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_VIDEO=y
+# CONFIG_ACPI_FAN is not set
+# CONFIG_ACPI_DOCK is not set
+CONFIG_ACPI_CPU_FREQ_PSS=y
+CONFIG_ACPI_PROCESSOR_CSTATE=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_PROCESSOR_AGGREGATOR=y
+CONFIG_ACPI_THERMAL=y
+CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
+CONFIG_ACPI_TABLE_UPGRADE=y
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_PCI_SLOT is not set
+CONFIG_ACPI_CONTAINER=y
+CONFIG_ACPI_HOTPLUG_IOAPIC=y
+# CONFIG_ACPI_SBS is not set
+# CONFIG_ACPI_HED is not set
+CONFIG_ACPI_CUSTOM_METHOD=y
+# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set
+# CONFIG_ACPI_NFIT is not set
+CONFIG_ACPI_NUMA=y
+# CONFIG_ACPI_HMAT is not set
+CONFIG_HAVE_ACPI_APEI=y
+CONFIG_HAVE_ACPI_APEI_NMI=y
+# CONFIG_ACPI_APEI is not set
+# CONFIG_ACPI_DPTF is not set
+# CONFIG_ACPI_CONFIGFS is not set
+# CONFIG_PMIC_OPREGION is not set
+# CONFIG_X86_PM_TIMER is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+# end of CPU Frequency scaling
+
+#
+# CPU Idle
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+# CONFIG_CPU_IDLE_GOV_TEO is not set
+# end of CPU Idle
+# end of Power management and ACPI options
+
+#
+# Bus options (PCI etc.)
+#
+CONFIG_PCI_DIRECT=y
+CONFIG_PCI_MMCONFIG=y
+CONFIG_MMCONF_FAM10H=y
+# CONFIG_PCI_CNB20LE_QUIRK is not set
+# CONFIG_ISA_BUS is not set
+CONFIG_ISA_DMA_API=y
+CONFIG_AMD_NB=y
+# end of Bus options (PCI etc.)
+
+#
+# Binary Emulations
+#
+CONFIG_IA32_EMULATION=y
+CONFIG_X86_X32=y
+CONFIG_COMPAT_32=y
+CONFIG_COMPAT=y
+CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
+CONFIG_SYSVIPC_COMPAT=y
+# end of Binary Emulations
+
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_KVM_IRQCHIP=y
+CONFIG_HAVE_KVM_IRQFD=y
+CONFIG_HAVE_KVM_IRQ_ROUTING=y
+CONFIG_HAVE_KVM_EVENTFD=y
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_ASYNC_PF=y
+CONFIG_HAVE_KVM_MSI=y
+CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
+CONFIG_KVM_VFIO=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_COMPAT=y
+CONFIG_HAVE_KVM_IRQ_BYPASS=y
+CONFIG_HAVE_KVM_NO_POLL=y
+CONFIG_KVM_XFER_TO_GUEST_WORK=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+# CONFIG_KVM_WERROR is not set
+CONFIG_KVM_AMD=y
+CONFIG_KVM_XEN=y
+CONFIG_AS_AVX512=y
+CONFIG_AS_SHA1_NI=y
+CONFIG_AS_SHA256_NI=y
+CONFIG_AS_TPAUSE=y
+
+#
+# General architecture-dependent options
+#
+CONFIG_CRASH_CORE=y
+CONFIG_KEXEC_CORE=y
+CONFIG_HOTPLUG_SMT=y
+CONFIG_GENERIC_ENTRY=y
+# CONFIG_KPROBES is not set
+CONFIG_JUMP_LABEL=y
+# CONFIG_STATIC_KEYS_SELFTEST is not set
+# CONFIG_STATIC_CALL_SELFTEST is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_USER_RETURN_NOTIFIER=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_KPROBES_ON_FTRACE=y
+CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
+CONFIG_HAVE_NMI=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
+CONFIG_ARCH_HAS_SET_MEMORY=y
+CONFIG_ARCH_HAS_SET_DIRECT_MAP=y
+CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
+CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_HAVE_ASM_MODVERSIONS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_RSEQ=y
+CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y
+CONFIG_HAVE_USER_RETURN_NOTIFIER=y
+CONFIG_HAVE_PERF_EVENTS_NMI=y
+CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
+CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
+CONFIG_HAVE_CMPXCHG_LOCAL=y
+CONFIG_HAVE_CMPXCHG_DOUBLE=y
+CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
+CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y
+CONFIG_HAVE_ARCH_SECCOMP=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+# CONFIG_SECCOMP is not set
+CONFIG_HAVE_ARCH_STACKLEAK=y
+CONFIG_HAVE_STACKPROTECTOR=y
+# CONFIG_STACKPROTECTOR is not set
+CONFIG_ARCH_SUPPORTS_LTO_CLANG=y
+CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y
+CONFIG_LTO_NONE=y
+CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MOVE_PUD=y
+CONFIG_HAVE_MOVE_PMD=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y
+CONFIG_HAVE_ARCH_HUGE_VMAP=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_HAVE_ARCH_SOFT_DIRTY=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
+CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
+CONFIG_HAVE_EXIT_THREAD=y
+CONFIG_ARCH_MMAP_RND_BITS=28
+CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8
+CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y
+CONFIG_HAVE_STACK_VALIDATION=y
+CONFIG_HAVE_RELIABLE_STACKTRACE=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_HAVE_ARCH_VMAP_STACK=y
+# CONFIG_VMAP_STACK is not set
+CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y
+# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set
+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
+CONFIG_STRICT_KERNEL_RWX=y
+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
+CONFIG_STRICT_MODULE_RWX=y
+CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
+# CONFIG_LOCK_EVENT_COUNTS is not set
+CONFIG_ARCH_HAS_MEM_ENCRYPT=y
+CONFIG_HAVE_STATIC_CALL=y
+CONFIG_HAVE_STATIC_CALL_INLINE=y
+CONFIG_HAVE_PREEMPT_DYNAMIC=y
+CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_ARCH_HAS_ELFCORE_COMPAT=y
+CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+# end of GCOV-based kernel profiling
+
+CONFIG_HAVE_GCC_PLUGINS=y
+CONFIG_GCC_PLUGINS=y
+# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
+# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
+# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
+# end of General architecture-dependent options
+
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_MODULE_SIG is not set
+CONFIG_MODULE_COMPRESS_NONE=y
+# CONFIG_MODULE_COMPRESS_GZIP is not set
+# CONFIG_MODULE_COMPRESS_XZ is not set
+# CONFIG_MODULE_COMPRESS_ZSTD is not set
+# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set
+CONFIG_MODPROBE_PATH="/sbin/modprobe"
+# CONFIG_TRIM_UNUSED_KSYMS is not set
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_BLOCK=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_DEV_ZONED is not set
+# CONFIG_BLK_DEV_THROTTLING is not set
+CONFIG_BLK_WBT=y
+CONFIG_BLK_WBT_MQ=y
+# CONFIG_BLK_CGROUP_IOLATENCY is not set
+# CONFIG_BLK_CGROUP_IOCOST is not set
+# CONFIG_BLK_CGROUP_IOPRIO is not set
+CONFIG_BLK_DEBUG_FS=y
+# CONFIG_BLK_SED_OPAL is not set
+# CONFIG_BLK_INLINE_ENCRYPTION is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_AIX_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_CMDLINE_PARTITION is not set
+# end of Partition Types
+
+CONFIG_BLOCK_COMPAT=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLOCK_HOLDER_DEPRECATED=y
+
+#
+# IO Schedulers
+#
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+# CONFIG_IOSCHED_BFQ is not set
+# end of IO Schedulers
+
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_ASN1=y
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_INLINE_READ_UNLOCK=y
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y
+CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y
+CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
+CONFIG_FREEZER=y
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_ELFCORE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_SCRIPT=y
+CONFIG_BINFMT_MISC=y
+CONFIG_COREDUMP=y
+# end of Executable file formats
+
+#
+# Memory Management options
+#
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_HAVE_FAST_GUP=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+# CONFIG_MEMORY_HOTPLUG is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y
+CONFIG_COMPACTION=y
+# CONFIG_PAGE_REPORTING is not set
+CONFIG_MIGRATION=y
+CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y
+CONFIG_ARCH_ENABLE_THP_MIGRATION=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_MMU_NOTIFIER=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
+# CONFIG_MEMORY_FAILURE is not set
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_THP_SWAP=y
+CONFIG_CLEANCACHE=y
+CONFIG_FRONTSWAP=y
+# CONFIG_CMA is not set
+# CONFIG_ZSWAP is not set
+CONFIG_ZPOOL=y
+# CONFIG_ZBUD is not set
+# CONFIG_Z3FOLD is not set
+# CONFIG_ZSMALLOC is not set
+CONFIG_GENERIC_EARLY_IOREMAP=y
+# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set
+# CONFIG_IDLE_PAGE_TRACKING is not set
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_ARCH_HAS_PTE_DEVMAP=y
+CONFIG_ARCH_HAS_ZONE_DMA_SET=y
+CONFIG_ZONE_DMA=y
+CONFIG_ZONE_DMA32=y
+CONFIG_HMM_MIRROR=y
+CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
+CONFIG_ARCH_HAS_PKEYS=y
+# CONFIG_PERCPU_STATS is not set
+# CONFIG_GUP_TEST is not set
+# CONFIG_READ_ONLY_THP_FOR_FS is not set
+CONFIG_ARCH_HAS_PTE_SPECIAL=y
+CONFIG_SECRETMEM=y
+
+#
+# Data Access Monitoring
+#
+# CONFIG_DAMON is not set
+# end of Data Access Monitoring
+# end of Memory Management options
+
+CONFIG_NET=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=y
+CONFIG_UNIX=y
+CONFIG_UNIX_SCM=y
+CONFIG_AF_UNIX_OOB=y
+CONFIG_UNIX_DIAG=y
+# CONFIG_TLS is not set
+# CONFIG_XFRM_USER is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_NET_IP_TUNNEL=y
+# CONFIG_IP_MROUTE is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_NET_IPVTI is not set
+CONFIG_NET_UDP_TUNNEL=y
+# CONFIG_NET_FOU is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INET_UDP_DIAG=y
+# CONFIG_INET_RAW_DIAG is not set
+# CONFIG_INET_DIAG_DESTROY is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_IPV6_VTI is not set
+# CONFIG_IPV6_SIT is not set
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_IPV6_SEG6_LWTUNNEL is not set
+# CONFIG_IPV6_SEG6_HMAC is not set
+# CONFIG_IPV6_RPL_LWTUNNEL is not set
+# CONFIG_IPV6_IOAM6_LWTUNNEL is not set
+# CONFIG_MPTCP is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_BPFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_6LOWPAN is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+# CONFIG_DNS_RESOLVER is not set
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+CONFIG_NETLINK_DIAG=y
+# CONFIG_MPLS is not set
+# CONFIG_NET_NSH is not set
+# CONFIG_HSR is not set
+# CONFIG_NET_SWITCHDEV is not set
+# CONFIG_NET_L3_MASTER_DEV is not set
+# CONFIG_QRTR is not set
+# CONFIG_NET_NCSI is not set
+CONFIG_PCPU_DEV_REFCNT=y
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_XPS=y
+# CONFIG_CGROUP_NET_PRIO is not set
+# CONFIG_CGROUP_NET_CLASSID is not set
+CONFIG_NET_RX_BUSY_POLL=y
+CONFIG_BQL=y
+CONFIG_NET_FLOW_LIMIT=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# end of Network testing
+# end of Networking options
+
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+CONFIG_BT=y
+CONFIG_BT_BREDR=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_HS=y
+CONFIG_BT_LE=y
+# CONFIG_BT_LEDS is not set
+# CONFIG_BT_MSFTEXT is not set
+# CONFIG_BT_AOSPEXT is not set
+# CONFIG_BT_DEBUGFS is not set
+# CONFIG_BT_SELFTEST is not set
+# CONFIG_BT_FEATURE_DEBUG is not set
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTUSB is not set
+CONFIG_BT_HCIBTSDIO=y
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+CONFIG_BT_MRVL=y
+CONFIG_BT_MRVL_SDIO=y
+# CONFIG_BT_MTKSDIO is not set
+# end of Bluetooth device drivers
+
+# CONFIG_AF_RXRPC is not set
+# CONFIG_AF_KCM is not set
+# CONFIG_MCTP is not set
+CONFIG_WIRELESS=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
+CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
+CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_MESSAGE_TRACING is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+CONFIG_RFKILL=y
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL_INPUT=y
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+# CONFIG_PSAMPLE is not set
+# CONFIG_NET_IFE is not set
+# CONFIG_LWTUNNEL is not set
+CONFIG_DST_CACHE=y
+CONFIG_GRO_CELLS=y
+CONFIG_NET_SELFTESTS=y
+# CONFIG_FAILOVER is not set
+CONFIG_ETHTOOL_NETLINK=y
+
+#
+# Device Drivers
+#
+CONFIG_HAVE_EISA=y
+# CONFIG_EISA is not set
+CONFIG_HAVE_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEAER=y
+# CONFIG_PCIEAER_INJECT is not set
+# CONFIG_PCIE_ECRC is not set
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEFAULT is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEASPM_PERFORMANCE=y
+# CONFIG_PCIE_DPC is not set
+# CONFIG_PCIE_PTM is not set
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_QUIRKS=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+CONFIG_PCI_ATS=y
+CONFIG_PCI_LOCKLESS_CONFIG=y
+# CONFIG_PCI_IOV is not set
+CONFIG_PCI_PRI=y
+CONFIG_PCI_PASID=y
+CONFIG_PCI_LABEL=y
+# CONFIG_PCIE_BUS_TUNE_OFF is not set
+CONFIG_PCIE_BUS_DEFAULT=y
+# CONFIG_PCIE_BUS_SAFE is not set
+# CONFIG_PCIE_BUS_PERFORMANCE is not set
+# CONFIG_PCIE_BUS_PEER2PEER is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# PCI controller drivers
+#
+# CONFIG_VMD is not set
+
+#
+# DesignWare PCI Core Support
+#
+# CONFIG_PCIE_DW_PLAT_HOST is not set
+# CONFIG_PCI_MESON is not set
+# end of DesignWare PCI Core Support
+
+#
+# Mobiveil PCIe Core Support
+#
+# end of Mobiveil PCIe Core Support
+
+#
+# Cadence PCIe controllers support
+#
+# end of Cadence PCIe controllers support
+# end of PCI controller drivers
+
+#
+# PCI Endpoint
+#
+# CONFIG_PCI_ENDPOINT is not set
+# end of PCI Endpoint
+
+#
+# PCI switch controller drivers
+#
+# CONFIG_PCI_SW_SWITCHTEC is not set
+# end of PCI switch controller drivers
+
+# CONFIG_CXL_BUS is not set
+# CONFIG_PCCARD is not set
+# CONFIG_RAPIDIO is not set
+
+#
+# Generic Driver Options
+#
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+
+#
+# Firmware loader
+#
+CONFIG_FW_LOADER=y
+CONFIG_EXTRA_FIRMWARE="mrvl/sd8897_uapsta.bin mrvl/sd8797_uapsta.bin"
+CONFIG_EXTRA_FIRMWARE_DIR="/lib/firmware"
+# CONFIG_FW_LOADER_USER_HELPER is not set
+# CONFIG_FW_LOADER_COMPRESS is not set
+# end of Firmware loader
+
+CONFIG_WANT_DEV_COREDUMP=y
+CONFIG_ALLOW_DEV_COREDUMP=y
+CONFIG_DEV_COREDUMP=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set
+# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_DMA_SHARED_BUFFER=y
+# CONFIG_DMA_FENCE_TRACE is not set
+# end of Generic Driver Options
+
+#
+# Bus devices
+#
+# CONFIG_MHI_BUS is not set
+# end of Bus devices
+
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+
+#
+# Firmware Drivers
+#
+
+#
+# ARM System Control and Management Interface Protocol
+#
+# end of ARM System Control and Management Interface Protocol
+
+# CONFIG_EDD is not set
+CONFIG_FIRMWARE_MEMMAP=y
+CONFIG_DMIID=y
+CONFIG_DMI_SYSFS=y
+CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
+# CONFIG_FW_CFG_SYSFS is not set
+CONFIG_SYSFB=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+# CONFIG_GOOGLE_FIRMWARE is not set
+
+#
+# Tegra firmware driver
+#
+# end of Tegra firmware driver
+# end of Firmware Drivers
+
+# CONFIG_GNSS is not set
+# CONFIG_MTD is not set
+# CONFIG_OF is not set
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_PARPORT is not set
+CONFIG_PNP=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+
+#
+# Protocols
+#
+CONFIG_PNPACPI=y
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_NULL_BLK is not set
+# CONFIG_BLK_DEV_FD is not set
+CONFIG_CDROM=y
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=32768
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_BLK_DEV_RSXX is not set
+
+#
+# NVME Support
+#
+# CONFIG_BLK_DEV_NVME is not set
+# CONFIG_NVME_FC is not set
+# CONFIG_NVME_TCP is not set
+# CONFIG_NVME_TARGET is not set
+# end of NVME Support
+
+#
+# Misc devices
+#
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_IBM_ASM is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SRAM is not set
+# CONFIG_DW_XDATA_PCIE is not set
+# CONFIG_PCI_ENDPOINT_TEST is not set
+# CONFIG_XILINX_SDFEC is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_LEGACY=y
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_EEPROM_IDT_89HPESX is not set
+# CONFIG_EEPROM_EE1004 is not set
+# end of EEPROM support
+
+# CONFIG_CB710_CORE is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# end of Texas Instruments shared transport line discipline
+
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_ALTERA_STAPL is not set
+# CONFIG_INTEL_MEI is not set
+# CONFIG_INTEL_MEI_ME is not set
+# CONFIG_INTEL_MEI_TXE is not set
+# CONFIG_VMWARE_VMCI is not set
+# CONFIG_GENWQE is not set
+# CONFIG_ECHO is not set
+# CONFIG_BCM_VK is not set
+# CONFIG_MISC_ALCOR_PCI is not set
+# CONFIG_MISC_RTSX_PCI is not set
+# CONFIG_MISC_RTSX_USB is not set
+# CONFIG_HABANA_AI is not set
+# CONFIG_UACCE is not set
+# CONFIG_PVPANIC is not set
+# end of Misc devices
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI_COMMON=y
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# end of SCSI Transports
+
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# end of SCSI device support
+
+CONFIG_ATA=y
+CONFIG_SATA_HOST=y
+CONFIG_PATA_TIMINGS=y
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_ATA_FORCE=y
+CONFIG_ATA_ACPI=y
+CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_MOBILE_LPM_POLICY=0
+# CONFIG_SATA_AHCI_PLATFORM is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+# CONFIG_ATA_SFF is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_BCACHE is not set
+CONFIG_BLK_DEV_DM_BUILTIN=y
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_DEBUG is not set
+# CONFIG_DM_UNSTRIPED is not set
+CONFIG_DM_CRYPT=y
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_THIN_PROVISIONING is not set
+# CONFIG_DM_CACHE is not set
+# CONFIG_DM_WRITECACHE is not set
+# CONFIG_DM_EBS is not set
+# CONFIG_DM_ERA is not set
+# CONFIG_DM_CLONE is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_RAID is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_DUST is not set
+# CONFIG_DM_INIT is not set
+# CONFIG_DM_UEVENT is not set
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_DM_VERITY is not set
+# CONFIG_DM_SWITCH is not set
+# CONFIG_DM_LOG_WRITES is not set
+# CONFIG_DM_INTEGRITY is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# end of IEEE 1394 (FireWire) support
+
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+CONFIG_WIREGUARD=y
+# CONFIG_WIREGUARD_DEBUG is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_IPVLAN is not set
+# CONFIG_VXLAN is not set
+# CONFIG_GENEVE is not set
+# CONFIG_BAREUDP is not set
+# CONFIG_GTP is not set
+# CONFIG_MACSEC is not set
+CONFIG_NETCONSOLE=y
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_TUN is not set
+# CONFIG_TUN_VNET_CROSS_LE is not set
+# CONFIG_VETH is not set
+# CONFIG_NLMON is not set
+# CONFIG_ARCNET is not set
+CONFIG_ETHERNET=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_AGERE is not set
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_ALTERA_TSE is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CADENCE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_CX_ECAT is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_GOOGLE is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICROSOFT is not set
+# CONFIG_JME is not set
+# CONFIG_NET_VENDOR_LITEX is not set
+CONFIG_NET_VENDOR_MARVELL=y
+# CONFIG_MVMDIO is not set
+# CONFIG_SKGE is not set
+CONFIG_SKY2=y
+# CONFIG_SKY2_DEBUG is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETERION is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_ETHOC is not set
+# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
+# CONFIG_NET_VENDOR_PENSANDO is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_NET_VENDOR_XILINX is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_NET_SB1000 is not set
+CONFIG_PHYLIB=y
+CONFIG_SWPHY=y
+# CONFIG_LED_TRIGGER_PHY is not set
+CONFIG_FIXED_PHY=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_AMD_PHY is not set
+# CONFIG_ADIN_PHY is not set
+# CONFIG_AQUANTIA_PHY is not set
+# CONFIG_AX88796B_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_BCM54140_PHY is not set
+# CONFIG_BCM7XXX_PHY is not set
+# CONFIG_BCM84881_PHY is not set
+# CONFIG_BCM87XX_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_CORTINA_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_INTEL_XWAY_PHY is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+CONFIG_MARVELL_PHY=y
+# CONFIG_MARVELL_10G_PHY is not set
+# CONFIG_MARVELL_88X2222_PHY is not set
+# CONFIG_MAXLINEAR_GPHY is not set
+# CONFIG_MEDIATEK_GE_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_MICROCHIP_PHY is not set
+# CONFIG_MICROCHIP_T1_PHY is not set
+# CONFIG_MICROSEMI_PHY is not set
+# CONFIG_MOTORCOMM_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_NXP_C45_TJA11XX_PHY is not set
+# CONFIG_NXP_TJA11XX_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_RENESAS_PHY is not set
+# CONFIG_ROCKCHIP_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_TERANETICS_PHY is not set
+# CONFIG_DP83822_PHY is not set
+# CONFIG_DP83TC811_PHY is not set
+# CONFIG_DP83848_PHY is not set
+# CONFIG_DP83867_PHY is not set
+# CONFIG_DP83869_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_XILINX_GMII2RGMII is not set
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_BUS=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_ACPI_MDIO=y
+CONFIG_MDIO_DEVRES=y
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MDIO_BCM_UNIMAC is not set
+# CONFIG_MDIO_MVUSB is not set
+# CONFIG_MDIO_MSCC_MIIM is not set
+# CONFIG_MDIO_THUNDER is not set
+
+#
+# MDIO Multiplexers
+#
+
+#
+# PCS device drivers
+#
+# CONFIG_PCS_XPCS is not set
+# end of PCS device drivers
+
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_USB_NET_DRIVERS is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+# CONFIG_WLAN_VENDOR_BROADCOM is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+CONFIG_WLAN_VENDOR_MARVELL=y
+# CONFIG_LIBERTAS is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_MWIFIEX=y
+CONFIG_MWIFIEX_SDIO=y
+# CONFIG_MWIFIEX_PCIE is not set
+# CONFIG_MWIFIEX_USB is not set
+# CONFIG_MWL8K is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+CONFIG_WLAN_VENDOR_MICROCHIP=y
+# CONFIG_WILC1000_SDIO is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+# CONFIG_WLAN_VENDOR_REALTEK is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+# CONFIG_WLAN_VENDOR_QUANTENNA is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_VIRT_WIFI is not set
+# CONFIG_WAN is not set
+
+#
+# Wireless WAN
+#
+# CONFIG_WWAN is not set
+# end of Wireless WAN
+
+# CONFIG_VMXNET3 is not set
+# CONFIG_FUJITSU_ES is not set
+# CONFIG_NETDEVSIM is not set
+# CONFIG_NET_FAILOVER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_SPARSEKMAP is not set
+# CONFIG_INPUT_MATRIXKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1280
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=1024
+CONFIG_INPUT_JOYDEV=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_QT1050 is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_DLINK_DIR685 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+# CONFIG_MOUSE_ELAN_I2C is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_MOUSE_SYNAPTICS_USB is not set
+CONFIG_INPUT_JOYSTICK=y
+# CONFIG_JOYSTICK_ANALOG is not set
+# CONFIG_JOYSTICK_A3D is not set
+# CONFIG_JOYSTICK_ADI is not set
+# CONFIG_JOYSTICK_COBRA is not set
+# CONFIG_JOYSTICK_GF2K is not set
+# CONFIG_JOYSTICK_GRIP is not set
+# CONFIG_JOYSTICK_GRIP_MP is not set
+# CONFIG_JOYSTICK_GUILLEMOT is not set
+# CONFIG_JOYSTICK_INTERACT is not set
+# CONFIG_JOYSTICK_SIDEWINDER is not set
+# CONFIG_JOYSTICK_TMDC is not set
+# CONFIG_JOYSTICK_IFORCE is not set
+# CONFIG_JOYSTICK_WARRIOR is not set
+# CONFIG_JOYSTICK_MAGELLAN is not set
+# CONFIG_JOYSTICK_SPACEORB is not set
+# CONFIG_JOYSTICK_SPACEBALL is not set
+# CONFIG_JOYSTICK_STINGER is not set
+# CONFIG_JOYSTICK_TWIDJOY is not set
+# CONFIG_JOYSTICK_ZHENHUA is not set
+# CONFIG_JOYSTICK_AS5011 is not set
+# CONFIG_JOYSTICK_JOYDUMP is not set
+CONFIG_JOYSTICK_XPAD=y
+CONFIG_JOYSTICK_XPAD_FF=y
+# CONFIG_JOYSTICK_XPAD_LEDS is not set
+# CONFIG_JOYSTICK_PXRC is not set
+# CONFIG_JOYSTICK_QWIIC is not set
+# CONFIG_JOYSTICK_FSIA6B is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_E3X0_BUTTON is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_APANEL is not set
+# CONFIG_INPUT_ATLAS_BTNS is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_DA7280_HAPTICS is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_IMS_PCU is not set
+# CONFIG_INPUT_IQS269A is not set
+# CONFIG_INPUT_IQS626A is not set
+# CONFIG_INPUT_CMA3000 is not set
+# CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set
+# CONFIG_INPUT_DRV2665_HAPTICS is not set
+# CONFIG_INPUT_DRV2667_HAPTICS is not set
+# CONFIG_RMI4_CORE is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_SERIO_ARC_PS2 is not set
+# CONFIG_USERIO is not set
+# CONFIG_GAMEPORT is not set
+# end of Hardware I/O ports
+# end of Input device support
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_LDISC_AUTOLOAD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_PNP=y
+# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
+# CONFIG_SERIAL_8250_FINTEK is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DMA=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+# CONFIG_SERIAL_8250_DW is not set
+# CONFIG_SERIAL_8250_RT288X is not set
+# CONFIG_SERIAL_8250_LPSS is not set
+# CONFIG_SERIAL_8250_MID is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_SERIAL_LANTIQ=y
+# CONFIG_SERIAL_LANTIQ_CONSOLE is not set
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_SC16IS7XX is not set
+# CONFIG_SERIAL_BCM63XX is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_RP2 is not set
+# CONFIG_SERIAL_FSL_LPUART is not set
+# CONFIG_SERIAL_FSL_LINFLEXUART is not set
+# CONFIG_SERIAL_SPRD is not set
+# end of Serial drivers
+
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_NULL_TTY is not set
+# CONFIG_SERIAL_DEV_BUS is not set
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_VIRTIO_CONSOLE is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_IPMB_DEVICE_INTERFACE is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_HW_RANDOM_INTEL is not set
+CONFIG_HW_RANDOM_AMD=y
+# CONFIG_HW_RANDOM_BA431 is not set
+# CONFIG_HW_RANDOM_VIA is not set
+# CONFIG_HW_RANDOM_XIPHERA is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_MWAVE is not set
+CONFIG_DEVMEM=y
+CONFIG_NVRAM=y
+CONFIG_DEVPORT=y
+# CONFIG_HPET is not set
+# CONFIG_HANGCHECK_TIMER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+# CONFIG_XILLYBUS is not set
+# CONFIG_XILLYUSB is not set
+# CONFIG_RANDOM_TRUST_CPU is not set
+# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
+# end of Character devices
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+
+#
+# Multiplexer I2C Chip support
+#
+# CONFIG_I2C_MUX_LTC4306 is not set
+# CONFIG_I2C_MUX_PCA9541 is not set
+# CONFIG_I2C_MUX_REG is not set
+# CONFIG_I2C_MUX_MLXCPLD is not set
+# end of Multiplexer I2C Chip support
+
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_AMD_MP2 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_ISMT is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_NVIDIA_GPU is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# ACPI drivers
+#
+# CONFIG_I2C_SCMI is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_EMEV2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_CP2615 is not set
+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_MLXCPLD is not set
+# CONFIG_I2C_VIRTIO is not set
+# end of I2C Hardware Bus support
+
+# CONFIG_I2C_STUB is not set
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SLAVE_EEPROM=y
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
+CONFIG_I2C_DEBUG_CORE=y
+CONFIG_I2C_DEBUG_ALGO=y
+CONFIG_I2C_DEBUG_BUS=y
+# end of I2C support
+
+# CONFIG_I3C is not set
+# CONFIG_SPI is not set
+# CONFIG_SPMI is not set
+# CONFIG_HSI is not set
+# CONFIG_PPS is not set
+
+#
+# PTP clock support
+#
+# CONFIG_PTP_1588_CLOCK is not set
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+# end of PTP clock support
+
+# CONFIG_PINCTRL is not set
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_RESET is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_POWER_SUPPLY_HWMON is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_CHARGER_ADP5061 is not set
+# CONFIG_BATTERY_CW2015 is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_CHARGER_SBS is not set
+# CONFIG_BATTERY_BQ27XXX is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_LTC4162L is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_BATTERY_GAUGE_LTC2941 is not set
+# CONFIG_BATTERY_GOLDFISH is not set
+# CONFIG_BATTERY_RT5033 is not set
+# CONFIG_CHARGER_BD99954 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_ABITUGURU3 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM1177 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7410 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_AHT10 is not set
+# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set
+# CONFIG_SENSORS_AS370 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_AXI_FAN_CONTROL is not set
+CONFIG_SENSORS_K8TEMP=y
+CONFIG_SENSORS_K10TEMP=y
+CONFIG_SENSORS_FAM15H_POWER=y
+# CONFIG_SENSORS_APPLESMC is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ASPEED is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_CORSAIR_CPRO is not set
+# CONFIG_SENSORS_CORSAIR_PSU is not set
+# CONFIG_SENSORS_DRIVETEMP is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_DELL_SMM is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_FSCHMD is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_G762 is not set
+# CONFIG_SENSORS_HIH6130 is not set
+# CONFIG_SENSORS_I5500 is not set
+# CONFIG_SENSORS_CORETEMP is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_POWR1220 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LTC2945 is not set
+# CONFIG_SENSORS_LTC2947_I2C is not set
+# CONFIG_SENSORS_LTC2990 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4222 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4260 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_MAX127 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX197 is not set
+# CONFIG_SENSORS_MAX31730 is not set
+# CONFIG_SENSORS_MAX6621 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MAX6697 is not set
+# CONFIG_SENSORS_MAX31790 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_TC654 is not set
+# CONFIG_SENSORS_TPS23861 is not set
+# CONFIG_SENSORS_MR75203 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LM95234 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_NCT6683 is not set
+# CONFIG_SENSORS_NCT6775 is not set
+# CONFIG_SENSORS_NCT7802 is not set
+# CONFIG_SENSORS_NPCM7XX is not set
+# CONFIG_SENSORS_NZXT_KRAKEN2 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SBTSI is not set
+# CONFIG_SENSORS_SBRMI is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SHT3x is not set
+# CONFIG_SENSORS_SHT4x is not set
+# CONFIG_SENSORS_SHTC1 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_STTS751 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_ADC128D818 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_INA209 is not set
+# CONFIG_SENSORS_INA2XX is not set
+# CONFIG_SENSORS_INA3221 is not set
+# CONFIG_SENSORS_TC74 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP103 is not set
+# CONFIG_SENSORS_TMP108 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_TMP513 is not set
+# CONFIG_SENSORS_VIA_CPUTEMP is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83773G is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+
+#
+# ACPI drivers
+#
+# CONFIG_SENSORS_ACPI_POWER is not set
+# CONFIG_SENSORS_ATK0110 is not set
+CONFIG_THERMAL=y
+# CONFIG_THERMAL_NETLINK is not set
+# CONFIG_THERMAL_STATISTICS is not set
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_THERMAL_WRITABLE_TRIPS is not set
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
+CONFIG_THERMAL_GOV_STEP_WISE=y
+# CONFIG_THERMAL_GOV_BANG_BANG is not set
+# CONFIG_THERMAL_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_EMULATION is not set
+
+#
+# Intel thermal drivers
+#
+# CONFIG_INTEL_SOC_DTS_THERMAL is not set
+
+#
+# ACPI INT340X thermal drivers
+#
+# CONFIG_INT340X_THERMAL is not set
+# end of ACPI INT340X thermal drivers
+
+# CONFIG_INTEL_PCH_THERMAL is not set
+# CONFIG_INTEL_TCC_COOLING is not set
+# CONFIG_INTEL_MENLOW is not set
+# end of Intel thermal drivers
+
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_BCM590XX is not set
+# CONFIG_MFD_BD9571MWV is not set
+# CONFIG_MFD_AXP20X_I2C is not set
+# CONFIG_MFD_MADERA is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
+# CONFIG_MFD_DA9062 is not set
+# CONFIG_MFD_DA9063 is not set
+# CONFIG_MFD_DA9150 is not set
+# CONFIG_MFD_DLN2 is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_MFD_MP2629 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set
+# CONFIG_LPC_ICH is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_INTEL_LPSS_ACPI is not set
+# CONFIG_MFD_INTEL_LPSS_PCI is not set
+# CONFIG_MFD_INTEL_PMT is not set
+# CONFIG_MFD_IQS62X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_KEMPLD is not set
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_MAX14577 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX77843 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MT6360 is not set
+# CONFIG_MFD_MT6397 is not set
+# CONFIG_MFD_MENF21BMC is not set
+# CONFIG_MFD_VIPERBOARD is not set
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_RT4831 is not set
+# CONFIG_MFD_RT5033 is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_MFD_SI476X_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SKY81452 is not set
+# CONFIG_MFD_SYSCON is not set
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_LP3943 is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_TI_LMU is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65086 is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TI_LP873X is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS80031 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_TQMX86 is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_ATC260X_I2C is not set
+# end of Multifunction device drivers
+
+# CONFIG_REGULATOR is not set
+# CONFIG_RC_CORE is not set
+CONFIG_MEDIA_CEC_SUPPORT=y
+# CONFIG_CEC_CH7322 is not set
+# CONFIG_CEC_SECO is not set
+# CONFIG_USB_PULSE8_CEC is not set
+# CONFIG_USB_RAINSHADOW_CEC is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+CONFIG_AGP=y
+CONFIG_AGP_AMD64=y
+# CONFIG_AGP_INTEL is not set
+# CONFIG_AGP_SIS is not set
+# CONFIG_AGP_VIA is not set
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=2
+# CONFIG_VGA_SWITCHEROO is not set
+CONFIG_DRM=y
+# CONFIG_DRM_DP_AUX_CHARDEV is not set
+# CONFIG_DRM_DEBUG_MM is not set
+# CONFIG_DRM_DEBUG_SELFTEST is not set
+CONFIG_DRM_KMS_HELPER=y
+# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+# CONFIG_DRM_DP_CEC is not set
+CONFIG_DRM_TTM=y
+CONFIG_DRM_TTM_HELPER=y
+CONFIG_DRM_SCHED=y
+
+#
+# I2C encoder or helper chips
+#
+# CONFIG_DRM_I2C_CH7006 is not set
+# CONFIG_DRM_I2C_SIL164 is not set
+# CONFIG_DRM_I2C_NXP_TDA998X is not set
+# CONFIG_DRM_I2C_NXP_TDA9950 is not set
+# end of I2C encoder or helper chips
+
+#
+# ARM devices
+#
+# end of ARM devices
+
+# CONFIG_DRM_RADEON is not set
+CONFIG_DRM_AMDGPU=y
+# CONFIG_DRM_AMDGPU_SI is not set
+CONFIG_DRM_AMDGPU_CIK=y
+# CONFIG_DRM_AMDGPU_USERPTR is not set
+
+#
+# ACP (Audio CoProcessor) Configuration
+#
+# CONFIG_DRM_AMD_ACP is not set
+# end of ACP (Audio CoProcessor) Configuration
+
+#
+# Display Engine Configuration
+#
+CONFIG_DRM_AMD_DC=y
+CONFIG_DRM_AMD_DC_DCN=y
+CONFIG_DRM_AMD_DC_HDCP=y
+CONFIG_DRM_AMD_SECURE_DISPLAY=y
+# end of Display Engine Configuration
+
+# CONFIG_HSA_AMD is not set
+# CONFIG_DRM_NOUVEAU is not set
+# CONFIG_DRM_I915 is not set
+# CONFIG_DRM_VGEM is not set
+# CONFIG_DRM_VKMS is not set
+# CONFIG_DRM_VMWGFX is not set
+# CONFIG_DRM_GMA500 is not set
+# CONFIG_DRM_UDL is not set
+# CONFIG_DRM_AST is not set
+# CONFIG_DRM_MGAG200 is not set
+# CONFIG_DRM_QXL is not set
+CONFIG_DRM_PANEL=y
+
+#
+# Display Panels
+#
+# end of Display Panels
+
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_PANEL_BRIDGE=y
+
+#
+# Display Interface Bridges
+#
+# CONFIG_DRM_ANALOGIX_ANX78XX is not set
+# end of Display Interface Bridges
+
+# CONFIG_DRM_ETNAVIV is not set
+# CONFIG_DRM_BOCHS is not set
+# CONFIG_DRM_CIRRUS_QEMU is not set
+# CONFIG_DRM_GM12U320 is not set
+# CONFIG_DRM_SIMPLEDRM is not set
+# CONFIG_DRM_VBOXVIDEO is not set
+# CONFIG_DRM_GUD is not set
+# CONFIG_DRM_LEGACY is not set
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+
+#
+# Frame buffer Devices
+#
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_NOTIFY=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FB_BOOT_VESA_SUPPORT=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ARC is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_VGA16 is not set
+# CONFIG_FB_UVESA is not set
+CONFIG_FB_VESA=y
+# CONFIG_FB_N411 is not set
+# CONFIG_FB_HGA is not set
+# CONFIG_FB_OPENCORES is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_LE80578 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+CONFIG_FB_SIMPLE=y
+# CONFIG_FB_SM712 is not set
+# end of Frame buffer Devices
+
+#
+# Backlight & LCD device support
+#
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_APPLE is not set
+# CONFIG_BACKLIGHT_QCOM_WLED is not set
+# CONFIG_BACKLIGHT_SAHARA is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_LM3639 is not set
+# CONFIG_BACKLIGHT_LV5207LP is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+# CONFIG_BACKLIGHT_ARCXCNN is not set
+# end of Backlight & LCD device support
+
+CONFIG_HDMI=y
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE_ROWS=25
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set
+# end of Console display driver support
+
+# CONFIG_LOGO is not set
+# end of Graphics support
+
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_SEQ_DEVICE=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_HRTIMER=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_MAX_CARDS=16
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_PROC_FS=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_DMA_SGBUF=y
+CONFIG_SND_CTL_LED=y
+CONFIG_SND_SEQUENCER=y
+# CONFIG_SND_SEQ_DUMMY is not set
+# CONFIG_SND_SEQUENCER_OSS is not set
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_ALOOP is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALS4000 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ASIHPI is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CTXFI is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_INDIGOIOX is not set
+# CONFIG_SND_INDIGODJX is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_LOLA is not set
+# CONFIG_SND_LX6464ES is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SE6X is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+
+#
+# HD-Audio
+#
+CONFIG_SND_HDA=y
+CONFIG_SND_HDA_GENERIC_LEDS=y
+CONFIG_SND_HDA_INTEL=y
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_RECONFIG=y
+CONFIG_SND_HDA_INPUT_BEEP=y
+CONFIG_SND_HDA_INPUT_BEEP_MODE=1
+CONFIG_SND_HDA_PATCH_LOADER=y
+CONFIG_SND_HDA_CODEC_REALTEK=y
+CONFIG_SND_HDA_CODEC_ANALOG=y
+CONFIG_SND_HDA_CODEC_SIGMATEL=y
+CONFIG_SND_HDA_CODEC_VIA=y
+CONFIG_SND_HDA_CODEC_HDMI=y
+CONFIG_SND_HDA_CODEC_CIRRUS=y
+# CONFIG_SND_HDA_CODEC_CS8409 is not set
+CONFIG_SND_HDA_CODEC_CONEXANT=y
+CONFIG_SND_HDA_CODEC_CA0110=y
+CONFIG_SND_HDA_CODEC_CA0132=y
+CONFIG_SND_HDA_CODEC_CA0132_DSP=y
+CONFIG_SND_HDA_CODEC_CMEDIA=y
+CONFIG_SND_HDA_CODEC_SI3054=y
+CONFIG_SND_HDA_GENERIC=y
+# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set
+# end of HD-Audio
+
+CONFIG_SND_HDA_CORE=y
+CONFIG_SND_HDA_DSP_LOADER=y
+CONFIG_SND_HDA_COMPONENT=y
+CONFIG_SND_HDA_PREALLOC_SIZE=0
+CONFIG_SND_INTEL_NHLT=y
+CONFIG_SND_INTEL_DSP_CONFIG=y
+CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_SOC is not set
+CONFIG_SND_X86=y
+
+#
+# HID support
+#
+CONFIG_HID=y
+# CONFIG_HID_BATTERY_STRENGTH is not set
+CONFIG_HIDRAW=y
+CONFIG_UHID=y
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACCUTOUCH is not set
+# CONFIG_HID_ACRUX is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_APPLEIR is not set
+# CONFIG_HID_ASUS is not set
+# CONFIG_HID_AUREAL is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_BETOP_FF is not set
+# CONFIG_HID_BIGBEN_FF is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CORSAIR is not set
+# CONFIG_HID_COUGAR is not set
+# CONFIG_HID_MACALLY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CMEDIA is not set
+# CONFIG_HID_CREATIVE_SB0540 is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELAN is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_ELO is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_FT260 is not set
+# CONFIG_HID_GEMBIRD is not set
+# CONFIG_HID_GFRM is not set
+# CONFIG_HID_GLORIOUS is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_VIVALDI is not set
+# CONFIG_HID_GT683R is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_VIEWSONIC is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_ICADE is not set
+# CONFIG_HID_ITE is not set
+# CONFIG_HID_JABRA is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LED is not set
+# CONFIG_HID_LENOVO is not set
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_LOGITECH_DJ=y
+CONFIG_HID_LOGITECH_HIDPP=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGIG940_FF is not set
+# CONFIG_LOGIWHEELS_FF is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MALTRON is not set
+# CONFIG_HID_MAYFLASH is not set
+# CONFIG_HID_REDRAGON is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTI is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PENMOUNT is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PLANTRONICS is not set
+CONFIG_HID_PLAYSTATION=y
+CONFIG_PLAYSTATION_FF=y
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_RETRODE is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SEMITEK is not set
+CONFIG_HID_SONY=y
+CONFIG_SONY_FF=y
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_STEAM is not set
+# CONFIG_HID_STEELSERIES is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_RMI is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THINGM is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_UDRAW_PS3 is not set
+# CONFIG_HID_U2FZERO is not set
+# CONFIG_HID_WACOM is not set
+CONFIG_HID_WIIMOTE=y
+# CONFIG_HID_XINMO is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+# CONFIG_HID_SENSOR_HUB is not set
+# CONFIG_HID_ALPS is not set
+# end of Special HID drivers
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+# end of USB HID support
+
+#
+# I2C HID support
+#
+# CONFIG_I2C_HID_ACPI is not set
+# end of I2C HID support
+
+#
+# Intel ISH HID support
+#
+# CONFIG_INTEL_ISH_HID is not set
+# end of Intel ISH HID support
+
+#
+# AMD SFH HID Support
+#
+# CONFIG_AMD_SFH_HID is not set
+# end of AMD SFH HID Support
+# end of HID support
+
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+# CONFIG_USB_LED_TRIG is not set
+# CONFIG_USB_ULPI_BUS is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+CONFIG_USB_PCI=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_FEW_INIT_RETRIES is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG_PRODUCTLIST is not set
+# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
+# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set
+CONFIG_USB_AUTOSUSPEND_DELAY=2
+# CONFIG_USB_MON is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_DBGCAP is not set
+CONFIG_USB_XHCI_PCI=y
+# CONFIG_USB_XHCI_PCI_RENESAS is not set
+# CONFIG_USB_XHCI_PLATFORM is not set
+CONFIG_USB_XHCI_AEOLIA=y
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_FOTG210_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HCD_TEST_MODE is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+CONFIG_USB_UAS=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USB_CDNS_SUPPORT is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_DWC3 is not set
+# CONFIG_USB_DWC2 is not set
+# CONFIG_USB_ISP1760 is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_APPLE_MFI_FASTCHARGE is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_EHSET_TEST_FIXTURE is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_HUB_USB251XB is not set
+# CONFIG_USB_HSIC_USB3503 is not set
+# CONFIG_USB_HSIC_USB4604 is not set
+# CONFIG_USB_LINK_LAYER_TEST is not set
+# CONFIG_USB_CHAOSKEY is not set
+
+#
+# USB Physical Layer drivers
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_USB_ISP1301 is not set
+# end of USB Physical Layer drivers
+
+# CONFIG_USB_GADGET is not set
+# CONFIG_TYPEC is not set
+# CONFIG_USB_ROLE_SWITCH is not set
+CONFIG_MMC=y
+# CONFIG_MMC_BLOCK is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_PCI=y
+# CONFIG_MMC_RICOH_MMC is not set
+# CONFIG_MMC_SDHCI_ACPI is not set
+# CONFIG_MMC_SDHCI_PLTFM is not set
+# CONFIG_MMC_WBSD is not set
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MMC_USDHI6ROL0 is not set
+CONFIG_MMC_CQHCI=y
+# CONFIG_MMC_HSQ is not set
+# CONFIG_MMC_TOSHIBA_PCI is not set
+# CONFIG_MMC_MTK is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+# CONFIG_LEDS_CLASS_FLASH is not set
+# CONFIG_LEDS_CLASS_MULTICOLOR is not set
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_APU is not set
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_LM3532 is not set
+# CONFIG_LEDS_LM3642 is not set
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP50XX is not set
+# CONFIG_LEDS_CLEVO_MAIL is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA963X is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_INTEL_SS4200 is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_TLC591XX is not set
+# CONFIG_LEDS_LM355x is not set
+
+#
+# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM)
+#
+# CONFIG_LEDS_BLINKM is not set
+# CONFIG_LEDS_MLXCPLD is not set
+# CONFIG_LEDS_MLXREG is not set
+# CONFIG_LEDS_USER is not set
+# CONFIG_LEDS_NIC78BX is not set
+# CONFIG_LEDS_TI_LMU_COMMON is not set
+
+#
+# Flash and Torch LED drivers
+#
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_ONESHOT is not set
+# CONFIG_LEDS_TRIGGER_DISK is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_CPU is not set
+# CONFIG_LEDS_TRIGGER_ACTIVITY is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_LEDS_TRIGGER_TRANSIENT is not set
+# CONFIG_LEDS_TRIGGER_CAMERA is not set
+# CONFIG_LEDS_TRIGGER_PANIC is not set
+# CONFIG_LEDS_TRIGGER_NETDEV is not set
+# CONFIG_LEDS_TRIGGER_PATTERN is not set
+CONFIG_LEDS_TRIGGER_AUDIO=y
+# CONFIG_LEDS_TRIGGER_TTY is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+# CONFIG_EDAC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_MC146818_LIB=y
+# CONFIG_RTC_CLASS is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMADEVICES_DEBUG=y
+CONFIG_DMADEVICES_VDEBUG=y
+
+#
+# DMA Devices
+#
+CONFIG_DMA_ACPI=y
+# CONFIG_ALTERA_MSGDMA is not set
+# CONFIG_INTEL_IDMA64 is not set
+# CONFIG_INTEL_IDXD is not set
+# CONFIG_INTEL_IDXD_COMPAT is not set
+# CONFIG_INTEL_IOATDMA is not set
+# CONFIG_PLX_DMA is not set
+# CONFIG_AMD_PTDMA is not set
+# CONFIG_QCOM_HIDMA_MGMT is not set
+# CONFIG_QCOM_HIDMA is not set
+# CONFIG_DW_DMAC is not set
+# CONFIG_DW_DMAC_PCI is not set
+# CONFIG_DW_EDMA is not set
+# CONFIG_DW_EDMA_PCIE is not set
+# CONFIG_SF_PDMA is not set
+# CONFIG_INTEL_LDMA is not set
+
+#
+# DMABUF options
+#
+CONFIG_SYNC_FILE=y
+# CONFIG_SW_SYNC is not set
+# CONFIG_UDMABUF is not set
+# CONFIG_DMABUF_MOVE_NOTIFY is not set
+# CONFIG_DMABUF_DEBUG is not set
+# CONFIG_DMABUF_SELFTESTS is not set
+# CONFIG_DMABUF_HEAPS is not set
+# CONFIG_DMABUF_SYSFS_STATS is not set
+# end of DMABUF options
+
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=y
+# CONFIG_UIO_CIF is not set
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_DMEM_GENIRQ=y
+# CONFIG_UIO_AEC is not set
+# CONFIG_UIO_SERCOS3 is not set
+CONFIG_UIO_PCI_GENERIC=y
+# CONFIG_UIO_NETX is not set
+# CONFIG_UIO_PRUSS is not set
+# CONFIG_UIO_MF624 is not set
+# CONFIG_VFIO is not set
+CONFIG_IRQ_BYPASS_MANAGER=y
+# CONFIG_VIRT_DRIVERS is not set
+# CONFIG_VIRTIO_MENU is not set
+# CONFIG_VDPA is not set
+CONFIG_VHOST_MENU=y
+# CONFIG_VHOST_NET is not set
+# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+# end of Microsoft Hyper-V guest support
+
+# CONFIG_GREYBUS is not set
+# CONFIG_COMEDI is not set
+# CONFIG_STAGING is not set
+# CONFIG_X86_PLATFORM_DEVICES is not set
+CONFIG_PMC_ATOM=y
+# CONFIG_CHROME_PLATFORMS is not set
+# CONFIG_MELLANOX_PLATFORM is not set
+# CONFIG_SURFACE_PLATFORMS is not set
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+
+#
+# Clock driver for ARM Reference designs
+#
+# CONFIG_ICST is not set
+# CONFIG_CLK_SP810 is not set
+# end of Clock driver for ARM Reference designs
+
+# CONFIG_COMMON_CLK_MAX9485 is not set
+# CONFIG_COMMON_CLK_SI5341 is not set
+# CONFIG_COMMON_CLK_SI5351 is not set
+# CONFIG_COMMON_CLK_SI544 is not set
+# CONFIG_COMMON_CLK_CDCE706 is not set
+# CONFIG_COMMON_CLK_CS2000_CP is not set
+# CONFIG_XILINX_VCU is not set
+# CONFIG_HWSPINLOCK is not set
+
+#
+# Clock Source drivers
+#
+CONFIG_CLKEVT_I8253=y
+CONFIG_CLKBLD_I8253=y
+# end of Clock Source drivers
+
+# CONFIG_MAILBOX is not set
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_API=y
+CONFIG_IOMMU_SUPPORT=y
+
+#
+# Generic IOMMU Pagetable Support
+#
+CONFIG_IOMMU_IO_PGTABLE=y
+# end of Generic IOMMU Pagetable Support
+
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
+CONFIG_IOMMU_DMA=y
+CONFIG_AMD_IOMMU=y
+# CONFIG_AMD_IOMMU_V2 is not set
+CONFIG_DMAR_TABLE=y
+# CONFIG_INTEL_IOMMU is not set
+CONFIG_IRQ_REMAP=y
+
+#
+# Remoteproc drivers
+#
+# CONFIG_REMOTEPROC is not set
+# end of Remoteproc drivers
+
+#
+# Rpmsg drivers
+#
+# CONFIG_RPMSG_VIRTIO is not set
+# end of Rpmsg drivers
+
+# CONFIG_SOUNDWIRE is not set
+
+#
+# SOC (System On Chip) specific Drivers
+#
+
+#
+# Amlogic SoC drivers
+#
+# end of Amlogic SoC drivers
+
+#
+# Broadcom SoC drivers
+#
+# end of Broadcom SoC drivers
+
+#
+# NXP/Freescale QorIQ SoC drivers
+#
+# end of NXP/Freescale QorIQ SoC drivers
+
+#
+# i.MX SoC drivers
+#
+# end of i.MX SoC drivers
+
+#
+# Enable LiteX SoC Builder specific drivers
+#
+# end of Enable LiteX SoC Builder specific drivers
+
+#
+# Qualcomm SoC drivers
+#
+# end of Qualcomm SoC drivers
+
+# CONFIG_SOC_TI is not set
+
+#
+# Xilinx SoC drivers
+#
+# end of Xilinx SoC drivers
+# end of SOC (System On Chip) specific Drivers
+
+# CONFIG_PM_DEVFREQ is not set
+# CONFIG_EXTCON is not set
+# CONFIG_MEMORY is not set
+# CONFIG_IIO is not set
+# CONFIG_NTB is not set
+# CONFIG_VME_BUS is not set
+# CONFIG_PWM is not set
+
+#
+# IRQ chip support
+#
+# end of IRQ chip support
+
+# CONFIG_IPACK_BUS is not set
+# CONFIG_RESET_CONTROLLER is not set
+
+#
+# PHY Subsystem
+#
+CONFIG_GENERIC_PHY=y
+# CONFIG_USB_LGM_PHY is not set
+# CONFIG_PHY_CAN_TRANSCEIVER is not set
+# CONFIG_BCM_KONA_USB2_PHY is not set
+# CONFIG_PHY_PXA_28NM_HSIC is not set
+# CONFIG_PHY_PXA_28NM_USB2 is not set
+# CONFIG_PHY_INTEL_LGM_EMMC is not set
+# end of PHY Subsystem
+
+# CONFIG_POWERCAP is not set
+# CONFIG_MCB is not set
+
+#
+# Performance monitor support
+#
+# end of Performance monitor support
+
+CONFIG_RAS=y
+# CONFIG_USB4 is not set
+
+#
+# Android
+#
+# CONFIG_ANDROID is not set
+# end of Android
+
+# CONFIG_LIBNVDIMM is not set
+CONFIG_DAX=y
+# CONFIG_DEV_DAX is not set
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+# CONFIG_NVMEM_RMEM is not set
+
+#
+# HW tracing support
+#
+# CONFIG_STM is not set
+# CONFIG_INTEL_TH is not set
+# end of HW tracing support
+
+# CONFIG_FPGA is not set
+# CONFIG_TEE is not set
+# CONFIG_UNISYS_VISORBUS is not set
+# CONFIG_SIOX is not set
+# CONFIG_SLIMBUS is not set
+# CONFIG_INTERCONNECT is not set
+# CONFIG_COUNTER is not set
+# CONFIG_MOST is not set
+# end of Device Drivers
+
+#
+# File systems
+#
+CONFIG_DCACHE_WORD_ACCESS=y
+# CONFIG_VALIDATE_FS_PARSER is not set
+CONFIG_FS_IOMAP=y
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_USE_FOR_EXT2=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_F2FS_FS is not set
+# CONFIG_FS_DAX is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+# CONFIG_EXPORTFS_BLOCK_OPS is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_FS_ENCRYPTION is not set
+# CONFIG_FS_VERITY is not set
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_FANOTIFY=y
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+# CONFIG_VIRTIO_FS is not set
+# CONFIG_OVERLAY_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+# end of Caches
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+# end of CD-ROM/DVD Filesystems
+
+#
+# DOS/FAT/EXFAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=850
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_FAT_DEFAULT_UTF8 is not set
+CONFIG_EXFAT_FS=y
+CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+CONFIG_NTFS3_FS=y
+CONFIG_NTFS3_64BIT_CLUSTER=y
+# CONFIG_NTFS3_LZX_XPRESS is not set
+# CONFIG_NTFS3_FS_POSIX_ACL is not set
+# end of DOS/FAT/EXFAT/NT Filesystems
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+# CONFIG_PROC_CHILDREN is not set
+CONFIG_PROC_PID_ARCH_STATUS=y
+CONFIG_KERNFS=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_TMPFS_INODE64 is not set
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HUGETLB_PAGE_FREE_VMEMMAP=y
+# CONFIG_HUGETLB_PAGE_FREE_VMEMMAP_DEFAULT_ON is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
+CONFIG_CONFIGFS_FS=y
+# end of Pseudo filesystems
+
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ORANGEFS_FS is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+CONFIG_UFS_FS=y
+CONFIG_UFS_FS_WRITE=y
+CONFIG_UFS_DEBUG=y
+# CONFIG_EROFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V2 is not set
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+# CONFIG_NFS_V4 is not set
+CONFIG_NFS_SWAP=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFS_DISABLE_UDP_SUPPORT=y
+# CONFIG_NFSD is not set
+CONFIG_GRACE_PERIOD=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_SWAP=y
+# CONFIG_SUNRPC_DEBUG is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_SMB_SERVER is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=y
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+# CONFIG_UNICODE is not set
+# end of File systems
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_REQUEST_CACHE is not set
+# CONFIG_PERSISTENT_KEYRINGS is not set
+# CONFIG_BIG_KEYS is not set
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEY_DH_OPERATIONS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_PAGE_TABLE_ISOLATION is not set
+CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
+# CONFIG_HARDENED_USERCOPY is not set
+# CONFIG_FORTIFY_SOURCE is not set
+# CONFIG_STATIC_USERMODEHELPER is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_LSM="yama,loadpin,safesetid,integrity"
+
+#
+# Kernel hardening options
+#
+
+#
+# Memory initialization
+#
+CONFIG_INIT_STACK_NONE=y
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set
+# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set
+# CONFIG_GCC_PLUGIN_STACKLEAK is not set
+# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set
+# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set
+CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y
+# CONFIG_ZERO_CALL_USED_REGS is not set
+# end of Memory initialization
+# end of Kernel hardening options
+# end of Security options
+
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_SKCIPHER=y
+CONFIG_CRYPTO_SKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_AKCIPHER=y
+CONFIG_CRYPTO_KPP2=y
+CONFIG_CRYPTO_KPP=y
+CONFIG_CRYPTO_ACOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_USER is not set
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_SIMD=y
+
+#
+# Public-key cryptography
+#
+CONFIG_CRYPTO_RSA=y
+# CONFIG_CRYPTO_DH is not set
+CONFIG_CRYPTO_ECC=y
+CONFIG_CRYPTO_ECDH=y
+# CONFIG_CRYPTO_ECDSA is not set
+# CONFIG_CRYPTO_ECRDSA is not set
+# CONFIG_CRYPTO_SM2 is not set
+# CONFIG_CRYPTO_CURVE25519 is not set
+CONFIG_CRYPTO_CURVE25519_X86=y
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_AEGIS128 is not set
+# CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set
+CONFIG_CRYPTO_SEQIV=y
+# CONFIG_CRYPTO_ECHAINIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CFB is not set
+CONFIG_CRYPTO_CTR=y
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_PCBC is not set
+CONFIG_CRYPTO_XTS=y
+# CONFIG_CRYPTO_KEYWRAP is not set
+# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set
+# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set
+# CONFIG_CRYPTO_ADIANTUM is not set
+CONFIG_CRYPTO_ESSIV=y
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC32C_INTEL=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32_PCLMUL=y
+# CONFIG_CRYPTO_XXHASH is not set
+# CONFIG_CRYPTO_BLAKE2B is not set
+# CONFIG_CRYPTO_BLAKE2S is not set
+CONFIG_CRYPTO_BLAKE2S_X86=y
+# CONFIG_CRYPTO_CRCT10DIF is not set
+CONFIG_CRYPTO_GHASH=y
+# CONFIG_CRYPTO_POLY1305 is not set
+CONFIG_CRYPTO_POLY1305_X86_64=y
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD160 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_SSSE3=y
+CONFIG_CRYPTO_SHA256_SSSE3=y
+CONFIG_CRYPTO_SHA512_SSSE3=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+# CONFIG_CRYPTO_SHA3 is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_STREEBOG is not set
+CONFIG_CRYPTO_WP512=y
+# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_AES_TI is not set
+CONFIG_CRYPTO_AES_NI_INTEL=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+CONFIG_CRYPTO_BLOWFISH_COMMON=y
+CONFIG_CRYPTO_BLOWFISH_X86_64=y
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set
+# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set
+# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DES3_EDE_X86_64=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_CHACHA20 is not set
+CONFIG_CRYPTO_CHACHA20_X86_64=y
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set
+# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set
+# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64 is not set
+# CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+CONFIG_CRYPTO_TWOFISH_X86_64=y
+CONFIG_CRYPTO_TWOFISH_X86_64_3WAY=y
+CONFIG_CRYPTO_TWOFISH_AVX_X86_64=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_842 is not set
+# CONFIG_CRYPTO_LZ4 is not set
+# CONFIG_CRYPTO_LZ4HC is not set
+# CONFIG_CRYPTO_ZSTD is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+# CONFIG_CRYPTO_DRBG_HASH is not set
+# CONFIG_CRYPTO_DRBG_CTR is not set
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_USER_API=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_CRYPTO_USER_API_RNG=y
+# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set
+# CONFIG_CRYPTO_USER_API_AEAD is not set
+CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y
+CONFIG_CRYPTO_HASH_INFO=y
+
+#
+# Crypto library routines
+#
+CONFIG_CRYPTO_LIB_AES=y
+CONFIG_CRYPTO_LIB_ARC4=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_BLAKE2S=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_LIB_CHACHA=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=y
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
+CONFIG_CRYPTO_LIB_CURVE25519=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
+CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305=y
+CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_PADLOCK is not set
+# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
+# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
+CONFIG_CRYPTO_DEV_CCP=y
+# CONFIG_CRYPTO_DEV_CCP_DD is not set
+# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set
+# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set
+# CONFIG_CRYPTO_DEV_QAT_C62X is not set
+# CONFIG_CRYPTO_DEV_QAT_4XXX is not set
+# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set
+# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set
+# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set
+# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set
+# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
+# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_X509_CERTIFICATE_PARSER=y
+# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
+CONFIG_PKCS7_MESSAGE_PARSER=y
+# CONFIG_PKCS7_TEST_KEY is not set
+# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
+
+#
+# Certificates for signature checking
+#
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSTEM_TRUSTED_KEYS=""
+# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
+# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
+# end of Certificates for signature checking
+
+#
+# Library routines
+#
+# CONFIG_PACKING is not set
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_NET_UTILS=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+# CONFIG_CORDIC is not set
+# CONFIG_PRIME_NUMBERS is not set
+CONFIG_RATIONAL=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
+CONFIG_ARCH_USE_SYM_ANNOTATIONS=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+# CONFIG_CRC64 is not set
+# CONFIG_CRC4 is not set
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+# CONFIG_CRC8 is not set
+CONFIG_XXHASH=y
+CONFIG_RANDOM32_SELFTEST=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_INTERVAL_TREE=y
+CONFIG_XARRAY_MULTI=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAS_DMA=y
+CONFIG_DMA_OPS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_SWIOTLB=y
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_DMA_MAP_BENCHMARK is not set
+CONFIG_SGL_ALLOC=y
+CONFIG_IOMMU_HELPER=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_GLOB=y
+# CONFIG_GLOB_SELFTEST is not set
+CONFIG_NLATTR=y
+CONFIG_CLZ_TAB=y
+# CONFIG_IRQ_POLL is not set
+CONFIG_MPILIB=y
+CONFIG_OID_REGISTRY=y
+CONFIG_HAVE_GENERIC_VDSO=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_VDSO_TIME_NS=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+# CONFIG_FONT_8x16 is not set
+CONFIG_FONT_6x11=y
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+CONFIG_FONT_6x10=y
+CONFIG_FONT_10x18=y
+CONFIG_FONT_SUN8x16=y
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_TER16x32 is not set
+# CONFIG_FONT_6x8 is not set
+CONFIG_SG_POOL=y
+CONFIG_ARCH_HAS_PMEM_API=y
+CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y
+CONFIG_ARCH_HAS_COPY_MC=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_SBITMAP=y
+# end of Library routines
+
+#
+# Kernel hacking
+#
+
+#
+# printk and dmesg options
+#
+CONFIG_PRINTK_TIME=y
+# CONFIG_PRINTK_CALLER is not set
+# CONFIG_STACKTRACE_BUILD_ID is not set
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7
+CONFIG_CONSOLE_LOGLEVEL_QUIET=4
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=5
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DYNAMIC_DEBUG_CORE is not set
+CONFIG_SYMBOLIC_ERRNAME=y
+CONFIG_DEBUG_BUGVERBOSE=y
+# end of printk and dmesg options
+
+#
+# Compile-time checks and compiler options
+#
+# CONFIG_DEBUG_INFO is not set
+CONFIG_FRAME_WARN=2048
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+# CONFIG_HEADERS_INSTALL is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
+# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set
+CONFIG_STACK_VALIDATION=y
+# CONFIG_VMLINUX_MAP is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# end of Compile-time checks and compiler options
+
+#
+# Generic Kernel Debugging Instruments
+#
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_DEBUG_FS_ALLOW_ALL is not set
+# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
+CONFIG_DEBUG_FS_ALLOW_NONE=y
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y
+# CONFIG_UBSAN is not set
+CONFIG_HAVE_ARCH_KCSAN=y
+CONFIG_HAVE_KCSAN_COMPILER=y
+# CONFIG_KCSAN is not set
+# end of Generic Kernel Debugging Instruments
+
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_MISC is not set
+
+#
+# Memory Debugging
+#
+# CONFIG_PAGE_EXTENSION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_PAGE_OWNER is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_DEBUG_RODATA_TEST=y
+CONFIG_ARCH_HAS_DEBUG_WX=y
+# CONFIG_DEBUG_WX is not set
+CONFIG_GENERIC_PTDUMP=y
+# CONFIG_PTDUMP_DEBUGFS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_SCHED_STACK_END_CHECK is not set
+CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_VM_PGTABLE is not set
+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
+# CONFIG_DEBUG_VIRTUAL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y
+# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set
+CONFIG_HAVE_ARCH_KASAN=y
+CONFIG_HAVE_ARCH_KASAN_VMALLOC=y
+CONFIG_CC_HAS_KASAN_GENERIC=y
+CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y
+# CONFIG_KASAN is not set
+CONFIG_HAVE_ARCH_KFENCE=y
+# CONFIG_KFENCE is not set
+# end of Memory Debugging
+
+# CONFIG_DEBUG_SHIRQ is not set
+
+#
+# Debug Oops, Lockups and Hangs
+#
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=10
+# CONFIG_SOFTLOCKUP_DETECTOR is not set
+CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_WQ_WATCHDOG is not set
+# CONFIG_TEST_LOCKUP is not set
+# end of Debug Oops, Lockups and Hangs
+
+#
+# Scheduler Debugging
+#
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHED_INFO=y
+# CONFIG_SCHEDSTATS is not set
+# end of Scheduler Debugging
+
+# CONFIG_DEBUG_TIMEKEEPING is not set
+
+#
+# Lock Debugging (spinlocks, mutexes, etc...)
+#
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set
+# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_LOCK_TORTURE_TEST is not set
+# CONFIG_WW_MUTEX_SELFTEST is not set
+# CONFIG_SCF_TORTURE_TEST is not set
+# CONFIG_CSD_LOCK_WAIT_DEBUG is not set
+# end of Lock Debugging (spinlocks, mutexes, etc...)
+
+# CONFIG_DEBUG_IRQFLAGS is not set
+# CONFIG_STACKTRACE is not set
+# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set
+# CONFIG_DEBUG_KOBJECT is not set
+
+#
+# Debug kernel data structures
+#
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_PLIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+# end of Debug kernel data structures
+
+# CONFIG_DEBUG_CREDENTIALS is not set
+
+#
+# RCU Debugging
+#
+# CONFIG_RCU_SCALE_TEST is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_REF_SCALE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+# CONFIG_RCU_TRACE is not set
+# CONFIG_RCU_EQS_DEBUG is not set
+# end of RCU Debugging
+
+# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set
+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_USER_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_FENTRY=y
+CONFIG_HAVE_OBJTOOL_MCOUNT=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
+# CONFIG_SAMPLES is not set
+CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y
+# CONFIG_STRICT_DEVMEM is not set
+
+#
+# x86 Debugging
+#
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_X86_VERBOSE_BOOTUP=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_EARLY_PRINTK_DBGP is not set
+# CONFIG_EARLY_PRINTK_USB_XDBC is not set
+# CONFIG_DEBUG_TLBFLUSH is not set
+CONFIG_IOMMU_DEBUG=y
+CONFIG_HAVE_MMIOTRACE_SUPPORT=y
+# CONFIG_X86_DECODER_SELFTEST is not set
+CONFIG_IO_DELAY_0X80=y
+# CONFIG_IO_DELAY_0XED is not set
+# CONFIG_IO_DELAY_UDELAY is not set
+# CONFIG_IO_DELAY_NONE is not set
+CONFIG_DEBUG_BOOT_PARAMS=y
+# CONFIG_CPA_DEBUG is not set
+# CONFIG_DEBUG_ENTRY is not set
+# CONFIG_DEBUG_NMI_SELFTEST is not set
+# CONFIG_X86_DEBUG_FPU is not set
+# CONFIG_PUNIT_ATOM_DEBUG is not set
+CONFIG_UNWINDER_ORC=y
+# CONFIG_UNWINDER_FRAME_POINTER is not set
+# CONFIG_UNWINDER_GUESS is not set
+# end of x86 Debugging
+
+#
+# Kernel Testing and Coverage
+#
+# CONFIG_KUNIT is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_CC_HAS_SANCOV_TRACE_PC=y
+# CONFIG_KCOV is not set
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_ARCH_USE_MEMTEST=y
+# CONFIG_MEMTEST is not set
+# end of Kernel Testing and Coverage
+# end of Kernel hacking