.ci/shellcheck.sh

@@ -23,6 +23,7 @@ sh_files="
 	./main/postmarketos-initramfs/init.sh
 	./main/postmarketos-initramfs/init_functions.sh
 	./main/postmarketos-mkinitfs-hook-debug-shell/20-debug-shell.sh
+	./main/postmarketos-mkinitfs-hook-debug-shell/setup_usb_storage.sh
 	./main/postmarketos-mkinitfs-hook-netboot/netboot.sh
 	./main/postmarketos-update-kernel/update-kernel.sh
 	./main/ttyescape/*.post-install

.ci/testcases/add_pmbootstrap_to_import_path/__init__.py

@@ -7,7 +7,7 @@ import sys
 import os
 import importlib
 import importlib.util
-from distutils.sysconfig import get_python_lib
+from site import getsitepackages
 
 
 def path_pmbootstrap():
@@ -24,13 +24,14 @@ def path_pmbootstrap():
         sys.exit(1)
 
     # Resolve the symlink and verify the folder
-    dir = os.path.dirname(os.path.realpath(bin))
-    if os.path.exists(dir + "/pmb/__init__.py"):
-        return dir
-
-    dir = get_python_lib()
-    if os.path.exists(dir + "/pmb/__init__.py"):
-        return dir
+    directory = os.path.dirname(os.path.realpath(bin))
+    if os.path.exists(directory + "/pmb/__init__.py"):
+        return directory
+
+    directories = getsitepackages()
+    for directory in directories:
+        if os.path.exists(directory + "/pmb/__init__.py"):
+            return directory
 
     # Symlink not set up properly
     print("ERROR: 'pmbootstrap' is not a symlink to pmbootstrap.py")

.gitlab/issue_templates/Default.md

@@ -21,8 +21,8 @@
 	Replace space inside `[ ]` with `x` to fill the checkbox
 -->
 * [ ] edge (`master` branch)
+* [ ] `v23.12`
 * [ ] `v23.06`
-* [ ] `v22.12` (Supported until 2023-07-06)
 
 * [ ] I confirm that the issue still is present after running `sudo apk upgrade -a`
 

channels.cfg

@@ -8,6 +8,12 @@ branch_pmaports=master
 branch_aports=master
 mirrordir_alpine=edge
 
+[v23.12]
+description=Upcoming stable release (DO NOT USE)
+branch_pmaports=v23.12
+branch_aports=3.19-stable
+mirrordir_alpine=v3.19
+
 [v23.06]
 description=Latest release / Recommended for best stability
 branch_pmaports=v23.06

cross/busybox-static-aarch64/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=busybox-static-aarch64
 pkgver=1.36.1
-pkgrel=8
+pkgrel=16
 
 _arch="aarch64"
 _mirror="http://dl-4.alpinelinux.org/alpine/"
@@ -32,5 +32,5 @@ package() {
 }
 
 sha512sums="
-89b28ab6e676d9c789375a85840c1f1062670992e4e44199c01d2356c439ab4d07c24ea5251d96388e150eb1343d0043a97316128b9603ad3ecb40dfa80e9072  busybox-static-1.36.1-r8-aarch64-edge.apk
+6287ccf7af6347f7b6fb5e49395a9a8bdfef584b4a2611d17d6132076902b057d787c098f563ab3640f770fca20864aff2a4762248ca405e58e032bad276fca5  busybox-static-1.36.1-r16-aarch64-edge.apk
 "

cross/busybox-static-armhf/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=busybox-static-armhf
 pkgver=1.36.1
-pkgrel=8
+pkgrel=16
 
 _arch="armhf"
 _mirror="http://dl-4.alpinelinux.org/alpine/"
@@ -32,5 +32,5 @@ package() {
 }
 
 sha512sums="
-b9909d463d65476b6ef5766ccf0b5c432f5d6a0209aaef9cb1b838633e8128fd1ddecc821cc63743f9db1f2136b8884ed19986430549660bb89008dd98f986f6  busybox-static-1.36.1-r8-armhf-edge.apk
+d216e65b0d08783eb1f6c8bb6eda441037a77530ac1069ff28b1a66846d219eed425b4390c56a3e2a7b9e080873533c3392782bb06b9e190ec004a3ae3ab7857  busybox-static-1.36.1-r16-armhf-edge.apk
 "

cross/busybox-static-armv7/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=busybox-static-armv7
 pkgver=1.36.1
-pkgrel=8
+pkgrel=16
 
 _arch="armv7"
 _mirror="http://dl-4.alpinelinux.org/alpine/"
@@ -32,5 +32,5 @@ package() {
 }
 
 sha512sums="
-40094ff8b8d45fce75ff872f94cc24da5129c1b2a28da2a7336dd6995ca973cb595d0a46f6346d55c862fb72c6c517fe00f6d6d7b20c604f644d1f8c4fc1afb0  busybox-static-1.36.1-r8-armv7-edge.apk
+f9280cf852098400859968249f51bfe16db47655c15f0e384891ba9574ad42d2cef753760e895dfa9d625f2e051e6982a16e459d792e573bde161b1bd563c020  busybox-static-1.36.1-r16-armv7-edge.apk
 "

cross/gcc-aarch64/0035-Fix-ICE-observed-in-PR110280.patch

-From ef740fff300fd9eb8285fb5611f6205705ee54ec Mon Sep 17 00:00:00 2001
-From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
-Date: Fri, 23 Jun 2023 15:27:17 +0530
-Subject: [PATCH 35/35] Fix ICE observed in PR110280.
-
-gcc/ChangeLog:
-	PR tree-optimization/110280
-	* match.pd (vec_perm_expr(v, v, mask) -> v): Explicitly build vector
-	using build_vector_from_val with the element of input operand, and
-	mask's type if operand and mask's types don't match.
-
-gcc/testsuite/ChangeLog:
-	PR tree-optimization/110280
-	* gcc.target/aarch64/sve/pr110280.c: New test.
----
- gcc/match.pd                                    |  9 ++++++++-
- gcc/testsuite/gcc.target/aarch64/sve/pr110280.c | 12 ++++++++++++
- 2 files changed, 20 insertions(+), 1 deletion(-)
- create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
-
-diff --git a/gcc/match.pd b/gcc/match.pd
-index 91182448250..c3bb4fbc0a7 100644
---- a/gcc/match.pd
-+++ b/gcc/match.pd
-@@ -8292,7 +8292,14 @@ and,
- 
- (simplify
-  (vec_perm vec_same_elem_p@0 @0 @1)
-- @0)
-+ (if (types_match (type, TREE_TYPE (@0)))
-+  @0
-+  (with
-+   {
-+     tree elem = uniform_vector_p (@0);
-+   }
-+   (if (elem)
-+    { build_vector_from_val (type, elem); }))))
- 
- /* Push VEC_PERM earlier if that may help FMA perception (PR101895).  */
- (simplify
-diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
-new file mode 100644
-index 00000000000..d3279f38362
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
-@@ -0,0 +1,12 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O3 -fdump-tree-optimized" } */
-+
-+#include "arm_sve.h"
-+
-+svuint32_t l()
-+{
-+  _Alignas(16) const unsigned int lanes[4] = {0, 0, 0, 0};
-+  return svld1rq_u32(svptrue_b8(), lanes);
-+}
-+
-+/* { dg-final { scan-tree-dump-not "VEC_PERM_EXPR" "optimized" } } */
--- 
-2.41.0
-

cross/gcc-aarch64/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

+https://gcc.gnu.org/PR110792
+https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
+https://github.com/randombit/botan/issues/3637
+
+From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
+From: Roger Sayle <roger@nextmovesoftware.com>
+Date: Thu, 3 Aug 2023 07:12:04 +0100
+Subject: [PATCH] PR target/110792: Early clobber issues with
+ rot32di2_doubleword on i386.
+
+This patch is a conservative fix for PR target/110792, a wrong-code
+regression affecting doubleword rotations by BITS_PER_WORD, which
+effectively swaps the highpart and lowpart words, when the source to be
+rotated resides in memory. The issue is that if the register used to
+hold the lowpart of the destination is mentioned in the address of
+the memory operand, the current define_insn_and_split unintentionally
+clobbers it before reading the highpart.
+
+Hence, for the testcase, the incorrectly generated code looks like:
+
+        salq    $4, %rdi		// calculate address
+        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
+        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
+
+Traditionally, the textbook way to fix this would be to add an
+explicit early clobber to the instruction's constraints.
+
+ (define_insn_and_split "<insn>32di2_doubleword"
+- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
++ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
+        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
+                       (const_int 32)))]
+
+but unfortunately this currently generates significantly worse code,
+due to a strange choice of reloads (effectively memcpy), which ends up
+looking like:
+
+        salq    $4, %rdi		// calculate address
+        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
+        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
+        movq    -8(%rsp), %rdi		// load highpart
+        movq    -16(%rsp), %rbp		// load lowpart
+
+Note that reload's "&" doesn't distinguish between the memory being
+early clobbered, vs the registers used in an addressing mode being
+early clobbered.
+
+The fix proposed in this patch is to remove the third alternative, that
+allowed offsetable memory as an operand, forcing reload to place the
+operand into a register before the rotation.  This results in:
+
+        salq    $4, %rdi
+        movq    WHIRL_S(%rdi), %rax
+        movq    WHIRL_S+8(%rdi), %rdi
+        movq    %rax, %rbp
+
+I believe there's a more advanced solution, by swapping the order of
+the loads (if first destination register is mentioned in the address),
+or inserting a lea insn (if both destination registers are mentioned
+in the address), but this fix is a minimal "safe" solution, that
+should hopefully be suitable for backporting.
+
+2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
+
+gcc/ChangeLog
+	PR target/110792
+	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
+	place operand in a register before gen_<insn>64ti2_doubleword.
+	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
+	operand in a register before gen_<insn>32di2_doubleword.
+	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
+	(<any_rotate>64ti2_doubleword): Likewise.
+
+gcc/testsuite/ChangeLog
+	PR target/110792
+	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
+	* gcc.target/i386/pr110792.c: New 64-bit C test case.
+
+(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
+---
+ gcc/config/i386/i386.md                  | 18 ++++++++++++------
+ gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
+ gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
+ 3 files changed, 46 insertions(+), 6 deletions(-)
+ create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
+ create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
+
+diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
+index f3a3305..a71e837 100644
+--- a/gcc/config/i386/i386.md
++++ b/gcc/config/i386/i386.md
+@@ -14359,7 +14359,10 @@
+     emit_insn (gen_ix86_<insn>ti3_doubleword
+ 		(operands[0], operands[1], operands[2]));
+   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
+-    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
++    {
++      operands[1] = force_reg (TImode, operands[1]);
++      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
++    }
+   else
+     {
+       rtx amount = force_reg (QImode, operands[2]);
+@@ -14394,7 +14397,10 @@
+     emit_insn (gen_ix86_<insn>di3_doubleword
+ 		(operands[0], operands[1], operands[2]));
+   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
+-    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
++    {
++      operands[1] = force_reg (DImode, operands[1]);
++      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
++    }
+   else
+     FAIL;
+ 
+@@ -14562,8 +14568,8 @@
+ })
+ 
+ (define_insn_and_split "<insn>32di2_doubleword"
+- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+-       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
++ [(set (match_operand:DI 0 "register_operand" "=r,r")
++       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
+                       (const_int 32)))]
+  "!TARGET_64BIT"
+  "#"
+@@ -14580,8 +14586,8 @@
+ })
+ 
+ (define_insn_and_split "<insn>64ti2_doubleword"
+- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
+-       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
++ [(set (match_operand:TI 0 "register_operand" "=r,r")
++       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
+                       (const_int 64)))]
+  "TARGET_64BIT"
+  "#"
+diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
+new file mode 100644
+index 0000000..ce21a7a
+--- /dev/null
++++ b/gcc/testsuite/g++.target/i386/pr110792.C
+@@ -0,0 +1,16 @@
++/* { dg-do compile { target ia32 } } */
++/* { dg-options "-O2" } */
++
++template <int ROT, typename T>
++inline T rotr(T input)
++{
++   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
++}
++
++unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
++unsigned long long whirl(unsigned char x0)
++{
++   const unsigned long long s4 = WHIRL_S[x0&0xFF];
++   return rotr<32>(s4);
++}
++/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
+diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
+new file mode 100644
+index 0000000..b65125c
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/i386/pr110792.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile { target int128 } } */
++/* { dg-options "-O2" } */
++
++static inline unsigned __int128 rotr(unsigned __int128 input)
++{
++   return ((input >> 64) | (input << (64)));
++}
++
++unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
++unsigned __int128 whirl(unsigned char x0)
++{
++   register int t __asm("rdi") = x0&0xFF;
++   const unsigned __int128 s4 = WHIRL_S[t];
++   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
++   asm("":::"memory");
++   return tt;
++}
++/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
+-- 
+2.41.0
+

cross/gcc-aarch64/APKBUILD

@@ -24,8 +24,8 @@ CBUILDROOT="/"
 _cross_configure="--disable-bootstrap --with-sysroot=/usr/$CTARGET"
 
 pkgname=gcc-aarch64
-pkgver=13.1.1_git20230722
-# i.e. 13.1.1, must match gcc/BASE-VER
+pkgver=13.2.1_git20231014
+# i.e. 13.2.1, must match gcc/BASE-VER
 _pkgbase="${pkgver%%_git*}"
 # date component from snapshots
 _pkgsnap="${pkgver##*_git}"
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-aarch64
-pkgrel=2
+pkgrel=0
 pkgdesc="Stage2 cross-compiler for aarch64"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -268,9 +268,13 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
-	0035-Fix-ICE-observed-in-PR110280.patch
+	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
 	"
 
+# secfixes:
+#   13.2.1_git20231014-r0:
+#     - CVE-2023-4039
+
 # we build out-of-tree
 _gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
 _gcclibdir="/usr/lib/gcc/$CTARGET/${_pkgbase:-$pkgver}"
@@ -783,7 +787,7 @@ gdb() {
 }
 
 sha512sums="
-284719308cad4546ebd85934fb9f12112e8f1a4c3e5beea0760da1f73509907c194e7c133e6e755b6148bd1c51a72c071ac0d16b05641d901af7105461686655  gcc-13-20230722.tar.xz
+406673a62deba759fc0532a801b3f57cabf894ea328587b23e62a707ba5767b0e3ae9b3f86bf3c6fcf13e8a3c30bc470e6598b625c8231efb629034211c162c2  gcc-13-20231014.tar.xz
 1ecffba1b07d60e1b4422302b032bbea918b674c8e12b30aa6965b544d700ce86b61e9f7b8d402c6caf59257f491a394dd0912f0948565d6eae9335ee54f3b35  0001-posix_memalign.patch
 163f282455b6a4df33f011bcd8b0440566ba0ffaeeab30d8ac52d39948980a56881ca0eff60687129d59556389a58b9d64e7768750bd70b1fe0fedbc9fc30dc2  0002-gcc-poison-system-directories.patch
 3f24bb6a50d3c45b71ea05590e32fe3e69b91377ab185352891d5035c76ed193117c6d0b314a4c364bcf136b9a9dd5c926d6c7c30ab436976c121ebfea8d3ddd  0003-specs-turn-on-Wl-z-now-by-default.patch
@@ -818,5 +822,5 @@ d47b559075f40d526235f47b91da1d0cf6bfe6c5b7311bbfe08af9dd6e8f27e6c7cd82e3b2d529aa
 b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95e21c9ffbf2412193f8b9fc89a4c36fa5a6a041661ac7399d  0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
-048d767f4477c92ee6835850d13063ede21c0be751d0945c94445d04054e134cdc617eeb0b1ac8c892a604d8644580fcfebeccaf537d6b7380558ac6378e445a  0035-Fix-ICE-observed-in-PR110280.patch
+cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
 "

cross/gcc-armhf/0035-Fix-ICE-observed-in-PR110280.patch

-From ef740fff300fd9eb8285fb5611f6205705ee54ec Mon Sep 17 00:00:00 2001
-From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
-Date: Fri, 23 Jun 2023 15:27:17 +0530
-Subject: [PATCH 35/35] Fix ICE observed in PR110280.
-
-gcc/ChangeLog:
-	PR tree-optimization/110280
-	* match.pd (vec_perm_expr(v, v, mask) -> v): Explicitly build vector
-	using build_vector_from_val with the element of input operand, and
-	mask's type if operand and mask's types don't match.
-
-gcc/testsuite/ChangeLog:
-	PR tree-optimization/110280
-	* gcc.target/aarch64/sve/pr110280.c: New test.
----
- gcc/match.pd                                    |  9 ++++++++-
- gcc/testsuite/gcc.target/aarch64/sve/pr110280.c | 12 ++++++++++++
- 2 files changed, 20 insertions(+), 1 deletion(-)
- create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
-
-diff --git a/gcc/match.pd b/gcc/match.pd
-index 91182448250..c3bb4fbc0a7 100644
---- a/gcc/match.pd
-+++ b/gcc/match.pd
-@@ -8292,7 +8292,14 @@ and,
- 
- (simplify
-  (vec_perm vec_same_elem_p@0 @0 @1)
-- @0)
-+ (if (types_match (type, TREE_TYPE (@0)))
-+  @0
-+  (with
-+   {
-+     tree elem = uniform_vector_p (@0);
-+   }
-+   (if (elem)
-+    { build_vector_from_val (type, elem); }))))
- 
- /* Push VEC_PERM earlier if that may help FMA perception (PR101895).  */
- (simplify
-diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
-new file mode 100644
-index 00000000000..d3279f38362
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
-@@ -0,0 +1,12 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O3 -fdump-tree-optimized" } */
-+
-+#include "arm_sve.h"
-+
-+svuint32_t l()
-+{
-+  _Alignas(16) const unsigned int lanes[4] = {0, 0, 0, 0};
-+  return svld1rq_u32(svptrue_b8(), lanes);
-+}
-+
-+/* { dg-final { scan-tree-dump-not "VEC_PERM_EXPR" "optimized" } } */
--- 
-2.41.0
-

cross/gcc-armhf/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

+https://gcc.gnu.org/PR110792
+https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
+https://github.com/randombit/botan/issues/3637
+
+From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
+From: Roger Sayle <roger@nextmovesoftware.com>
+Date: Thu, 3 Aug 2023 07:12:04 +0100
+Subject: [PATCH] PR target/110792: Early clobber issues with
+ rot32di2_doubleword on i386.
+
+This patch is a conservative fix for PR target/110792, a wrong-code
+regression affecting doubleword rotations by BITS_PER_WORD, which
+effectively swaps the highpart and lowpart words, when the source to be
+rotated resides in memory. The issue is that if the register used to
+hold the lowpart of the destination is mentioned in the address of
+the memory operand, the current define_insn_and_split unintentionally
+clobbers it before reading the highpart.
+
+Hence, for the testcase, the incorrectly generated code looks like:
+
+        salq    $4, %rdi		// calculate address
+        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
+        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
+
+Traditionally, the textbook way to fix this would be to add an
+explicit early clobber to the instruction's constraints.
+
+ (define_insn_and_split "<insn>32di2_doubleword"
+- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
++ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
+        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
+                       (const_int 32)))]
+
+but unfortunately this currently generates significantly worse code,
+due to a strange choice of reloads (effectively memcpy), which ends up
+looking like:
+
+        salq    $4, %rdi		// calculate address
+        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
+        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
+        movq    -8(%rsp), %rdi		// load highpart
+        movq    -16(%rsp), %rbp		// load lowpart
+
+Note that reload's "&" doesn't distinguish between the memory being
+early clobbered, vs the registers used in an addressing mode being
+early clobbered.
+
+The fix proposed in this patch is to remove the third alternative, that
+allowed offsetable memory as an operand, forcing reload to place the
+operand into a register before the rotation.  This results in:
+
+        salq    $4, %rdi
+        movq    WHIRL_S(%rdi), %rax
+        movq    WHIRL_S+8(%rdi), %rdi
+        movq    %rax, %rbp
+
+I believe there's a more advanced solution, by swapping the order of
+the loads (if first destination register is mentioned in the address),
+or inserting a lea insn (if both destination registers are mentioned
+in the address), but this fix is a minimal "safe" solution, that
+should hopefully be suitable for backporting.
+
+2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
+
+gcc/ChangeLog
+	PR target/110792
+	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
+	place operand in a register before gen_<insn>64ti2_doubleword.
+	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
+	operand in a register before gen_<insn>32di2_doubleword.
+	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
+	(<any_rotate>64ti2_doubleword): Likewise.
+
+gcc/testsuite/ChangeLog
+	PR target/110792
+	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
+	* gcc.target/i386/pr110792.c: New 64-bit C test case.
+
+(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
+---
+ gcc/config/i386/i386.md                  | 18 ++++++++++++------
+ gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
+ gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
+ 3 files changed, 46 insertions(+), 6 deletions(-)
+ create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
+ create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
+
+diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
+index f3a3305..a71e837 100644
+--- a/gcc/config/i386/i386.md
++++ b/gcc/config/i386/i386.md
+@@ -14359,7 +14359,10 @@
+     emit_insn (gen_ix86_<insn>ti3_doubleword
+ 		(operands[0], operands[1], operands[2]));
+   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
+-    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
++    {
++      operands[1] = force_reg (TImode, operands[1]);
++      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
++    }
+   else
+     {
+       rtx amount = force_reg (QImode, operands[2]);
+@@ -14394,7 +14397,10 @@
+     emit_insn (gen_ix86_<insn>di3_doubleword
+ 		(operands[0], operands[1], operands[2]));
+   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
+-    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
++    {
++      operands[1] = force_reg (DImode, operands[1]);
++      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
++    }
+   else
+     FAIL;
+ 
+@@ -14562,8 +14568,8 @@
+ })
+ 
+ (define_insn_and_split "<insn>32di2_doubleword"
+- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+-       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
++ [(set (match_operand:DI 0 "register_operand" "=r,r")
++       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
+                       (const_int 32)))]
+  "!TARGET_64BIT"
+  "#"
+@@ -14580,8 +14586,8 @@
+ })
+ 
+ (define_insn_and_split "<insn>64ti2_doubleword"
+- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
+-       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
++ [(set (match_operand:TI 0 "register_operand" "=r,r")
++       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
+                       (const_int 64)))]
+  "TARGET_64BIT"
+  "#"
+diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
+new file mode 100644
+index 0000000..ce21a7a
+--- /dev/null
++++ b/gcc/testsuite/g++.target/i386/pr110792.C
+@@ -0,0 +1,16 @@
++/* { dg-do compile { target ia32 } } */
++/* { dg-options "-O2" } */
++
++template <int ROT, typename T>
++inline T rotr(T input)
++{
++   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
++}
++
++unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
++unsigned long long whirl(unsigned char x0)
++{
++   const unsigned long long s4 = WHIRL_S[x0&0xFF];
++   return rotr<32>(s4);
++}
++/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
+diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
+new file mode 100644
+index 0000000..b65125c
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/i386/pr110792.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile { target int128 } } */
++/* { dg-options "-O2" } */
++
++static inline unsigned __int128 rotr(unsigned __int128 input)
++{
++   return ((input >> 64) | (input << (64)));
++}
++
++unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
++unsigned __int128 whirl(unsigned char x0)
++{
++   register int t __asm("rdi") = x0&0xFF;
++   const unsigned __int128 s4 = WHIRL_S[t];
++   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
++   asm("":::"memory");
++   return tt;
++}
++/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
+-- 
+2.41.0
+

cross/gcc-armhf/APKBUILD

@@ -24,8 +24,8 @@ CBUILDROOT="/"
 _cross_configure="--disable-bootstrap --with-sysroot=/usr/$CTARGET"
 
 pkgname=gcc-armhf
-pkgver=13.1.1_git20230722
-# i.e. 13.1.1, must match gcc/BASE-VER
+pkgver=13.2.1_git20231014
+# i.e. 13.2.1, must match gcc/BASE-VER
 _pkgbase="${pkgver%%_git*}"
 # date component from snapshots
 _pkgsnap="${pkgver##*_git}"
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-armhf
-pkgrel=2
+pkgrel=0
 pkgdesc="Stage2 cross-compiler for armhf"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -268,9 +268,13 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
-	0035-Fix-ICE-observed-in-PR110280.patch
+	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
 	"
 
+# secfixes:
+#   13.2.1_git20231014-r0:
+#     - CVE-2023-4039
+
 # we build out-of-tree
 _gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
 _gcclibdir="/usr/lib/gcc/$CTARGET/${_pkgbase:-$pkgver}"
@@ -783,7 +787,7 @@ gdb() {
 }
 
 sha512sums="
-284719308cad4546ebd85934fb9f12112e8f1a4c3e5beea0760da1f73509907c194e7c133e6e755b6148bd1c51a72c071ac0d16b05641d901af7105461686655  gcc-13-20230722.tar.xz
+406673a62deba759fc0532a801b3f57cabf894ea328587b23e62a707ba5767b0e3ae9b3f86bf3c6fcf13e8a3c30bc470e6598b625c8231efb629034211c162c2  gcc-13-20231014.tar.xz
 1ecffba1b07d60e1b4422302b032bbea918b674c8e12b30aa6965b544d700ce86b61e9f7b8d402c6caf59257f491a394dd0912f0948565d6eae9335ee54f3b35  0001-posix_memalign.patch
 163f282455b6a4df33f011bcd8b0440566ba0ffaeeab30d8ac52d39948980a56881ca0eff60687129d59556389a58b9d64e7768750bd70b1fe0fedbc9fc30dc2  0002-gcc-poison-system-directories.patch
 3f24bb6a50d3c45b71ea05590e32fe3e69b91377ab185352891d5035c76ed193117c6d0b314a4c364bcf136b9a9dd5c926d6c7c30ab436976c121ebfea8d3ddd  0003-specs-turn-on-Wl-z-now-by-default.patch
@@ -818,5 +822,5 @@ d47b559075f40d526235f47b91da1d0cf6bfe6c5b7311bbfe08af9dd6e8f27e6c7cd82e3b2d529aa
 b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95e21c9ffbf2412193f8b9fc89a4c36fa5a6a041661ac7399d  0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
-048d767f4477c92ee6835850d13063ede21c0be751d0945c94445d04054e134cdc617eeb0b1ac8c892a604d8644580fcfebeccaf537d6b7380558ac6378e445a  0035-Fix-ICE-observed-in-PR110280.patch
+cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
 "

cross/gcc-armv7/0035-Fix-ICE-observed-in-PR110280.patch

-From ef740fff300fd9eb8285fb5611f6205705ee54ec Mon Sep 17 00:00:00 2001
-From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
-Date: Fri, 23 Jun 2023 15:27:17 +0530
-Subject: [PATCH 35/35] Fix ICE observed in PR110280.
-
-gcc/ChangeLog:
-	PR tree-optimization/110280
-	* match.pd (vec_perm_expr(v, v, mask) -> v): Explicitly build vector
-	using build_vector_from_val with the element of input operand, and
-	mask's type if operand and mask's types don't match.
-
-gcc/testsuite/ChangeLog:
-	PR tree-optimization/110280
-	* gcc.target/aarch64/sve/pr110280.c: New test.
----
- gcc/match.pd                                    |  9 ++++++++-
- gcc/testsuite/gcc.target/aarch64/sve/pr110280.c | 12 ++++++++++++
- 2 files changed, 20 insertions(+), 1 deletion(-)
- create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
-
-diff --git a/gcc/match.pd b/gcc/match.pd
-index 91182448250..c3bb4fbc0a7 100644
---- a/gcc/match.pd
-+++ b/gcc/match.pd
-@@ -8292,7 +8292,14 @@ and,
- 
- (simplify
-  (vec_perm vec_same_elem_p@0 @0 @1)
-- @0)
-+ (if (types_match (type, TREE_TYPE (@0)))
-+  @0
-+  (with
-+   {
-+     tree elem = uniform_vector_p (@0);
-+   }
-+   (if (elem)
-+    { build_vector_from_val (type, elem); }))))
- 
- /* Push VEC_PERM earlier if that may help FMA perception (PR101895).  */
- (simplify
-diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
-new file mode 100644
-index 00000000000..d3279f38362
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
-@@ -0,0 +1,12 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O3 -fdump-tree-optimized" } */
-+
-+#include "arm_sve.h"
-+
-+svuint32_t l()
-+{
-+  _Alignas(16) const unsigned int lanes[4] = {0, 0, 0, 0};
-+  return svld1rq_u32(svptrue_b8(), lanes);
-+}
-+
-+/* { dg-final { scan-tree-dump-not "VEC_PERM_EXPR" "optimized" } } */
--- 
-2.41.0
-

cross/gcc-armv7/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

+https://gcc.gnu.org/PR110792
+https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
+https://github.com/randombit/botan/issues/3637
+
+From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
+From: Roger Sayle <roger@nextmovesoftware.com>
+Date: Thu, 3 Aug 2023 07:12:04 +0100
+Subject: [PATCH] PR target/110792: Early clobber issues with
+ rot32di2_doubleword on i386.
+
+This patch is a conservative fix for PR target/110792, a wrong-code
+regression affecting doubleword rotations by BITS_PER_WORD, which
+effectively swaps the highpart and lowpart words, when the source to be
+rotated resides in memory. The issue is that if the register used to
+hold the lowpart of the destination is mentioned in the address of
+the memory operand, the current define_insn_and_split unintentionally
+clobbers it before reading the highpart.
+
+Hence, for the testcase, the incorrectly generated code looks like:
+
+        salq    $4, %rdi		// calculate address
+        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
+        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
+
+Traditionally, the textbook way to fix this would be to add an
+explicit early clobber to the instruction's constraints.
+
+ (define_insn_and_split "<insn>32di2_doubleword"
+- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
++ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
+        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
+                       (const_int 32)))]
+
+but unfortunately this currently generates significantly worse code,
+due to a strange choice of reloads (effectively memcpy), which ends up
+looking like:
+
+        salq    $4, %rdi		// calculate address
+        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
+        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
+        movq    -8(%rsp), %rdi		// load highpart
+        movq    -16(%rsp), %rbp		// load lowpart
+
+Note that reload's "&" doesn't distinguish between the memory being
+early clobbered, vs the registers used in an addressing mode being
+early clobbered.
+
+The fix proposed in this patch is to remove the third alternative, that
+allowed offsetable memory as an operand, forcing reload to place the
+operand into a register before the rotation.  This results in:
+
+        salq    $4, %rdi
+        movq    WHIRL_S(%rdi), %rax
+        movq    WHIRL_S+8(%rdi), %rdi
+        movq    %rax, %rbp
+
+I believe there's a more advanced solution, by swapping the order of
+the loads (if first destination register is mentioned in the address),
+or inserting a lea insn (if both destination registers are mentioned
+in the address), but this fix is a minimal "safe" solution, that
+should hopefully be suitable for backporting.
+
+2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
+
+gcc/ChangeLog
+	PR target/110792
+	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
+	place operand in a register before gen_<insn>64ti2_doubleword.
+	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
+	operand in a register before gen_<insn>32di2_doubleword.
+	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
+	(<any_rotate>64ti2_doubleword): Likewise.
+
+gcc/testsuite/ChangeLog
+	PR target/110792
+	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
+	* gcc.target/i386/pr110792.c: New 64-bit C test case.
+
+(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
+---
+ gcc/config/i386/i386.md                  | 18 ++++++++++++------
+ gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
+ gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
+ 3 files changed, 46 insertions(+), 6 deletions(-)
+ create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
+ create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
+
+diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
+index f3a3305..a71e837 100644
+--- a/gcc/config/i386/i386.md
++++ b/gcc/config/i386/i386.md
+@@ -14359,7 +14359,10 @@
+     emit_insn (gen_ix86_<insn>ti3_doubleword
+ 		(operands[0], operands[1], operands[2]));
+   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
+-    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
++    {
++      operands[1] = force_reg (TImode, operands[1]);
++      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
++    }
+   else
+     {
+       rtx amount = force_reg (QImode, operands[2]);
+@@ -14394,7 +14397,10 @@
+     emit_insn (gen_ix86_<insn>di3_doubleword
+ 		(operands[0], operands[1], operands[2]));
+   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
+-    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
++    {
++      operands[1] = force_reg (DImode, operands[1]);
++      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
++    }
+   else
+     FAIL;
+ 
+@@ -14562,8 +14568,8 @@
+ })
+ 
+ (define_insn_and_split "<insn>32di2_doubleword"
+- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+-       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
++ [(set (match_operand:DI 0 "register_operand" "=r,r")
++       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
+                       (const_int 32)))]
+  "!TARGET_64BIT"
+  "#"
+@@ -14580,8 +14586,8 @@
+ })
+ 
+ (define_insn_and_split "<insn>64ti2_doubleword"
+- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
+-       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
++ [(set (match_operand:TI 0 "register_operand" "=r,r")
++       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
+                       (const_int 64)))]
+  "TARGET_64BIT"
+  "#"
+diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
+new file mode 100644
+index 0000000..ce21a7a
+--- /dev/null
++++ b/gcc/testsuite/g++.target/i386/pr110792.C
+@@ -0,0 +1,16 @@
++/* { dg-do compile { target ia32 } } */
++/* { dg-options "-O2" } */
++
++template <int ROT, typename T>
++inline T rotr(T input)
++{
++   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
++}
++
++unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
++unsigned long long whirl(unsigned char x0)
++{
++   const unsigned long long s4 = WHIRL_S[x0&0xFF];
++   return rotr<32>(s4);
++}
++/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
+diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
+new file mode 100644
+index 0000000..b65125c
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/i386/pr110792.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile { target int128 } } */
++/* { dg-options "-O2" } */
++
++static inline unsigned __int128 rotr(unsigned __int128 input)
++{
++   return ((input >> 64) | (input << (64)));
++}
++
++unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
++unsigned __int128 whirl(unsigned char x0)
++{
++   register int t __asm("rdi") = x0&0xFF;
++   const unsigned __int128 s4 = WHIRL_S[t];
++   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
++   asm("":::"memory");
++   return tt;
++}
++/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
+-- 
+2.41.0
+

cross/gcc-armv7/APKBUILD

@@ -24,8 +24,8 @@ CBUILDROOT="/"
 _cross_configure="--disable-bootstrap --with-sysroot=/usr/$CTARGET"
 
 pkgname=gcc-armv7
-pkgver=13.1.1_git20230722
-# i.e. 13.1.1, must match gcc/BASE-VER
+pkgver=13.2.1_git20231014
+# i.e. 13.2.1, must match gcc/BASE-VER
 _pkgbase="${pkgver%%_git*}"
 # date component from snapshots
 _pkgsnap="${pkgver##*_git}"
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-armv7
-pkgrel=2
+pkgrel=0
 pkgdesc="Stage2 cross-compiler for armv7"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -268,9 +268,13 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
-	0035-Fix-ICE-observed-in-PR110280.patch
+	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
 	"
 
+# secfixes:
+#   13.2.1_git20231014-r0:
+#     - CVE-2023-4039
+
 # we build out-of-tree
 _gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
 _gcclibdir="/usr/lib/gcc/$CTARGET/${_pkgbase:-$pkgver}"
@@ -783,7 +787,7 @@ gdb() {
 }
 
 sha512sums="
-284719308cad4546ebd85934fb9f12112e8f1a4c3e5beea0760da1f73509907c194e7c133e6e755b6148bd1c51a72c071ac0d16b05641d901af7105461686655  gcc-13-20230722.tar.xz
+406673a62deba759fc0532a801b3f57cabf894ea328587b23e62a707ba5767b0e3ae9b3f86bf3c6fcf13e8a3c30bc470e6598b625c8231efb629034211c162c2  gcc-13-20231014.tar.xz
 1ecffba1b07d60e1b4422302b032bbea918b674c8e12b30aa6965b544d700ce86b61e9f7b8d402c6caf59257f491a394dd0912f0948565d6eae9335ee54f3b35  0001-posix_memalign.patch
 163f282455b6a4df33f011bcd8b0440566ba0ffaeeab30d8ac52d39948980a56881ca0eff60687129d59556389a58b9d64e7768750bd70b1fe0fedbc9fc30dc2  0002-gcc-poison-system-directories.patch
 3f24bb6a50d3c45b71ea05590e32fe3e69b91377ab185352891d5035c76ed193117c6d0b314a4c364bcf136b9a9dd5c926d6c7c30ab436976c121ebfea8d3ddd  0003-specs-turn-on-Wl-z-now-by-default.patch
@@ -818,5 +822,5 @@ d47b559075f40d526235f47b91da1d0cf6bfe6c5b7311bbfe08af9dd6e8f27e6c7cd82e3b2d529aa
 b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95e21c9ffbf2412193f8b9fc89a4c36fa5a6a041661ac7399d  0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
-048d767f4477c92ee6835850d13063ede21c0be751d0945c94445d04054e134cdc617eeb0b1ac8c892a604d8644580fcfebeccaf537d6b7380558ac6378e445a  0035-Fix-ICE-observed-in-PR110280.patch
+cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
 "

cross/gcc-riscv64/0035-Fix-ICE-observed-in-PR110280.patch

-From ef740fff300fd9eb8285fb5611f6205705ee54ec Mon Sep 17 00:00:00 2001
-From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
-Date: Fri, 23 Jun 2023 15:27:17 +0530
-Subject: [PATCH 35/35] Fix ICE observed in PR110280.
-
-gcc/ChangeLog:
-	PR tree-optimization/110280
-	* match.pd (vec_perm_expr(v, v, mask) -> v): Explicitly build vector
-	using build_vector_from_val with the element of input operand, and
-	mask's type if operand and mask's types don't match.
-
-gcc/testsuite/ChangeLog:
-	PR tree-optimization/110280
-	* gcc.target/aarch64/sve/pr110280.c: New test.
----
- gcc/match.pd                                    |  9 ++++++++-
- gcc/testsuite/gcc.target/aarch64/sve/pr110280.c | 12 ++++++++++++
- 2 files changed, 20 insertions(+), 1 deletion(-)
- create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
-
-diff --git a/gcc/match.pd b/gcc/match.pd
-index 91182448250..c3bb4fbc0a7 100644
---- a/gcc/match.pd
-+++ b/gcc/match.pd
-@@ -8292,7 +8292,14 @@ and,
- 
- (simplify
-  (vec_perm vec_same_elem_p@0 @0 @1)
-- @0)
-+ (if (types_match (type, TREE_TYPE (@0)))
-+  @0
-+  (with
-+   {
-+     tree elem = uniform_vector_p (@0);
-+   }
-+   (if (elem)
-+    { build_vector_from_val (type, elem); }))))
- 
- /* Push VEC_PERM earlier if that may help FMA perception (PR101895).  */
- (simplify
-diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
-new file mode 100644
-index 00000000000..d3279f38362
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/aarch64/sve/pr110280.c
-@@ -0,0 +1,12 @@
-+/* { dg-do compile } */
-+/* { dg-options "-O3 -fdump-tree-optimized" } */
-+
-+#include "arm_sve.h"
-+
-+svuint32_t l()
-+{
-+  _Alignas(16) const unsigned int lanes[4] = {0, 0, 0, 0};
-+  return svld1rq_u32(svptrue_b8(), lanes);
-+}
-+
-+/* { dg-final { scan-tree-dump-not "VEC_PERM_EXPR" "optimized" } } */
--- 
-2.41.0
-

cross/gcc-riscv64/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

+https://gcc.gnu.org/PR110792
+https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
+https://github.com/randombit/botan/issues/3637
+
+From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
+From: Roger Sayle <roger@nextmovesoftware.com>
+Date: Thu, 3 Aug 2023 07:12:04 +0100
+Subject: [PATCH] PR target/110792: Early clobber issues with
+ rot32di2_doubleword on i386.
+
+This patch is a conservative fix for PR target/110792, a wrong-code
+regression affecting doubleword rotations by BITS_PER_WORD, which
+effectively swaps the highpart and lowpart words, when the source to be
+rotated resides in memory. The issue is that if the register used to
+hold the lowpart of the destination is mentioned in the address of
+the memory operand, the current define_insn_and_split unintentionally
+clobbers it before reading the highpart.
+
+Hence, for the testcase, the incorrectly generated code looks like:
+
+        salq    $4, %rdi		// calculate address
+        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
+        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
+
+Traditionally, the textbook way to fix this would be to add an
+explicit early clobber to the instruction's constraints.
+
+ (define_insn_and_split "<insn>32di2_doubleword"
+- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
++ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
+        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
+                       (const_int 32)))]
+
+but unfortunately this currently generates significantly worse code,
+due to a strange choice of reloads (effectively memcpy), which ends up
+looking like:
+
+        salq    $4, %rdi		// calculate address
+        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
+        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
+        movq    -8(%rsp), %rdi		// load highpart
+        movq    -16(%rsp), %rbp		// load lowpart
+
+Note that reload's "&" doesn't distinguish between the memory being
+early clobbered, vs the registers used in an addressing mode being
+early clobbered.
+
+The fix proposed in this patch is to remove the third alternative, that
+allowed offsetable memory as an operand, forcing reload to place the
+operand into a register before the rotation.  This results in:
+
+        salq    $4, %rdi
+        movq    WHIRL_S(%rdi), %rax
+        movq    WHIRL_S+8(%rdi), %rdi
+        movq    %rax, %rbp
+
+I believe there's a more advanced solution, by swapping the order of
+the loads (if first destination register is mentioned in the address),
+or inserting a lea insn (if both destination registers are mentioned
+in the address), but this fix is a minimal "safe" solution, that
+should hopefully be suitable for backporting.
+
+2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
+
+gcc/ChangeLog
+	PR target/110792
+	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
+	place operand in a register before gen_<insn>64ti2_doubleword.
+	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
+	operand in a register before gen_<insn>32di2_doubleword.
+	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
+	(<any_rotate>64ti2_doubleword): Likewise.
+
+gcc/testsuite/ChangeLog
+	PR target/110792
+	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
+	* gcc.target/i386/pr110792.c: New 64-bit C test case.
+
+(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
+---
+ gcc/config/i386/i386.md                  | 18 ++++++++++++------
+ gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
+ gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
+ 3 files changed, 46 insertions(+), 6 deletions(-)
+ create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
+ create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
+
+diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
+index f3a3305..a71e837 100644
+--- a/gcc/config/i386/i386.md
++++ b/gcc/config/i386/i386.md
+@@ -14359,7 +14359,10 @@
+     emit_insn (gen_ix86_<insn>ti3_doubleword
+ 		(operands[0], operands[1], operands[2]));
+   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
+-    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
++    {
++      operands[1] = force_reg (TImode, operands[1]);
++      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
++    }
+   else
+     {
+       rtx amount = force_reg (QImode, operands[2]);
+@@ -14394,7 +14397,10 @@
+     emit_insn (gen_ix86_<insn>di3_doubleword
+ 		(operands[0], operands[1], operands[2]));
+   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
+-    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
++    {
++      operands[1] = force_reg (DImode, operands[1]);
++      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
++    }
+   else
+     FAIL;
+ 
+@@ -14562,8 +14568,8 @@
+ })
+ 
+ (define_insn_and_split "<insn>32di2_doubleword"
+- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+-       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
++ [(set (match_operand:DI 0 "register_operand" "=r,r")
++       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
+                       (const_int 32)))]
+  "!TARGET_64BIT"
+  "#"
+@@ -14580,8 +14586,8 @@
+ })
+ 
+ (define_insn_and_split "<insn>64ti2_doubleword"
+- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
+-       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
++ [(set (match_operand:TI 0 "register_operand" "=r,r")
++       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
+                       (const_int 64)))]
+  "TARGET_64BIT"
+  "#"
+diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
+new file mode 100644
+index 0000000..ce21a7a
+--- /dev/null
++++ b/gcc/testsuite/g++.target/i386/pr110792.C
+@@ -0,0 +1,16 @@
++/* { dg-do compile { target ia32 } } */
++/* { dg-options "-O2" } */
++
++template <int ROT, typename T>
++inline T rotr(T input)
++{
++   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
++}
++
++unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
++unsigned long long whirl(unsigned char x0)
++{
++   const unsigned long long s4 = WHIRL_S[x0&0xFF];
++   return rotr<32>(s4);
++}
++/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
+diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
+new file mode 100644
+index 0000000..b65125c
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/i386/pr110792.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile { target int128 } } */
++/* { dg-options "-O2" } */
++
++static inline unsigned __int128 rotr(unsigned __int128 input)
++{
++   return ((input >> 64) | (input << (64)));
++}
++
++unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
++unsigned __int128 whirl(unsigned char x0)
++{
++   register int t __asm("rdi") = x0&0xFF;
++   const unsigned __int128 s4 = WHIRL_S[t];
++   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
++   asm("":::"memory");
++   return tt;
++}
++/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
+-- 
+2.41.0
+

cross/gcc-riscv64/APKBUILD

@@ -24,8 +24,8 @@ CBUILDROOT="/"
 _cross_configure="--disable-bootstrap --with-sysroot=/usr/$CTARGET"
 
 pkgname=gcc-riscv64
-pkgver=13.1.1_git20230722
-# i.e. 13.1.1, must match gcc/BASE-VER
+pkgver=13.2.1_git20231014
+# i.e. 13.2.1, must match gcc/BASE-VER
 _pkgbase="${pkgver%%_git*}"
 # date component from snapshots
 _pkgsnap="${pkgver##*_git}"
@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-riscv64
-pkgrel=2
+pkgrel=0
 pkgdesc="Stage2 cross-compiler for riscv64"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -268,9 +268,13 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
-	0035-Fix-ICE-observed-in-PR110280.patch
+	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
 	"
 
+# secfixes:
+#   13.2.1_git20231014-r0:
+#     - CVE-2023-4039
+
 # we build out-of-tree
 _gccdir="$srcdir"/gcc-${_pkgbase%%.*}-$_pkgsnap
 _gcclibdir="/usr/lib/gcc/$CTARGET/${_pkgbase:-$pkgver}"
@@ -783,7 +787,7 @@ gdb() {
 }
 
 sha512sums="
-284719308cad4546ebd85934fb9f12112e8f1a4c3e5beea0760da1f73509907c194e7c133e6e755b6148bd1c51a72c071ac0d16b05641d901af7105461686655  gcc-13-20230722.tar.xz
+406673a62deba759fc0532a801b3f57cabf894ea328587b23e62a707ba5767b0e3ae9b3f86bf3c6fcf13e8a3c30bc470e6598b625c8231efb629034211c162c2  gcc-13-20231014.tar.xz
 1ecffba1b07d60e1b4422302b032bbea918b674c8e12b30aa6965b544d700ce86b61e9f7b8d402c6caf59257f491a394dd0912f0948565d6eae9335ee54f3b35  0001-posix_memalign.patch
 163f282455b6a4df33f011bcd8b0440566ba0ffaeeab30d8ac52d39948980a56881ca0eff60687129d59556389a58b9d64e7768750bd70b1fe0fedbc9fc30dc2  0002-gcc-poison-system-directories.patch
 3f24bb6a50d3c45b71ea05590e32fe3e69b91377ab185352891d5035c76ed193117c6d0b314a4c364bcf136b9a9dd5c926d6c7c30ab436976c121ebfea8d3ddd  0003-specs-turn-on-Wl-z-now-by-default.patch
@@ -818,5 +822,5 @@ d47b559075f40d526235f47b91da1d0cf6bfe6c5b7311bbfe08af9dd6e8f27e6c7cd82e3b2d529aa
 b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95e21c9ffbf2412193f8b9fc89a4c36fa5a6a041661ac7399d  0032-libgnat-time_t-is-always-64-bit-on-musl-libc.patch
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
-048d767f4477c92ee6835850d13063ede21c0be751d0945c94445d04054e134cdc617eeb0b1ac8c892a604d8644580fcfebeccaf537d6b7380558ac6378e445a  0035-Fix-ICE-observed-in-PR110280.patch
+cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
 "

cross/gcc-x86/0001-posix_memalign.patch

+From 47b4bd4deb2c356bb07d2a96f22127aefafec3a4 Mon Sep 17 00:00:00 2001
+From: Szabolcs Nagy <nsz@port70.net>
+Date: Fri, 26 Jan 2018 20:32:50 +0000
+Subject: [PATCH 01/35] posix_memalign
+
+---
+ gcc/config/i386/pmm_malloc.h | 9 +++++----
+ 1 file changed, 5 insertions(+), 4 deletions(-)
+
+diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h
+index 3527283693b..c4071b64b53 100644
+--- a/gcc/config/i386/pmm_malloc.h
++++ b/gcc/config/i386/pmm_malloc.h
+@@ -27,12 +27,13 @@
+ #include <stdlib.h>
+ 
+ /* We can't depend on <stdlib.h> since the prototype of posix_memalign
+-   may not be visible.  */
++   may not be visible and we can't pollute the namespace either.  */
+ #ifndef __cplusplus
+-extern int posix_memalign (void **, size_t, size_t);
++extern int _mm_posix_memalign (void **, size_t, size_t)
+ #else
+-extern "C" int posix_memalign (void **, size_t, size_t) throw ();
++extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw ()
+ #endif
++__asm__("posix_memalign");
+ 
+ static __inline void *
+ _mm_malloc (size_t __size, size_t __alignment)
+@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment)
+     return malloc (__size);
+   if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4))
+     __alignment = sizeof (void *);
+-  if (posix_memalign (&__ptr, __alignment, __size) == 0)
++  if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0)
+     return __ptr;
+   else
+     return NULL;
+-- 
+2.41.0
+