cross/busybox-static-aarch64/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=busybox-static-aarch64
 pkgver=1.36.1
-pkgrel=8
+pkgrel=12
 
 _arch="aarch64"
 _mirror="http://dl-4.alpinelinux.org/alpine/"
@@ -32,5 +32,5 @@ package() {
 }
 
 sha512sums="
-89b28ab6e676d9c789375a85840c1f1062670992e4e44199c01d2356c439ab4d07c24ea5251d96388e150eb1343d0043a97316128b9603ad3ecb40dfa80e9072  busybox-static-1.36.1-r8-aarch64-edge.apk
+d55a5850facdd40b8dd971fc074a4bfb6d6a8fb22e82db32e0de3d24dd889c01f09e420118500298f43dfd3e299e6315454e0a102ccd60e1f0b1a3e20107b04a  busybox-static-1.36.1-r12-aarch64-edge.apk
 "

cross/busybox-static-armhf/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=busybox-static-armhf
 pkgver=1.36.1
-pkgrel=8
+pkgrel=12
 
 _arch="armhf"
 _mirror="http://dl-4.alpinelinux.org/alpine/"
@@ -32,5 +32,5 @@ package() {
 }
 
 sha512sums="
-b9909d463d65476b6ef5766ccf0b5c432f5d6a0209aaef9cb1b838633e8128fd1ddecc821cc63743f9db1f2136b8884ed19986430549660bb89008dd98f986f6  busybox-static-1.36.1-r8-armhf-edge.apk
+778c2f5418d571f450e90851f60fb830e866a90e66c58db9e41112dc7e7354e4f514b0c68a447f2f52323a26687db49d4409e5a9d67f75910971d13f61c56968  busybox-static-1.36.1-r12-armhf-edge.apk
 "

cross/busybox-static-armv7/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=busybox-static-armv7
 pkgver=1.36.1
-pkgrel=8
+pkgrel=12
 
 _arch="armv7"
 _mirror="http://dl-4.alpinelinux.org/alpine/"
@@ -32,5 +32,5 @@ package() {
 }
 
 sha512sums="
-40094ff8b8d45fce75ff872f94cc24da5129c1b2a28da2a7336dd6995ca973cb595d0a46f6346d55c862fb72c6c517fe00f6d6d7b20c604f644d1f8c4fc1afb0  busybox-static-1.36.1-r8-armv7-edge.apk
+d9d8921bb8182eeb2e92a7ea5b531429bf51ca0ab1ea676c826e9cc310c7d8e859167b17f49718bfa27f29ff40d50aa0759f9efea032835c293bd8d0ee8cfa8e  busybox-static-1.36.1-r12-armv7-edge.apk
 "

cross/gcc-aarch64/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

+https://gcc.gnu.org/PR110792
+https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
+https://github.com/randombit/botan/issues/3637
+
+From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
+From: Roger Sayle <roger@nextmovesoftware.com>
+Date: Thu, 3 Aug 2023 07:12:04 +0100
+Subject: [PATCH] PR target/110792: Early clobber issues with
+ rot32di2_doubleword on i386.
+
+This patch is a conservative fix for PR target/110792, a wrong-code
+regression affecting doubleword rotations by BITS_PER_WORD, which
+effectively swaps the highpart and lowpart words, when the source to be
+rotated resides in memory. The issue is that if the register used to
+hold the lowpart of the destination is mentioned in the address of
+the memory operand, the current define_insn_and_split unintentionally
+clobbers it before reading the highpart.
+
+Hence, for the testcase, the incorrectly generated code looks like:
+
+        salq    $4, %rdi		// calculate address
+        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
+        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
+
+Traditionally, the textbook way to fix this would be to add an
+explicit early clobber to the instruction's constraints.
+
+ (define_insn_and_split "<insn>32di2_doubleword"
+- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
++ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
+        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
+                       (const_int 32)))]
+
+but unfortunately this currently generates significantly worse code,
+due to a strange choice of reloads (effectively memcpy), which ends up
+looking like:
+
+        salq    $4, %rdi		// calculate address
+        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
+        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
+        movq    -8(%rsp), %rdi		// load highpart
+        movq    -16(%rsp), %rbp		// load lowpart
+
+Note that reload's "&" doesn't distinguish between the memory being
+early clobbered, vs the registers used in an addressing mode being
+early clobbered.
+
+The fix proposed in this patch is to remove the third alternative, that
+allowed offsetable memory as an operand, forcing reload to place the
+operand into a register before the rotation.  This results in:
+
+        salq    $4, %rdi
+        movq    WHIRL_S(%rdi), %rax
+        movq    WHIRL_S+8(%rdi), %rdi
+        movq    %rax, %rbp
+
+I believe there's a more advanced solution, by swapping the order of
+the loads (if first destination register is mentioned in the address),
+or inserting a lea insn (if both destination registers are mentioned
+in the address), but this fix is a minimal "safe" solution, that
+should hopefully be suitable for backporting.
+
+2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
+
+gcc/ChangeLog
+	PR target/110792
+	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
+	place operand in a register before gen_<insn>64ti2_doubleword.
+	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
+	operand in a register before gen_<insn>32di2_doubleword.
+	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
+	(<any_rotate>64ti2_doubleword): Likewise.
+
+gcc/testsuite/ChangeLog
+	PR target/110792
+	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
+	* gcc.target/i386/pr110792.c: New 64-bit C test case.
+
+(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
+---
+ gcc/config/i386/i386.md                  | 18 ++++++++++++------
+ gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
+ gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
+ 3 files changed, 46 insertions(+), 6 deletions(-)
+ create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
+ create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
+
+diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
+index f3a3305..a71e837 100644
+--- a/gcc/config/i386/i386.md
++++ b/gcc/config/i386/i386.md
+@@ -14359,7 +14359,10 @@
+     emit_insn (gen_ix86_<insn>ti3_doubleword
+ 		(operands[0], operands[1], operands[2]));
+   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
+-    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
++    {
++      operands[1] = force_reg (TImode, operands[1]);
++      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
++    }
+   else
+     {
+       rtx amount = force_reg (QImode, operands[2]);
+@@ -14394,7 +14397,10 @@
+     emit_insn (gen_ix86_<insn>di3_doubleword
+ 		(operands[0], operands[1], operands[2]));
+   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
+-    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
++    {
++      operands[1] = force_reg (DImode, operands[1]);
++      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
++    }
+   else
+     FAIL;
+ 
+@@ -14562,8 +14568,8 @@
+ })
+ 
+ (define_insn_and_split "<insn>32di2_doubleword"
+- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+-       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
++ [(set (match_operand:DI 0 "register_operand" "=r,r")
++       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
+                       (const_int 32)))]
+  "!TARGET_64BIT"
+  "#"
+@@ -14580,8 +14586,8 @@
+ })
+ 
+ (define_insn_and_split "<insn>64ti2_doubleword"
+- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
+-       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
++ [(set (match_operand:TI 0 "register_operand" "=r,r")
++       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
+                       (const_int 64)))]
+  "TARGET_64BIT"
+  "#"
+diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
+new file mode 100644
+index 0000000..ce21a7a
+--- /dev/null
++++ b/gcc/testsuite/g++.target/i386/pr110792.C
+@@ -0,0 +1,16 @@
++/* { dg-do compile { target ia32 } } */
++/* { dg-options "-O2" } */
++
++template <int ROT, typename T>
++inline T rotr(T input)
++{
++   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
++}
++
++unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
++unsigned long long whirl(unsigned char x0)
++{
++   const unsigned long long s4 = WHIRL_S[x0&0xFF];
++   return rotr<32>(s4);
++}
++/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
+diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
+new file mode 100644
+index 0000000..b65125c
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/i386/pr110792.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile { target int128 } } */
++/* { dg-options "-O2" } */
++
++static inline unsigned __int128 rotr(unsigned __int128 input)
++{
++   return ((input >> 64) | (input << (64)));
++}
++
++unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
++unsigned __int128 whirl(unsigned char x0)
++{
++   register int t __asm("rdi") = x0&0xFF;
++   const unsigned __int128 s4 = WHIRL_S[t];
++   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
++   asm("":::"memory");
++   return tt;
++}
++/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
+-- 
+2.41.0
+

cross/gcc-aarch64/APKBUILD

@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-aarch64
-pkgrel=2
+pkgrel=3
 pkgdesc="Stage2 cross-compiler for aarch64"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -269,6 +269,7 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-Fix-ICE-observed-in-PR110280.patch
+	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
 	"
 
 # we build out-of-tree
@@ -819,4 +820,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 048d767f4477c92ee6835850d13063ede21c0be751d0945c94445d04054e134cdc617eeb0b1ac8c892a604d8644580fcfebeccaf537d6b7380558ac6378e445a  0035-Fix-ICE-observed-in-PR110280.patch
+cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
 "

cross/gcc-armhf/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

+https://gcc.gnu.org/PR110792
+https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
+https://github.com/randombit/botan/issues/3637
+
+From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
+From: Roger Sayle <roger@nextmovesoftware.com>
+Date: Thu, 3 Aug 2023 07:12:04 +0100
+Subject: [PATCH] PR target/110792: Early clobber issues with
+ rot32di2_doubleword on i386.
+
+This patch is a conservative fix for PR target/110792, a wrong-code
+regression affecting doubleword rotations by BITS_PER_WORD, which
+effectively swaps the highpart and lowpart words, when the source to be
+rotated resides in memory. The issue is that if the register used to
+hold the lowpart of the destination is mentioned in the address of
+the memory operand, the current define_insn_and_split unintentionally
+clobbers it before reading the highpart.
+
+Hence, for the testcase, the incorrectly generated code looks like:
+
+        salq    $4, %rdi		// calculate address
+        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
+        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
+
+Traditionally, the textbook way to fix this would be to add an
+explicit early clobber to the instruction's constraints.
+
+ (define_insn_and_split "<insn>32di2_doubleword"
+- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
++ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
+        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
+                       (const_int 32)))]
+
+but unfortunately this currently generates significantly worse code,
+due to a strange choice of reloads (effectively memcpy), which ends up
+looking like:
+
+        salq    $4, %rdi		// calculate address
+        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
+        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
+        movq    -8(%rsp), %rdi		// load highpart
+        movq    -16(%rsp), %rbp		// load lowpart
+
+Note that reload's "&" doesn't distinguish between the memory being
+early clobbered, vs the registers used in an addressing mode being
+early clobbered.
+
+The fix proposed in this patch is to remove the third alternative, that
+allowed offsetable memory as an operand, forcing reload to place the
+operand into a register before the rotation.  This results in:
+
+        salq    $4, %rdi
+        movq    WHIRL_S(%rdi), %rax
+        movq    WHIRL_S+8(%rdi), %rdi
+        movq    %rax, %rbp
+
+I believe there's a more advanced solution, by swapping the order of
+the loads (if first destination register is mentioned in the address),
+or inserting a lea insn (if both destination registers are mentioned
+in the address), but this fix is a minimal "safe" solution, that
+should hopefully be suitable for backporting.
+
+2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
+
+gcc/ChangeLog
+	PR target/110792
+	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
+	place operand in a register before gen_<insn>64ti2_doubleword.
+	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
+	operand in a register before gen_<insn>32di2_doubleword.
+	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
+	(<any_rotate>64ti2_doubleword): Likewise.
+
+gcc/testsuite/ChangeLog
+	PR target/110792
+	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
+	* gcc.target/i386/pr110792.c: New 64-bit C test case.
+
+(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
+---
+ gcc/config/i386/i386.md                  | 18 ++++++++++++------
+ gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
+ gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
+ 3 files changed, 46 insertions(+), 6 deletions(-)
+ create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
+ create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
+
+diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
+index f3a3305..a71e837 100644
+--- a/gcc/config/i386/i386.md
++++ b/gcc/config/i386/i386.md
+@@ -14359,7 +14359,10 @@
+     emit_insn (gen_ix86_<insn>ti3_doubleword
+ 		(operands[0], operands[1], operands[2]));
+   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
+-    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
++    {
++      operands[1] = force_reg (TImode, operands[1]);
++      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
++    }
+   else
+     {
+       rtx amount = force_reg (QImode, operands[2]);
+@@ -14394,7 +14397,10 @@
+     emit_insn (gen_ix86_<insn>di3_doubleword
+ 		(operands[0], operands[1], operands[2]));
+   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
+-    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
++    {
++      operands[1] = force_reg (DImode, operands[1]);
++      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
++    }
+   else
+     FAIL;
+ 
+@@ -14562,8 +14568,8 @@
+ })
+ 
+ (define_insn_and_split "<insn>32di2_doubleword"
+- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+-       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
++ [(set (match_operand:DI 0 "register_operand" "=r,r")
++       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
+                       (const_int 32)))]
+  "!TARGET_64BIT"
+  "#"
+@@ -14580,8 +14586,8 @@
+ })
+ 
+ (define_insn_and_split "<insn>64ti2_doubleword"
+- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
+-       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
++ [(set (match_operand:TI 0 "register_operand" "=r,r")
++       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
+                       (const_int 64)))]
+  "TARGET_64BIT"
+  "#"
+diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
+new file mode 100644
+index 0000000..ce21a7a
+--- /dev/null
++++ b/gcc/testsuite/g++.target/i386/pr110792.C
+@@ -0,0 +1,16 @@
++/* { dg-do compile { target ia32 } } */
++/* { dg-options "-O2" } */
++
++template <int ROT, typename T>
++inline T rotr(T input)
++{
++   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
++}
++
++unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
++unsigned long long whirl(unsigned char x0)
++{
++   const unsigned long long s4 = WHIRL_S[x0&0xFF];
++   return rotr<32>(s4);
++}
++/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
+diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
+new file mode 100644
+index 0000000..b65125c
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/i386/pr110792.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile { target int128 } } */
++/* { dg-options "-O2" } */
++
++static inline unsigned __int128 rotr(unsigned __int128 input)
++{
++   return ((input >> 64) | (input << (64)));
++}
++
++unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
++unsigned __int128 whirl(unsigned char x0)
++{
++   register int t __asm("rdi") = x0&0xFF;
++   const unsigned __int128 s4 = WHIRL_S[t];
++   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
++   asm("":::"memory");
++   return tt;
++}
++/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
+-- 
+2.41.0
+

cross/gcc-armhf/APKBUILD

@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-armhf
-pkgrel=2
+pkgrel=3
 pkgdesc="Stage2 cross-compiler for armhf"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -269,6 +269,7 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-Fix-ICE-observed-in-PR110280.patch
+	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
 	"
 
 # we build out-of-tree
@@ -819,4 +820,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 048d767f4477c92ee6835850d13063ede21c0be751d0945c94445d04054e134cdc617eeb0b1ac8c892a604d8644580fcfebeccaf537d6b7380558ac6378e445a  0035-Fix-ICE-observed-in-PR110280.patch
+cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
 "

cross/gcc-armv7/0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch

+https://gcc.gnu.org/PR110792
+https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=790c1f60a5662b16eb19eb4b81922995863c7571
+https://github.com/randombit/botan/issues/3637
+
+From 85628c5653ff40963158a24c60eeec6a3b5a8e56 Mon Sep 17 00:00:00 2001
+From: Roger Sayle <roger@nextmovesoftware.com>
+Date: Thu, 3 Aug 2023 07:12:04 +0100
+Subject: [PATCH] PR target/110792: Early clobber issues with
+ rot32di2_doubleword on i386.
+
+This patch is a conservative fix for PR target/110792, a wrong-code
+regression affecting doubleword rotations by BITS_PER_WORD, which
+effectively swaps the highpart and lowpart words, when the source to be
+rotated resides in memory. The issue is that if the register used to
+hold the lowpart of the destination is mentioned in the address of
+the memory operand, the current define_insn_and_split unintentionally
+clobbers it before reading the highpart.
+
+Hence, for the testcase, the incorrectly generated code looks like:
+
+        salq    $4, %rdi		// calculate address
+        movq    WHIRL_S+8(%rdi), %rdi	// accidentally clobber addr
+        movq    WHIRL_S(%rdi), %rbp	// load (wrong) lowpart
+
+Traditionally, the textbook way to fix this would be to add an
+explicit early clobber to the instruction's constraints.
+
+ (define_insn_and_split "<insn>32di2_doubleword"
+- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
++ [(set (match_operand:DI 0 "register_operand" "=r,r,&r")
+        (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
+                       (const_int 32)))]
+
+but unfortunately this currently generates significantly worse code,
+due to a strange choice of reloads (effectively memcpy), which ends up
+looking like:
+
+        salq    $4, %rdi		// calculate address
+        movdqa  WHIRL_S(%rdi), %xmm0	// load the double word in SSE reg.
+        movaps  %xmm0, -16(%rsp)	// store the SSE reg back to the stack
+        movq    -8(%rsp), %rdi		// load highpart
+        movq    -16(%rsp), %rbp		// load lowpart
+
+Note that reload's "&" doesn't distinguish between the memory being
+early clobbered, vs the registers used in an addressing mode being
+early clobbered.
+
+The fix proposed in this patch is to remove the third alternative, that
+allowed offsetable memory as an operand, forcing reload to place the
+operand into a register before the rotation.  This results in:
+
+        salq    $4, %rdi
+        movq    WHIRL_S(%rdi), %rax
+        movq    WHIRL_S+8(%rdi), %rdi
+        movq    %rax, %rbp
+
+I believe there's a more advanced solution, by swapping the order of
+the loads (if first destination register is mentioned in the address),
+or inserting a lea insn (if both destination registers are mentioned
+in the address), but this fix is a minimal "safe" solution, that
+should hopefully be suitable for backporting.
+
+2023-08-03  Roger Sayle  <roger@nextmovesoftware.com>
+
+gcc/ChangeLog
+	PR target/110792
+	* config/i386/i386.md (<any_rotate>ti3): For rotations by 64 bits
+	place operand in a register before gen_<insn>64ti2_doubleword.
+	(<any_rotate>di3): Likewise, for rotations by 32 bits, place
+	operand in a register before gen_<insn>32di2_doubleword.
+	(<any_rotate>32di2_doubleword): Constrain operand to be in register.
+	(<any_rotate>64ti2_doubleword): Likewise.
+
+gcc/testsuite/ChangeLog
+	PR target/110792
+	* g++.target/i386/pr110792.C: New 32-bit C++ test case.
+	* gcc.target/i386/pr110792.c: New 64-bit C test case.
+
+(cherry picked from commit 790c1f60a5662b16eb19eb4b81922995863c7571)
+---
+ gcc/config/i386/i386.md                  | 18 ++++++++++++------
+ gcc/testsuite/g++.target/i386/pr110792.C | 16 ++++++++++++++++
+ gcc/testsuite/gcc.target/i386/pr110792.c | 18 ++++++++++++++++++
+ 3 files changed, 46 insertions(+), 6 deletions(-)
+ create mode 100644 gcc/testsuite/g++.target/i386/pr110792.C
+ create mode 100644 gcc/testsuite/gcc.target/i386/pr110792.c
+
+diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
+index f3a3305..a71e837 100644
+--- a/gcc/config/i386/i386.md
++++ b/gcc/config/i386/i386.md
+@@ -14359,7 +14359,10 @@
+     emit_insn (gen_ix86_<insn>ti3_doubleword
+ 		(operands[0], operands[1], operands[2]));
+   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 64)
+-    emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
++    {
++      operands[1] = force_reg (TImode, operands[1]);
++      emit_insn (gen_<insn>64ti2_doubleword (operands[0], operands[1]));
++    }
+   else
+     {
+       rtx amount = force_reg (QImode, operands[2]);
+@@ -14394,7 +14397,10 @@
+     emit_insn (gen_ix86_<insn>di3_doubleword
+ 		(operands[0], operands[1], operands[2]));
+   else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 32)
+-    emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
++    {
++      operands[1] = force_reg (DImode, operands[1]);
++      emit_insn (gen_<insn>32di2_doubleword (operands[0], operands[1]));
++    }
+   else
+     FAIL;
+ 
+@@ -14562,8 +14568,8 @@
+ })
+ 
+ (define_insn_and_split "<insn>32di2_doubleword"
+- [(set (match_operand:DI 0 "register_operand" "=r,r,r")
+-       (any_rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,r,o")
++ [(set (match_operand:DI 0 "register_operand" "=r,r")
++       (any_rotate:DI (match_operand:DI 1 "register_operand" "0,r")
+                       (const_int 32)))]
+  "!TARGET_64BIT"
+  "#"
+@@ -14580,8 +14586,8 @@
+ })
+ 
+ (define_insn_and_split "<insn>64ti2_doubleword"
+- [(set (match_operand:TI 0 "register_operand" "=r,r,r")
+-       (any_rotate:TI (match_operand:TI 1 "nonimmediate_operand" "0,r,o")
++ [(set (match_operand:TI 0 "register_operand" "=r,r")
++       (any_rotate:TI (match_operand:TI 1 "register_operand" "0,r")
+                       (const_int 64)))]
+  "TARGET_64BIT"
+  "#"
+diff --git a/gcc/testsuite/g++.target/i386/pr110792.C b/gcc/testsuite/g++.target/i386/pr110792.C
+new file mode 100644
+index 0000000..ce21a7a
+--- /dev/null
++++ b/gcc/testsuite/g++.target/i386/pr110792.C
+@@ -0,0 +1,16 @@
++/* { dg-do compile { target ia32 } } */
++/* { dg-options "-O2" } */
++
++template <int ROT, typename T>
++inline T rotr(T input)
++{
++   return static_cast<T>((input >> ROT) | (input << (8 * sizeof(T) - ROT)));
++}
++
++unsigned long long WHIRL_S[256] = {0x18186018C07830D8};
++unsigned long long whirl(unsigned char x0)
++{
++   const unsigned long long s4 = WHIRL_S[x0&0xFF];
++   return rotr<32>(s4);
++}
++/* { dg-final { scan-assembler-not "movl\tWHIRL_S\\+4\\(,%eax,8\\), %eax" } } */
+diff --git a/gcc/testsuite/gcc.target/i386/pr110792.c b/gcc/testsuite/gcc.target/i386/pr110792.c
+new file mode 100644
+index 0000000..b65125c
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/i386/pr110792.c
+@@ -0,0 +1,18 @@
++/* { dg-do compile { target int128 } } */
++/* { dg-options "-O2" } */
++
++static inline unsigned __int128 rotr(unsigned __int128 input)
++{
++   return ((input >> 64) | (input << (64)));
++}
++
++unsigned __int128 WHIRL_S[256] = {((__int128)0x18186018C07830D8) << 64 |0x18186018C07830D8};
++unsigned __int128 whirl(unsigned char x0)
++{
++   register int t __asm("rdi") = x0&0xFF;
++   const unsigned __int128 s4 = WHIRL_S[t];
++   register unsigned __int128 tt  __asm("rdi") = rotr(s4);
++   asm("":::"memory");
++   return tt;
++}
++/* { dg-final { scan-assembler-not "movq\tWHIRL_S\\+8\\(%rdi\\), %rdi" } } */
+-- 
+2.41.0
+

cross/gcc-armv7/APKBUILD

@@ -34,7 +34,7 @@ _pkgsnap="${pkgver##*_git}"
 [ "$CHOST" != "$CTARGET" ] && _target="-$CTARGET_ARCH" || _target=""
 
 pkgname=gcc-armv7
-pkgrel=2
+pkgrel=3
 pkgdesc="Stage2 cross-compiler for armv7"
 url="https://gcc.gnu.org"
 arch="x86_64"
@@ -269,6 +269,7 @@ source="https://dev.alpinelinux.org/archive/gcc/${_pkgbase%%.*}-$_pkgsnap/gcc-${
 	0033-libphobos-do-not-use-LFS64-symbols.patch
 	0034-libgo-fix-lfs64-use.patch
 	0035-Fix-ICE-observed-in-PR110280.patch
+	0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
 	"
 
 # we build out-of-tree
@@ -819,4 +820,5 @@ b325035cb7122d79c6b42ca6d3fc9e02319ed2f7cddb0639dff25d2798d2ce63812cd623462cdf95
 c474f34e6f9a4239d486a65141a133dbe8ce91427d502a57a9fd6eb403478a2b5715ba74f24c1cc0761e16eec77ba2c1ca921fb7d7bc1e040fc3703fc9559e75  0033-libphobos-do-not-use-LFS64-symbols.patch
 c4482ffc36e7894b2140800159f4cbc9a3e9011e43a69b69f4fa92d5a11e2ee645c7e21df4423dd1e0636e8890849a5719647bfbdf84f951d638f8f488cb718c  0034-libgo-fix-lfs64-use.patch
 048d767f4477c92ee6835850d13063ede21c0be751d0945c94445d04054e134cdc617eeb0b1ac8c892a604d8644580fcfebeccaf537d6b7380558ac6378e445a  0035-Fix-ICE-observed-in-PR110280.patch
+cc1e10ac6e72db816f09325e301103109cc212a6f3de3ce0b9b038d149233c467319d203941695dbf3d7b9e2dcbbcd17609cdb056e831fcc323cd592423882d8  0036-PR110792-Early-clobber-issues-with-rot32di2-on-i386.patch
 "

cross/musl-aarch64/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-aarch64
 pkgver=1.2.4_git20230717
-pkgrel=2
+pkgrel=3
 arch="x86_64"
 subpackages="musl-dev-aarch64:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-4c09316bf7c43332911bd845c1c737fdb032f1c05103db52d7a84a823d3e0ce8aeb2767e544c6121a9b77f64e38d60b98c19a079299ff16cbd79331364a3cc52  musl-1.2.4_git20230717-r2-aarch64-edge.apk
-eb509419fda2d08096b147a66fe4a412d0d5341d26ed78dfacc4aef90b02277072b7b1865f5843386f9c73500eb2984a28252519fe2c264aafe95e4ead2dd8d2  musl-dev-1.2.4_git20230717-r2-aarch64-edge.apk
+7f450061d9d45902ab90180816592426fe0e5f148a1a3373196b7d0564abe26780223a641006ce7d9808e0258b63646a3d7a551ab686a5590e064f25a63540e8  musl-1.2.4_git20230717-r3-aarch64-edge.apk
+4a4e255a149ceec21b644bf63a46a324955714154340052771734d5c303779c997ea1be02c4b45c16186ab3c50fdaa26eecfb0ebcfcba5ba8e0bf56d66df461b  musl-dev-1.2.4_git20230717-r3-aarch64-edge.apk
 "

cross/musl-armhf/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-armhf
 pkgver=1.2.4_git20230717
-pkgrel=2
+pkgrel=3
 arch="x86_64"
 subpackages="musl-dev-armhf:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-3cf75f7d646b721359620549c429025d944d88a57146633b4ca3b9ae4019fcfa2701ceeeb8c93ffa992ff29f19914bb6c6478ef1002032bd046bbd78a244203b  musl-1.2.4_git20230717-r2-armhf-edge.apk
-e7f64f165e5ca3a36dfc233ca10d9609772e29c51a40e0d2dcae518179b4c2f9c86d09884d82e5767fef82ea55bacf5169fd6028f30ca68ba27d984713f37241  musl-dev-1.2.4_git20230717-r2-armhf-edge.apk
+174208a869df2aa25806a3440b990c789c60609e3f8504ac0cf1068db753a309293994cd3482f28bb4a375ea8c42bddcd136f0eaf0af2bf3a779a80eba86ac49  musl-1.2.4_git20230717-r3-armhf-edge.apk
+9e76f36edb13bd09f149085c57135b2ced3093f5a617d7a29ea6cb40ca53fb82e141bc950918a55757213364d7ff9d4d83e2545f60686e94bebc1c21b01bcc91  musl-dev-1.2.4_git20230717-r3-armhf-edge.apk
 "

cross/musl-armv7/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-armv7
 pkgver=1.2.4_git20230717
-pkgrel=2
+pkgrel=3
 arch="x86_64"
 subpackages="musl-dev-armv7:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-ea0bb9d0b3bf8b36d2e3e12430c1cc21b4e722d3a162fced049dcb8a5f9089c324695c10e8cec181cba73c3c83fc6c9b5b70f38509c60127a6e9bcd6621dca37  musl-1.2.4_git20230717-r2-armv7-edge.apk
-80b71f862149d9d28df52eb73ea1f42d387fe400a5982f751e64323713be86dcb53a7492ea6b24fa56ac0d8e518f07dcc6341b9a026d06c144fe6bbf83bb4b2e  musl-dev-1.2.4_git20230717-r2-armv7-edge.apk
+0115bc654494c59bf0b77ac7118f14dce31cd8f86c3d5a20e3fdd49e66dd1c0d0fc1973b92f236e5845c2cf5395c19344acc4ea24c1f19095d44cc526fbc30c4  musl-1.2.4_git20230717-r3-armv7-edge.apk
+5a1558325c7a6b02556975ebb2014319657f3f5a721a49eb3b744a18fb7977d91c966d1a1a38f7f5a7c371585d88ebff436a2239e59bb695752167bc4fd7db7d  musl-dev-1.2.4_git20230717-r3-armv7-edge.apk
 "

cross/musl-riscv64/APKBUILD

@@ -8,7 +8,7 @@ fi
 
 pkgname=musl-riscv64
 pkgver=1.2.4_git20230717
-pkgrel=2
+pkgrel=3
 arch="x86_64"
 subpackages="musl-dev-riscv64:package_dev"
 
@@ -57,6 +57,6 @@ package_dev() {
 }
 
 sha512sums="
-76da75cb9de40f521ece5518980e28a8bdc7ee108229f574d9e7c61bc7956eae7f8ecf226b93fdd8d5d75ca9392cf6e0fe8b6f8044bfb07a8253ce6082689ca0  musl-1.2.4_git20230717-r2-riscv64-edge.apk
-7faed112e8b521c469acb7aad062beff8637be8ae403d856f3c1c678ce9921239ad4fdbaa196ca7abad88fc8952038627a3c4c741e5368a6de66ea7eb1440f51  musl-dev-1.2.4_git20230717-r2-riscv64-edge.apk
+1b0ab754d99bcc6216c5c1c49a7337e87268f7c9a8af9ec9c73b75f366672922b53c4b3c8950178419585699a7899d2000a8f9c498c123854f284b2778fdbc7f  musl-1.2.4_git20230717-r3-riscv64-edge.apk
+0ed3a00b5c1072b01cf0573cab70ec9fe2027c804b7f6c046ca00daa7d3d5083ed639e76467b98ffed1d45f938a73aff8b0e7da0ca00a4cbbed107021df52794  musl-dev-1.2.4_git20230717-r3-riscv64-edge.apk
 "

device/community/device-oneplus-enchilada/10-unl0kr.conf

+[quirks]
+fbdev_force_refresh=true
\ No newline at end of file

device/community/device-oneplus-enchilada/APKBUILD

@@ -3,8 +3,8 @@
 
 pkgname=device-oneplus-enchilada
 pkgdesc="OnePlus 6"
-pkgver=10
-pkgrel=2
+pkgver=11
+pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -20,6 +20,7 @@ depends="
 "
 makedepends="devicepkg-dev"
 source="
+	10-unl0kr.conf
 	deviceinfo
 	modules-initfs
 	q6voiced.conf
@@ -32,6 +33,9 @@ build() {
 
 package() {
 	devicepkg_package $startdir $pkgname
+
+	install -Dm644 "$srcdir"/10-unl0kr.conf \
+		"$pkgdir"/etc/unl0kr.conf.d/10-unl0kr.conf
 }
 
 nonfree_firmware() {
@@ -44,6 +48,7 @@ nonfree_firmware() {
 }
 
 sha512sums="
+e957b7b0ed219eaa56be6c6b976b60886f73970703fdebf045800154ee652affee4e19654b3ac4244b29bcf6760ad3db6cb87143dc9c4673e905800d751103d1  10-unl0kr.conf
 71b4d74cebe22556b2c819fdb6b279366c9a566cb077f6e6e80c0c0b2e7c7fca48ea23ffbacca5cce4c636d8f3e66ad8f66ce36e954644242f6b5a71c89f9ed6  deviceinfo
 ea8709aa214cffaefb1d486c0c47044537446faebff16efb3b015623f043f730b7121e401c676e43aa8868bd6c630fc8a2d7dbf5fb082490e9b5493e0405b66d  modules-initfs
 fe9871c325a38c0cadc9631870801ec15ab9f5b786ee854325b93eb3d23e7d8b1ac4f1075572ffcd225d8ec514dec09b986972ddff12a89260c0218af6de7887  q6voiced.conf

device/testing/device-xiaomi-daisy/APKBUILD → device/community/device-xiaomi-daisy/APKBUILD

-# Maintainer: Alikates <alikates@dnyon.com>
+# Maintainer: Alejandro Tafalla <alikates@dnyon.com>
 # Reference: <https://postmarketos.org/devicepkg>
 pkgname=device-xiaomi-daisy
 pkgdesc="Xiaomi Mi A2 Lite"
-pkgver=6
-pkgrel=4
+pkgver=7
+pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
 options="!check !archcheck"
-depends="postmarketos-base mkbootimg soc-qcom-msm8953 linux-postmarketos-qcom-msm8953 lk2nd-msm8953"
+depends="
+	linux-postmarketos-qcom-msm8953
+	lk2nd-msm8953
+	mkbootimg
+	postmarketos-base
+	soc-qcom-msm8953
+"
 makedepends="devicepkg-dev"
 subpackages="
-		$pkgname-nonfree-firmware:nonfree_firmware
-		$pkgname-modem
-		"
+	$pkgname-nonfree-firmware:nonfree_firmware
+"
 source="
 	deviceinfo
 	modules-initfs
-	30-gpu-firmware.files
-	"
+"
 
 build() {
 	devicepkg_build $startdir $pkgname
@@ -26,23 +30,21 @@ build() {
 
 package() {
 	devicepkg_package $startdir $pkgname
-	install -Dm0644 "$srcdir"/30-gpu-firmware.files "$pkgdir"/usr/share/mkinitfs/files/30-gpu-firmware.files
 }
 
 nonfree_firmware() {
-	pkgdesc="Wi-Fi, ADSP Firmware"
-	depends="firmware-xiaomi-daisy"
-	mkdir "$subpkgdir"
-}
-
-modem() {
-	depends="qrtr rmtfs rmtfs-openrc msm-modem-uim-selection"
-	install_if="$pkgname=$pkgver-r$pkgrel $pkgname-nonfree-firmware"
+	pkgdesc="Modem, WiFi, BT, ADSP, Venus and GPU Firmware"
+	depends="
+		firmware-xiaomi-daisy
+		msm-firmware-loader
+		qbootctl
+		soc-qcom-msm8953-initramfs
+		soc-qcom-msm8953-modem
+	"
 	mkdir "$subpkgdir"
 }
 
 sha512sums="
 8c5980c1da9e5bc91f11bb8056ac9a225cb84a90a42a964dc0dc2966220c105683081055fdcb1caa8c198019d8373d8c5fe27155429c17814d34075d5f961aa4  deviceinfo
-cb1729cae5703aaf3aee069af5f3440b84d0958f4c3a9c5c027d4e6b62ca0792d2e09cbb9afb86e00e192cc29de41ebdc8365c09a1656867941acff098e07fb8  modules-initfs
-302c0bec754bb79ef561c1a8d4ff34ba52b904c853bce6a15a79ba7b5b7a3d02c1c75bbe86d59be7b608a6dc744dd3e3c638eaa4539c53d20fa55fa5ea397d74  30-gpu-firmware.files
+0a1d769e4e60aca37dc71bdde9e6befbe74c09d775e19788d18a07e06546cbddd46efc876df0a89073f0819c9cc66e319f398772dec75f537ec5b82aa3032002  modules-initfs
 "

device/testing/device-xiaomi-daisy/modules-initfs → device/community/device-xiaomi-daisy/modules-initfs

-msm
+bam_dma
 edt_ft5x06
-panel_mdss_ili7807_fhdplus
+msm
 panel_himax_hx8399c_fhdplus
+panel_mdss_ili7807_fhdplus
+panel_mdss_otm1911_fhdplus

device/testing/device-xiaomi-markw/APKBUILD → device/community/device-xiaomi-markw/APKBUILD

+# Maintainer: Victor Pavlov (vipaoL) <vipaolmail@gmail.com>
 # Reference: <https://postmarketos.org/devicepkg>
 pkgname=device-xiaomi-markw
 pkgdesc="Xiaomi Redmi 4 Prime"
-pkgver=1.0
-pkgrel=4
+pkgver=2
+pkgrel=0
 url="https://postmarketos.org"
 license="MIT"
 arch="aarch64"
@@ -28,10 +29,16 @@ package() {
 
 nonfree_firmware() {
 	pkgdesc="WiFi, Bluetooth, Modem, Display and GPU Firmware"
-	depends="firmware-xiaomi-markw"
+	depends="
+		firmware-xiaomi-markw
+		msm-firmware-loader
+		soc-qcom-msm8953-initramfs
+		soc-qcom-msm8953-modem
+	"
 	mkdir "$subpkgdir"
 }
+
 sha512sums="
 0d393f07e551058781a67c096b1ad7f252c78e801a2da8752f893f4ea7c24f7aa65bc69f9c80c7be53e615269a7028eb151e7bc3fe79f0c260a4d28e97f10e7d  deviceinfo
-44efe9884cf2af88efd4bfbb68536977eac9cc04e5d270b9fc38d308f0181161fc968456ab2ca9b82996aa3cc5bff33dae590048c35fdbafdcef273bc5269613  modules-initfs
+a99cfed9b2b5afed33127874706841fc6e85dd0e663c5d924c8d22ec0c93f86c72d22943dcf1af5f7a840915c13e713583d359ffbefae812c95e3a5824d492e8  modules-initfs
 "