main/crust/0289a01c9ee211195728e14b4f26dd2e5226561a.patch

+From 0289a01c9ee211195728e14b4f26dd2e5226561a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 28 May 2021 18:26:39 -0500
+Subject: [PATCH] drivers: irq: Remove deprecated GPIO polling code
+
+Since v5.13, specifically commit 189bef235dd3 ("arm64: dts: allwinner:
+Move wakeup-capable IRQs to r_intc"), Linux routes the GPIO EINT IRQs to
+R_INTC during suspend and shutdown. This means Crust will detect pending
+EINT IRQs using the normal R_INTC status polling code.
+
+This change completely obsoletes the GPIO register polling code, so that
+code and its associated Kconfig options can be removed.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ configs/pinephone_defconfig    |  2 --
+ drivers/Kconfig                |  1 -
+ drivers/irq/Kconfig            | 51 ----------------------------------
+ drivers/irq/irq.c              | 29 ++-----------------
+ drivers/irq/irq.h              | 16 -----------
+ drivers/irq/sun6i-a31-r-intc.c |  4 +--
+ 6 files changed, 4 insertions(+), 99 deletions(-)
+ delete mode 100644 drivers/irq/Kconfig
+ delete mode 100644 drivers/irq/irq.h
+
+diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig
+index 5e720f1f..875ad025 100644
+--- a/configs/pinephone_defconfig
++++ b/configs/pinephone_defconfig
+@@ -1,4 +1,2 @@
+-CONFIG_IRQ_POLL_EINT=y
+-CONFIG_IRQ_POLL_EINT_LAST_BANK=0
+ CONFIG_MFD_AXP20X=y
+ # CONFIG_SERIAL is not set
+diff --git a/drivers/Kconfig b/drivers/Kconfig
+index 0cb6dae5..5f513533 100644
+--- a/drivers/Kconfig
++++ b/drivers/Kconfig
+@@ -8,7 +8,6 @@ menu "Device drivers"
+ source "dram/Kconfig"
+ source "cir/Kconfig"
+ source "clock/Kconfig"
+-source "irq/Kconfig"
+ source "regmap/Kconfig"
+ source "mfd/Kconfig"
+ source "pmic/Kconfig"
+diff --git a/drivers/irq/Kconfig b/drivers/irq/Kconfig
+deleted file mode 100644
+index 84330c8b..00000000
+--- a/drivers/irq/Kconfig
++++ /dev/null
+@@ -1,51 +0,0 @@
+-#
+-# Copyright © 2020-2021 The Crust Firmware Authors.
+-# SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only
+-#
+-
+-menu "Interrupt and wakeup options"
+-
+-config IRQ_POLL_EINT
+-	bool "Poll the GPIO controller for EINT IRQs (DEPRECATED)"
+-	help
+-		Check the main GPIO controller (the one containing ports
+-		A through H) for external interrupts (EINTs) when
+-		polling for wakeup IRQs.
+-
+-		This allows EINT-capable pins on those ports to be used
+-		as wakeup sources. The pins must be configured as EINT
+-		pins by Linux before entering suspend.
+-
+-		Note: This option is not needed when using a Linux patch
+-		set released in 2021. The newer driver plumbs the EINT
+-		IRQs through to R_INTC.
+-
+-		Say Y if your board has a device connected to port A-H
+-		that must be able to wake up or turn on the system, and
+-		you are using an older kernel. Otherwise, say N.
+-
+-if IRQ_POLL_EINT
+-
+-config IRQ_POLL_EINT_FIRST_BANK
+-	int "First EINT bank to poll"
+-	range 0 7
+-	default 0
+-	help
+-		Begin the EINT polling loop at the nth EINT-capable GPIO
+-		bank, counting from 0. This number is not related to the
+-		GPIO bank letter.
+-
+-config IRQ_POLL_EINT_LAST_BANK
+-	int "Last EINT bank to poll"
+-	range 0 7
+-	default 2 if PLATFORM_A64
+-	default 2 if PLATFORM_A83T
+-	default 7 if PLATFORM_H6
+-	help
+-		End the EINT polling loop at the nth EINT-capable GPIO
+-		bank, counting from 0. This number is not related to the
+-		GPIO bank letter.
+-
+-endif
+-
+-endmenu
+diff --git a/drivers/irq/irq.c b/drivers/irq/irq.c
+index 85efcb32..ae675374 100644
+--- a/drivers/irq/irq.c
++++ b/drivers/irq/irq.c
+@@ -4,32 +4,7 @@
+  */
+ 
+ #include <irq.h>
+-#include <mmio.h>
+ #include <stdint.h>
+-#include <platform/devices.h>
+-
+-#include "irq.h"
+-
+-#define EINT_CTL_REG(n)    (0x20 * (n) + 0x0210)
+-#define EINT_STATUS_REG(n) (0x20 * (n) + 0x0214)
+-
+-uint32_t
+-irq_poll_eint(void)
+-{
+-	uint32_t pending = 0;
+-
+-#if CONFIG(IRQ_POLL_EINT)
+-	uint32_t first = CONFIG_IRQ_POLL_EINT_FIRST_BANK;
+-	uint32_t last  = CONFIG_IRQ_POLL_EINT_LAST_BANK;
+-
+-	for (uint32_t bank = first; bank <= last; ++bank) {
+-		pending |= mmio_read_32(DEV_PIO + EINT_CTL_REG(bank)) &
+-		           mmio_read_32(DEV_PIO + EINT_STATUS_REG(bank));
+-	}
+-#endif
+-
+-	return pending;
+-}
+ 
+ uint32_t WEAK
+ irq_needs_avcc(void)
+@@ -40,11 +15,11 @@ irq_needs_avcc(void)
+ uint32_t WEAK
+ irq_needs_vdd_sys(void)
+ {
+-	return CONFIG(IRQ_POLL_EINT);
++	return 0;
+ }
+ 
+ uint32_t WEAK
+ irq_poll(void)
+ {
+-	return irq_poll_eint();
++	return 0;
+ }
+diff --git a/drivers/irq/irq.h b/drivers/irq/irq.h
+deleted file mode 100644
+index 314329d5..00000000
+--- a/drivers/irq/irq.h
++++ /dev/null
+@@ -1,16 +0,0 @@
+-/*
+- * Copyright © 2021 The Crust Firmware Authors.
+- * SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only
+- */
+-
+-#ifndef IRQ_PRIVATE_H
+-#define IRQ_PRIVATE_H
+-
+-#include <stdint.h>
+-
+-/**
+- * Poll for interrupts from the main PIO controller's EINT pins.
+- */
+-uint32_t irq_poll_eint(void);
+-
+-#endif /* IRQ_PRIVATE_H */
+diff --git a/drivers/irq/sun6i-a31-r-intc.c b/drivers/irq/sun6i-a31-r-intc.c
+index 5cd56440..c140994e 100644
+--- a/drivers/irq/sun6i-a31-r-intc.c
++++ b/drivers/irq/sun6i-a31-r-intc.c
+@@ -79,7 +79,7 @@ irq_needs_avcc(void)
+ uint32_t
+ irq_needs_vdd_sys(void)
+ {
+-	uint32_t enabled = CONFIG(IRQ_POLL_EINT);
++	uint32_t enabled = 0;
+ 
+ 	/* Only read registers with relevant bits. */
+ 	for (int i = 0; i < NUM_MUX_REGS; ++i) {
+@@ -96,7 +96,7 @@ irq_needs_vdd_sys(void)
+ uint32_t
+ irq_poll(void)
+ {
+-	uint32_t pending = irq_poll_eint();
++	uint32_t pending = 0;
+ 
+ 	for (int i = 0; i < NUM_IRQ_REGS; ++i)
+ 		pending |= mmio_read_32(DEV_R_INTC + INTC_IRQ_PEND_REG(i));

main/crust/APKBUILD

 # Maintainer: Martijn Braam <martijn@brixit.nl>
 pkgname=crust
-pkgver=0.3_git20210418
+pkgver=0.4
 pkgrel=0
-_commit="23d6d7b4fbb5375845d96f622e82435064343098"
 pkgdesc="SCP firmware for sunxi SoCs"
 arch="aarch64"
 url="https://github.com/crust-firmware/crust"
 license="BSD-1-Clause AND BSD-3-Clause AND GPL-2.0-only and MIT"
 makedepends="gcc-or1k-elf binutils-or1k-elf dtc bison flex"
-source="https://github.com/crust-firmware/crust/archive/$_commit/crust-$_commit.tar.gz"
+source="https://github.com/crust-firmware/crust/archive/v$pkgver/crust-v$pkgver.tar.gz
+	0289a01c9ee211195728e14b4f26dd2e5226561a.patch"
 options="!check !archcheck !tracedeps pmb:cross-native" # No tests
-builddir="$srcdir/$pkgname-$_commit"
 
 build() {
 	make CROSS_COMPILE=or1k-elf- pinephone_defconfig
@@ -21,5 +20,6 @@ package() {
 	install -D -m644 build/scp/scp.bin "$pkgdir"/usr/share/crust/pinephone/scp.bin
 }
 sha512sums="
-15058a888f10b9434eea76951acd44010bc6628d911c9cbbf043d5b8c26a4d226d24cc6fda3698b093d7ccb055a6c047d146410ca4cd2d44040c622b6aad2568  crust-23d6d7b4fbb5375845d96f622e82435064343098.tar.gz
+c6cd3b001ed3573c1737d07e68871740ae5df152d3dcb33358378f8e91ef599f6141bc4fc8aa66d2bc6d9be510da927cfab389e36e9f7f25bdad02f778acac03  crust-v0.4.tar.gz
+3e9271a9c2850f2c8864502b2db19b9c42c8c336ee8b4e31077fdb11c7ccdabcc8353f13b2d58330a01c2aa574c08e315ec75685ba39689ec51900f9c001862f  0289a01c9ee211195728e14b4f26dd2e5226561a.patch
 "

main/postmarketos-ui-plasma-mobile/APKBUILD

 # Maintainer: Bart Ribbers <bribbers@disroot.org>
 pkgname=postmarketos-ui-plasma-mobile
 pkgver=3.3
-pkgrel=6
+pkgrel=7
 pkgdesc="(Wayland) Mobile variant of KDE Plasma (does not run without hardware acceleration, allows only numeric passwords!)"
 url="https://wiki.postmarketos.org/wiki/Plasma_Mobile"
 arch="noarch !armhf !x86" # armhf: pmaports#75, x86: aports#11807
@@ -17,16 +17,11 @@ depends="
 	kscreen
 	kwallet-pam
 	kwayland-integration
-	networkmanager
-	ofono
-	ofono-openrc
 	plasma-phone-components
-	plasma-nm-mobile
 	polkit-kde-agent-1
 	postmarketos-base-ui
 	powerdevil
 	pulseaudio
-	qt5-qtvirtualkeyboard
 	xdg-desktop-portal-kde
 	urfkill
 	urfkill-openrc

temp/arm-trusted-firmware-crust/APKBUILD

-# Forked for adding crust compatibility
-pkgname=arm-trusted-firmware-crust
-_pkgver=crust-20210410
-pkgver=20210410
-pkgrel=0
-pkgdesc="ARM Trusted Firmware-A (TF-A) with Crust compatibility"
-url="https://github.com/crust-firmware/arm-trusted-firmware/"
-arch="aarch64"
-license="BSD-3-Clause"
-makedepends="dtc openssl-dev gcc-arm-none-eabi"
-source="
-	$pkgname-$pkgver.tar.gz::https://github.com/crust-firmware/arm-trusted-firmware/archive/refs/tags/$_pkgver.tar.gz
-"
-options="!check" # No tests
-builddir="$srcdir/$pkgname-$pkgver"
-
-_plats="sun50i_a64 sun50i_h6"
-
-build() {
-	unset LDFLAGS
-	for plat in $_plats; do
-		make PLAT=$plat bl31
-	done
-}
-
-package() {
-	for plat in $_plats; do
-		install -D "$builddir"/build/$plat/release/bl31.bin \
-			"$pkgdir"/usr/share/crust/arm-trusted-firmware/$plat/bl31.bin
-	done
-}
-
-sha512sums="
-ecc69c60d35d5c116647c13067e425b75f46ce5753d0e518396a55dfa6e934ff16ccbc91349bcb6dbd55011e289afc8448e2b3da082e05a0fc757563e4605948  arm-trusted-firmware-crust-20210410.tar.gz
-"

temp/arm-trusted-firmware/0001-bl_common-Import-BL_NOBITS_-BASE-END-when-defined.patch

+From 6cb17b16dfd06e1ff17a097f743905ae507ceb20 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 13 Dec 2020 20:42:22 -0600
+Subject: [PATCH 1/8] bl_common: Import BL_NOBITS_{BASE,END} when defined
+
+If SEPARATE_NOBITS_REGION is enabled, the platform may need to map
+memory specifically for that region. Import the symbols from the linker
+script to allow the platform to do so.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Change-Id: Iaec4dee94a6735b22f58f7b61f18d53e7bc6ca8d
+---
+ include/common/bl_common.h | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/include/common/bl_common.h b/include/common/bl_common.h
+index 77fb1f679..e33840c9d 100644
+--- a/include/common/bl_common.h
++++ b/include/common/bl_common.h
+@@ -106,6 +106,10 @@ IMPORT_SYM(uintptr_t, __RODATA_END__,		BL_RO_DATA_END);
+ IMPORT_SYM(uintptr_t, __RO_START__,		BL_CODE_BASE);
+ IMPORT_SYM(uintptr_t, __RO_END__,		BL_CODE_END);
+ #endif
++#if SEPARATE_NOBITS_REGION
++IMPORT_SYM(uintptr_t, __NOBITS_START__,		BL_NOBITS_BASE);
++IMPORT_SYM(uintptr_t, __NOBITS_END__,		BL_NOBITS_END);
++#endif
+ IMPORT_SYM(uintptr_t, __RW_END__,		BL_END);
+ 
+ #if defined(IMAGE_BL1)
+-- 
+2.31.1
+

temp/arm-trusted-firmware/0002-allwinner-Rename-static-mmap-region-constant.patch

+From c6219d9997a6cf474ca45f53bc49c6436f2861d5 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 13 Dec 2020 21:26:36 -0600
+Subject: [PATCH 2/8] allwinner: Rename static mmap region constant
+
+This constant specifically refers to the number of static mmap regions.
+Rename it to make that clear.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Change-Id: I475c037777ce2a10db2631ec0e7446bb73590a36
+---
+ plat/allwinner/common/include/platform_def.h | 6 +++---
+ plat/allwinner/common/sunxi_common.c         | 4 ++--
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h
+index 4893368c2..fa0c0abfa 100644
+--- a/plat/allwinner/common/include/platform_def.h
++++ b/plat/allwinner/common/include/platform_def.h
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
++ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -52,7 +52,8 @@
+ #define CACHE_WRITEBACK_SHIFT		6
+ #define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+ 
+-#define MAX_MMAP_REGIONS		(3 + PLATFORM_MMAP_REGIONS)
++#define MAX_STATIC_MMAP_REGIONS		5
++#define MAX_MMAP_REGIONS		(3 + MAX_STATIC_MMAP_REGIONS)
+ 
+ #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
+ 	(SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200)
+@@ -72,7 +73,6 @@
+ #define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER_COUNT * \
+ 					 PLATFORM_MAX_CPUS_PER_CLUSTER)
+ #define PLATFORM_MAX_CPUS_PER_CLUSTER	U(4)
+-#define PLATFORM_MMAP_REGIONS		5
+ #define PLATFORM_STACK_SIZE		(0x1000 / PLATFORM_CORE_COUNT)
+ 
+ #ifndef SPD_none
+diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c
+index d47d3605b..9d1b3c1ea 100644
+--- a/plat/allwinner/common/sunxi_common.c
++++ b/plat/allwinner/common/sunxi_common.c
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
++ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -14,7 +14,7 @@
+ #include <sunxi_mmap.h>
+ #include <sunxi_private.h>
+ 
+-static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = {
++static const mmap_region_t sunxi_mmap[MAX_STATIC_MMAP_REGIONS + 1] = {
+ 	MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE,
+ 			MT_RW_DATA | MT_SECURE),
+ #ifdef SUNXI_SCP_BASE
+-- 
+2.31.1
+

temp/arm-trusted-firmware/0003-allwinner-Map-SRAM-as-device-memory-by-default.patch

+From 6db436c8bb62053a23e41a50216bde87ebba1872 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 13 Dec 2020 20:45:49 -0600
+Subject: [PATCH 3/8] allwinner: Map SRAM as device memory by default
+
+The SRAM on Allwinner platforms is shared between BL31 and coprocessor
+firmware. Previously, SRAM was mapped as normal memory by default.
+This scheme requires carveouts and cache maintenance code for proper
+synchronization with the coprocessor.
+
+A better scheme is to only map pages owned by BL31 as normal memory,
+and leave everything else as device memory. This removes the need for
+cache maintenance, and it makes the mapping for BL31 RW data explicit
+instead of magic.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Change-Id: I820ddeba2dfa2396361c2322308c0db51b55c348
+---
+ plat/allwinner/common/include/platform_def.h |  4 ++--
+ plat/allwinner/common/sunxi_common.c         | 16 ++++++++++++----
+ plat/allwinner/common/sunxi_scpi_pm.c        |  1 -
+ plat/allwinner/sun50i_a64/sunxi_power.c      |  1 -
+ 4 files changed, 14 insertions(+), 8 deletions(-)
+
+diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h
+index fa0c0abfa..e6ca6010f 100644
+--- a/plat/allwinner/common/include/platform_def.h
++++ b/plat/allwinner/common/include/platform_def.h
+@@ -52,8 +52,8 @@
+ #define CACHE_WRITEBACK_SHIFT		6
+ #define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+ 
+-#define MAX_STATIC_MMAP_REGIONS		5
+-#define MAX_MMAP_REGIONS		(3 + MAX_STATIC_MMAP_REGIONS)
++#define MAX_STATIC_MMAP_REGIONS		4
++#define MAX_MMAP_REGIONS		(5 + MAX_STATIC_MMAP_REGIONS)
+ 
+ #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
+ 	(SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200)
+diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c
+index 9d1b3c1ea..d60d767ae 100644
+--- a/plat/allwinner/common/sunxi_common.c
++++ b/plat/allwinner/common/sunxi_common.c
+@@ -16,11 +16,7 @@
+ 
+ static const mmap_region_t sunxi_mmap[MAX_STATIC_MMAP_REGIONS + 1] = {
+ 	MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE,
+-			MT_RW_DATA | MT_SECURE),
+-#ifdef SUNXI_SCP_BASE
+-	MAP_REGION_FLAT(SUNXI_SCP_BASE, SUNXI_SCP_SIZE,
+ 			MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
+-#endif
+ 	MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE,
+ 			MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
+ 	MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE,
+@@ -40,12 +36,24 @@ void sunxi_configure_mmu_el3(int flags)
+ 	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
+ 			BL_CODE_END - BL_CODE_BASE,
+ 			MT_CODE | MT_SECURE);
++	mmap_add_region(BL_CODE_END, BL_CODE_END,
++			BL_END - BL_CODE_END,
++			MT_RW_DATA | MT_SECURE);
++#if SEPARATE_CODE_AND_RODATA
+ 	mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
+ 			BL_RO_DATA_END - BL_RO_DATA_BASE,
+ 			MT_RO_DATA | MT_SECURE);
++#endif
++#if SEPARATE_NOBITS_REGION
++	mmap_add_region(BL_NOBITS_BASE, BL_NOBITS_BASE,
++			BL_NOBITS_END - BL_NOBITS_BASE,
++			MT_RW_DATA | MT_SECURE);
++#endif
++#if USE_COHERENT_MEM
+ 	mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
+ 			BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
+ 			MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER);
++#endif
+ 
+ 	mmap_add(sunxi_mmap);
+ 	init_xlat_tables();
+diff --git a/plat/allwinner/common/sunxi_scpi_pm.c b/plat/allwinner/common/sunxi_scpi_pm.c
+index 74763ef7e..eb37daa63 100644
+--- a/plat/allwinner/common/sunxi_scpi_pm.c
++++ b/plat/allwinner/common/sunxi_scpi_pm.c
+@@ -212,7 +212,6 @@ int sunxi_set_scpi_psci_ops(const plat_psci_ops_t **psci_ops)
+ 		uint32_t offset = SUNXI_SCP_BASE - vector;
+ 
+ 		mmio_write_32(vector, offset >> 2);
+-		clean_dcache_range(vector, sizeof(uint32_t));
+ 	}
+ 
+ 	/* Take the SCP out of reset. */
+diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c
+index 0fdb62d05..a35b9ddc0 100644
+--- a/plat/allwinner/sun50i_a64/sunxi_power.c
++++ b/plat/allwinner/sun50i_a64/sunxi_power.c
+@@ -244,7 +244,6 @@ void sunxi_cpu_power_off_self(void)
+ 	 * in instruction granularity (32 bits).
+ 	 */
+ 	mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4);
+-	clean_dcache_range(arisc_reset_vec, 4);
+ 
+ 	/* De-assert the arisc reset line to let it run. */
+ 	mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
+-- 
+2.31.1
+

temp/arm-trusted-firmware/0004-allwinner-Do-not-map-BL32-DRAM-at-EL3.patch

+From 9ac48782303b8e86c4fee7c52ae9a26e13e8005e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 13 Dec 2020 20:22:42 -0600
+Subject: [PATCH 4/8] allwinner: Do not map BL32 DRAM at EL3
+
+BL31 does not appear to ever access the DRAM allocated to BL32,
+so there is no need to map it at EL3.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Change-Id: Ie8727b793e53ea14517894942266f6da0333eb74
+---
+ plat/allwinner/common/include/platform_def.h | 8 +++-----
+ plat/allwinner/common/sunxi_common.c         | 2 --
+ 2 files changed, 3 insertions(+), 7 deletions(-)
+
+diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h
+index e6ca6010f..de44174b2 100644
+--- a/plat/allwinner/common/include/platform_def.h
++++ b/plat/allwinner/common/include/platform_def.h
+@@ -39,12 +39,10 @@
+ 
+ #define MAX_XLAT_TABLES			1
+ #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 28)
+-#define SUNXI_BL33_VIRT_BASE		(SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE)
+ 
+-#endif /* SUNXI_BL31_IN_DRAM */
++#define SUNXI_BL33_VIRT_BASE		SUNXI_DRAM_VIRT_BASE
+ 
+-/* How much memory to reserve as secure for BL32, if configured */
+-#define SUNXI_DRAM_SEC_SIZE		(32U << 20)
++#endif /* SUNXI_BL31_IN_DRAM */
+ 
+ /* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */
+ #define SUNXI_DRAM_MAP_SIZE		(64U << 20)
+@@ -52,7 +50,7 @@
+ #define CACHE_WRITEBACK_SHIFT		6
+ #define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+ 
+-#define MAX_STATIC_MMAP_REGIONS		4
++#define MAX_STATIC_MMAP_REGIONS		3
+ #define MAX_MMAP_REGIONS		(5 + MAX_STATIC_MMAP_REGIONS)
+ 
+ #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
+diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c
+index d60d767ae..82410b1ed 100644
+--- a/plat/allwinner/common/sunxi_common.c
++++ b/plat/allwinner/common/sunxi_common.c
+@@ -19,8 +19,6 @@ static const mmap_region_t sunxi_mmap[MAX_STATIC_MMAP_REGIONS + 1] = {
+ 			MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
+ 	MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE,
+ 			MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
+-	MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE,
+-		   MT_RW_DATA | MT_SECURE),
+ 	MAP_REGION(PRELOADED_BL33_BASE, SUNXI_BL33_VIRT_BASE,
+ 		   SUNXI_DRAM_MAP_SIZE, MT_RW_DATA | MT_NS),
+ 	{},
+-- 
+2.31.1
+

temp/arm-trusted-firmware/0005-allwinner-Clean-up-some-platform-definitions.patch

+From e55aedf8ec36f624ad66a8dd033cbccc7e661faf Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 4 Apr 2021 15:54:17 -0500
+Subject: [PATCH 5/8] allwinner: Clean up some platform definitions
+
+Group the SCP base/size definitions in a more logical location.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Change-Id: Id43f9b468d7d855a2413173d674a5ee666527808
+---
+ plat/allwinner/common/include/platform_def.h | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h
+index de44174b2..56a2ad6f7 100644
+--- a/plat/allwinner/common/include/platform_def.h
++++ b/plat/allwinner/common/include/platform_def.h
+@@ -13,9 +13,6 @@
+ 
+ #include <sunxi_mmap.h>
+ 
+-/* The SCP firmware is allocated the last 16KiB of SRAM A2. */
+-#define SUNXI_SCP_SIZE			0x4000
+-
+ #ifdef SUNXI_BL31_IN_DRAM
+ 
+ #define BL31_BASE			SUNXI_DRAM_BASE
+@@ -31,7 +28,6 @@
+ #define BL31_BASE			(SUNXI_SRAM_A2_BASE + 0x4000)
+ #define BL31_LIMIT			(SUNXI_SRAM_A2_BASE + \
+ 					 SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE)
+-#define SUNXI_SCP_BASE			BL31_LIMIT
+ 
+ /* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */
+ #define BL31_NOBITS_BASE		(SUNXI_SRAM_A1_BASE + 0x1000)
+@@ -42,6 +38,10 @@
+ 
+ #define SUNXI_BL33_VIRT_BASE		SUNXI_DRAM_VIRT_BASE
+ 
++/* The SCP firmware is allocated the last 16KiB of SRAM A2. */
++#define SUNXI_SCP_BASE			BL31_LIMIT
++#define SUNXI_SCP_SIZE			0x4000
++
+ #endif /* SUNXI_BL31_IN_DRAM */
+ 
+ /* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */
+-- 
+2.31.1
+

temp/arm-trusted-firmware/0006-allwinner-Choose-PSCI-states-to-avoid-translation.patch

+From 3029a8f36df1246f781a5d10776b05c5ea7f2867 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 18 Mar 2021 22:55:15 -0500
+Subject: [PATCH 6/8] allwinner: Choose PSCI states to avoid translation
+
+By aligning the PSCI and SCPI power states, we can avoid some code to
+translate between the two. This also makes room for a second retention
+state, for future growth.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Change-Id: I26691085f277a96bd405e3305ab0fe390a92b418
+---
+ plat/allwinner/common/include/platform_def.h |  7 ++++---
+ plat/allwinner/common/sunxi_scpi_pm.c        | 17 +++--------------
+ 2 files changed, 7 insertions(+), 17 deletions(-)
+
+diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h
+index 56a2ad6f7..d771e92fe 100644
+--- a/plat/allwinner/common/include/platform_def.h
++++ b/plat/allwinner/common/include/platform_def.h
+@@ -56,9 +56,10 @@
+ #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
+ 	(SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200)
+ 
+-#define PLAT_MAX_PWR_LVL_STATES		U(2)
+-#define PLAT_MAX_RET_STATE		U(1)
+-#define PLAT_MAX_OFF_STATE		U(2)
++/* These states are used directly for SCPI communication. */
++#define PLAT_MAX_PWR_LVL_STATES		U(3)
++#define PLAT_MAX_RET_STATE		U(2)
++#define PLAT_MAX_OFF_STATE		U(3)
+ 
+ #define PLAT_MAX_PWR_LVL		U(2)
+ #define PLAT_NUM_PWR_DOMAINS		(U(1) + \
+diff --git a/plat/allwinner/common/sunxi_scpi_pm.c b/plat/allwinner/common/sunxi_scpi_pm.c
+index eb37daa63..ed1363537 100644
+--- a/plat/allwinner/common/sunxi_scpi_pm.c
++++ b/plat/allwinner/common/sunxi_scpi_pm.c
+@@ -44,17 +44,6 @@
+ #define SYSTEM_PWR_STATE(state) \
+ 	((state)->pwr_domain_state[SYSTEM_PWR_LVL])
+ 
+-static inline scpi_power_state_t scpi_map_state(plat_local_state_t psci_state)
+-{
+-	if (is_local_state_run(psci_state)) {
+-		return scpi_power_on;
+-	}
+-	if (is_local_state_retn(psci_state)) {
+-		return scpi_power_retention;
+-	}
+-	return scpi_power_off;
+-}
+-
+ static void sunxi_cpu_standby(plat_local_state_t cpu_state)
+ {
+ 	u_register_t scr = read_scr_el3();
+@@ -87,9 +76,9 @@ static void sunxi_pwr_domain_off(const psci_power_state_t *target_state)
+ 	}
+ 
+ 	scpi_set_css_power_state(read_mpidr(),
+-				 scpi_map_state(cpu_pwr_state),
+-				 scpi_map_state(cluster_pwr_state),
+-				 scpi_map_state(system_pwr_state));
++				 cpu_pwr_state,
++				 cluster_pwr_state,
++				 system_pwr_state);
+ }
+ 
+ static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state)
+-- 
+2.31.1
+

temp/arm-trusted-firmware/0007-allwinner-Simplify-CPU_SUSPEND-power-state-encoding.patch

+From 3b6ea6c08a365ada6e70c9ccc724cd7eb8729d31 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 18 Mar 2021 23:15:28 -0500
+Subject: [PATCH 7/8] allwinner: Simplify CPU_SUSPEND power state encoding
+
+Use the encoding recommended by the PSCI specification: four bits for
+the power state at each power level.
+
+Since SCPI provides no way to handshake an exit from a standby state,
+the only possible standby state is the architectural WFI state. Since
+WFI can be used without PSCI, we do not allow passing in standby states.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Change-Id: I4b3b84e5c255ee58a25255a0cab5d7623425086e
+---
+ plat/allwinner/common/sunxi_scpi_pm.c | 36 ++++++++++++---------------
+ 1 file changed, 16 insertions(+), 20 deletions(-)
+
+diff --git a/plat/allwinner/common/sunxi_scpi_pm.c b/plat/allwinner/common/sunxi_scpi_pm.c
+index ed1363537..41dc56397 100644
+--- a/plat/allwinner/common/sunxi_scpi_pm.c
++++ b/plat/allwinner/common/sunxi_scpi_pm.c
+@@ -33,6 +33,9 @@
+  */
+ #define SCP_FIRMWARE_MAGIC		0xb4400012
+ 
++#define PLAT_LOCAL_PSTATE_WIDTH		U(4)
++#define PLAT_LOCAL_PSTATE_MASK		((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1)
++
+ #define CPU_PWR_LVL			MPIDR_AFFLVL0
+ #define CLUSTER_PWR_LVL			MPIDR_AFFLVL1
+ #define SYSTEM_PWR_LVL			MPIDR_AFFLVL2
+@@ -126,7 +129,9 @@ static int sunxi_validate_power_state(unsigned int power_state,
+ 				      psci_power_state_t *req_state)
+ {
+ 	unsigned int power_level = psci_get_pstate_pwrlvl(power_state);
++	unsigned int state_id = psci_get_pstate_id(power_state);
+ 	unsigned int type = psci_get_pstate_type(power_state);
++	unsigned int i;
+ 
+ 	assert(req_state != NULL);
+ 
+@@ -135,28 +140,19 @@ static int sunxi_validate_power_state(unsigned int power_state,
+ 	}
+ 
+ 	if (type == PSTATE_TYPE_STANDBY) {
+-		/* Only one retention power state is supported. */
+-		if (psci_get_pstate_id(power_state) > 0) {
+-			return PSCI_E_INVALID_PARAMS;
+-		}
+-		/* The SoC cannot be suspended without losing state */
+-		if (power_level == SYSTEM_PWR_LVL) {
+-			return PSCI_E_INVALID_PARAMS;
+-		}
+-		for (unsigned int i = 0; i <= power_level; ++i) {
+-			req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE;
+-		}
+-	} else {
+-		/* Only one off power state is supported. */
+-		if (psci_get_pstate_id(power_state) > 0) {
+-			return PSCI_E_INVALID_PARAMS;
+-		}
+-		for (unsigned int i = 0; i <= power_level; ++i) {
+-			req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
+-		}
++		return PSCI_E_INVALID_PARAMS;
++	}
++
++	/* Pass through the requested PSCI state as-is. */
++	for (i = 0; i <= power_level; ++i) {
++		unsigned int local_pstate = state_id & PLAT_LOCAL_PSTATE_MASK;
++
++		req_state->pwr_domain_state[i] = local_pstate;
++		state_id >>= PLAT_LOCAL_PSTATE_WIDTH;
+ 	}
++
+ 	/* Higher power domain levels should all remain running */
+-	for (unsigned int i = power_level + 1; i <= PLAT_MAX_PWR_LVL; ++i) {
++	for (; i <= PLAT_MAX_PWR_LVL; ++i) {
+ 		req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN;
+ 	}
+ 
+-- 
+2.31.1
+

temp/arm-trusted-firmware/APKBUILD

-# Forked for adding rk3399 support
+# Forked for adding rk3399, rk3328 support and crust compatibility
 pkgname=arm-trusted-firmware
 pkgver=9999
 _pkgver=2.5
-pkgrel=4
+pkgrel=5
 pkgdesc="ARM Trusted Firmware-A (TF-A)"
 url="https://github.com/ARM-software/arm-trusted-firmware"
 arch="aarch64"
 license="BSD-3-Clause"
 makedepends="dtc openssl-dev gcc-arm-none-eabi"
-options="!check" # No tests
+source="
+	$pkgname-$_pkgver.tar.gz::https://github.com/ARM-software/$pkgname/archive/v$_pkgver.tar.gz
+	rk3399-baudrate.patch
+	0001-bl_common-Import-BL_NOBITS_-BASE-END-when-defined.patch
+	0002-allwinner-Rename-static-mmap-region-constant.patch
+	0003-allwinner-Map-SRAM-as-device-memory-by-default.patch
+	0004-allwinner-Do-not-map-BL32-DRAM-at-EL3.patch
+	0005-allwinner-Clean-up-some-platform-definitions.patch
+	0006-allwinner-Choose-PSCI-states-to-avoid-translation.patch
+	0007-allwinner-Simplify-CPU_SUSPEND-power-state-encoding.patch
+"
+options="!check" # no tests
 builddir="$srcdir/$pkgname-$_pkgver"
-source="https://github.com/ARM-software/arm-trusted-firmware/archive/v$_pkgver/arm-trusted-firmware-v$_pkgver.tar.gz
-	rk3399-baudrate.patch"
-options="!check" # No tests
-
 _plats="sun50i_a64 sun50i_h6 rk3399 rk3328"
 
 build() {
 	unset LDFLAGS
 	for plat in $_plats; do
-		make PLAT=$plat bl31
+		make PLAT=$plat DEBUG=0 bl31
 	done
 }
 
@@ -38,8 +45,15 @@ package() {
 	done
 }
 
+
 sha512sums="
-3c99f1d849c3c536e8e2e4838ee48a1a431f0bef35eaf27eb14f9caebde71a577589b10efbbd7db49bed3b9763bed46583d0b26e72f61fcd0d34cc46ff684846  arm-trusted-firmware-v2.5.tar.gz
+3c99f1d849c3c536e8e2e4838ee48a1a431f0bef35eaf27eb14f9caebde71a577589b10efbbd7db49bed3b9763bed46583d0b26e72f61fcd0d34cc46ff684846  arm-trusted-firmware-2.5.tar.gz
 86d8c60157145ab05e9b870aad11d2acaf2137ba00bf71419f8a54a4fd2b1906c19bc8bfeccc735344d1dcf11ba81bd9396bfd8854cdb972a72503b632d1e900  rk3399-baudrate.patch
+b1b36fd5219c608500f763bc784cb52349c7c3344273483594672bb1917ede21f2dd09ec37a383f39fca39b05b7a29fadbbeecfde1ae4f31319277f6561c2fbb  0001-bl_common-Import-BL_NOBITS_-BASE-END-when-defined.patch
+2b0e3d879a8e08301288a1eb233640e9366e107b621fa4a92a358b0b3aa4beaa68d1bb1f5b0d4bc7013369aa08d0f9a360e77c8b027daa40a4d2438fe804dde3  0002-allwinner-Rename-static-mmap-region-constant.patch
+fe2c975c2b5bbc583427be1ef4b2c3c901b22d8044eecf7058b3dcd9167710a40500dbfa12986c8010c9030b4a580dd62a772a76262010ddb4dc2b310f28721c  0003-allwinner-Map-SRAM-as-device-memory-by-default.patch
+f3c7c97a014939e09a3161a4ffd01ce2d7e1eb9f0556dc67a4e8c62fc95ec469d5c51b74279e373b0d411b6c6f8c3dd097901bdaace1750745d6ac66a6b61dac  0004-allwinner-Do-not-map-BL32-DRAM-at-EL3.patch
+b5848397f552b19c427e1675e2054e3ade8d7957df9e4e03c5dad1dcaa47bbfea8061374917250ecf6a83ba9fe9fd2dd273ee10d47abea1cf35e8c375a701165  0005-allwinner-Clean-up-some-platform-definitions.patch
+b37e0763182abaec1892d70ac8bfcf468185c0095749c96df3541cce7612be55b99f8c6fc51c2c2465db6d3b7d779ed08fe2da2dfa20c8e002c0cff8c2df33d9  0006-allwinner-Choose-PSCI-states-to-avoid-translation.patch
+341d51db93fed9c1ae8e7c295d00f9e021333485a70dc823b5729ed7ee84ddb1feb272b2ec9470ee06cc1df93da638eb84a10baf0f4cc1b24a48033ac97eaf5f  0007-allwinner-Simplify-CPU_SUSPEND-power-state-encoding.patch
 "
-

temp/u-boot-pinebookpro/APKBUILD

@@ -2,7 +2,7 @@
 # a driver for the display and supports efi loading operating systems
 pkgname=u-boot-pinebookpro
 pkgver=2020.07
-pkgrel=2
+pkgrel=3
 pkgdesc="u-boot bootloader for the rk3399"
 url="https://gitlab.denx.de/u-boot/u-boot"
 arch="aarch64"

temp/u-boot-pinephone/0001-mmc-sunxi-Avoid-ifdefs-in-delay-and-width-setup.patch

+From af0ac30c08414e65f299149285dc81de664fc3f0 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Fri, 18 Dec 2020 22:02:11 +0000
+Subject: [PATCH 01/29] mmc: sunxi: Avoid #ifdefs in delay and width setup
+
+The delay and bus-width setup are slightly different across the
+Allwinner SoC generations, and we covered this so far with some
+preprocessor conditionals.
+
+Use the more readable IS_ENABLE() instead.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/mmc/sunxi_mmc.c | 33 +++++++++++++++------------------
+ 1 file changed, 15 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
+index 3503ccdb2e..87b79fcf5e 100644
+--- a/drivers/mmc/sunxi_mmc.c
++++ b/drivers/mmc/sunxi_mmc.c
+@@ -156,23 +156,19 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
+ 	} else if (hz <= 25000000) {
+ 		oclk_dly = 0;
+ 		sclk_dly = 5;
+-#ifdef CONFIG_MACH_SUN9I
+-	} else if (hz <= 52000000) {
+-		oclk_dly = 5;
+-		sclk_dly = 4;
+-	} else {
+-		/* hz > 52000000 */
+-		oclk_dly = 2;
+-		sclk_dly = 4;
+-#else
+-	} else if (hz <= 52000000) {
+-		oclk_dly = 3;
+-		sclk_dly = 4;
+ 	} else {
+-		/* hz > 52000000 */
+-		oclk_dly = 1;
++		if (IS_ENABLED(CONFIG_MACH_SUN9I)) {
++			if (hz <= 52000000)
++				oclk_dly = 5;
++			else
++				oclk_dly = 2;
++		} else {
++			if (hz <= 52000000)
++				oclk_dly = 3;
++			else
++				oclk_dly = 1;
++		}
+ 		sclk_dly = 4;
+-#endif
+ 	}
+ 
+ 	if (new_mode) {
+@@ -521,10 +517,11 @@ struct mmc *sunxi_mmc_init(int sdc_no)
+ 
+ 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+ 	cfg->host_caps = MMC_MODE_4BIT;
+-#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_SUN50I_GEN_H6)
+-	if (sdc_no == 2)
++
++	if ((IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN8I) ||
++	    IS_ENABLED(CONFIG_SUN50I_GEN_H6)) && (sdc_no == 2))
+ 		cfg->host_caps = MMC_MODE_8BIT;
+-#endif
++
+ 	cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+ 
+-- 
+2.31.1
+

temp/u-boot-pinephone/0002-mmc-sunxi-Fix-warnings-with-CONFIG_PHYS_64BIT.patch

+From 43e334d01e4ffb3d536bee35d8eeb57a2e0c497f Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Thu, 29 Apr 2021 09:31:58 +0100
+Subject: [PATCH 02/29] mmc: sunxi: Fix warnings with CONFIG_PHYS_64BIT
+
+When enabling PHYS_64BIT on 32-bit platforms, we get two warnings about
+pointer casts in sunxi_mmc.c. Those are related to MMIO addresses, which
+are always below 1GB on all Allwinner SoCs, so there is no problem with
+anything having more than 32 bits.
+
+Add the proper casts to make it compile cleanly.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/mmc/sunxi_mmc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
+index 87b79fcf5e..869af993d3 100644
+--- a/drivers/mmc/sunxi_mmc.c
++++ b/drivers/mmc/sunxi_mmc.c
+@@ -631,14 +631,14 @@ static int sunxi_mmc_probe(struct udevice *dev)
+ 	cfg->f_min = 400000;
+ 	cfg->f_max = 52000000;
+ 
+-	priv->reg = (void *)dev_read_addr(dev);
++	priv->reg = dev_read_addr_ptr(dev);
+ 
+ 	/* We don't have a sunxi clock driver so find the clock address here */
+ 	ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
+ 					  1, &args);
+ 	if (ret)
+ 		return ret;
+-	ccu_reg = (u32 *)ofnode_get_addr(args.node);
++	ccu_reg = (u32 *)(uintptr_t)ofnode_get_addr(args.node);
+ 
+ 	priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
+ 	priv->mclkreg = (void *)ccu_reg + get_mclk_offset() + priv->mmc_no * 4;
+-- 
+2.31.1
+

temp/u-boot-pinephone/0003-mmc-sunxi-Fix-MMC-clock-parent-selection.patch

+From 8bd521470df1cb6324520babf9d3a2e96bc7b96e Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Wed, 5 May 2021 09:57:47 +0100
+Subject: [PATCH 03/29] mmc: sunxi: Fix MMC clock parent selection
+
+Most Allwinner SoCs which use the so called "new timing mode" in their
+MMC controllers actually use the double-rate PLL6/PERIPH0 clock as their
+parent input clock. This is interestingly enough compensated by a hidden
+"by 2" post-divider in the mod clock, so the divider and actual output
+rate stay the same.
+
+Even though for the H6 and H616 (but only for them!) we use the doubled
+input clock for the divider computation, we never accounted for the
+implicit post-divider, so the clock was only half the speed on those SoCs.
+
+Clean up the code around that selection, to always use the normal PLL6
+(PERIPH0(1x)) clock as an input. As the rate and divider are the same,
+that makes no difference.
+Explain the hardware differences in a comment.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h |  2 +-
+ drivers/mmc/sunxi_mmc.c                           | 10 +++++++---
+ 2 files changed, 8 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+index 62abfc4ef6..e000f78ff4 100644
+--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
++++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+@@ -326,7 +326,7 @@ struct sunxi_ccm_reg {
+ #define CCM_MMC_CTRL_M(x)		((x) - 1)
+ #define CCM_MMC_CTRL_N(x)		((x) << 8)
+ #define CCM_MMC_CTRL_OSCM24		(0x0 << 24)
+-#define CCM_MMC_CTRL_PLL6X2		(0x1 << 24)
++#define CCM_MMC_CTRL_PLL6		(0x1 << 24)
+ #define CCM_MMC_CTRL_PLL_PERIPH2X2	(0x2 << 24)
+ #define CCM_MMC_CTRL_ENABLE		(0x1 << 31)
+ /* H6 doesn't have these delays */
+diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
+index 869af993d3..bc68debdad 100644
+--- a/drivers/mmc/sunxi_mmc.c
++++ b/drivers/mmc/sunxi_mmc.c
+@@ -124,10 +124,14 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
+ #ifdef CONFIG_MACH_SUN9I
+ 		pll = CCM_MMC_CTRL_PLL_PERIPH0;
+ 		pll_hz = clock_get_pll4_periph0();
+-#elif defined(CONFIG_SUN50I_GEN_H6)
+-		pll = CCM_MMC_CTRL_PLL6X2;
+-		pll_hz = clock_get_pll6() * 2;
+ #else
++		/*
++		 * SoCs since the A64 (H5, H6, H616) actually use the doubled
++		 * rate of PLL6/PERIPH0 as an input clock, but compensate for
++		 * that with a fixed post-divider of 2 in the mod clock.
++		 * This cancels each other out, so for simplicity we just
++		 * pretend it's always PLL6 without a post divider here.
++		 */
+ 		pll = CCM_MMC_CTRL_PLL6;
+ 		pll_hz = clock_get_pll6();
+ #endif
+-- 
+2.31.1
+

temp/u-boot-pinephone/0004-mmc-sunxi-Cleanup-new-timing-mode-selection.patch

+From b8e83c3840068beb42ca821e20aaaa82369b84bc Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Wed, 5 May 2021 09:57:47 +0100
+Subject: [PATCH 04/29] mmc: sunxi: Cleanup "new timing mode" selection
+
+Among the SoCs using the "new timing mode", only the A83T needs to
+explicitly switch to that mode.
+
+By just defining the symbol for that one odd A83T bit to 0 for any other
+SoCs, we can always OR that in, and save the confusing nested #ifdefs.
+
+Clean up the also confusing new_mode setting on the way.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/mmc/sunxi_mmc.c | 15 ++++++---------
+ 1 file changed, 6 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
+index bc68debdad..33cedb4edb 100644
+--- a/drivers/mmc/sunxi_mmc.c
++++ b/drivers/mmc/sunxi_mmc.c
+@@ -23,6 +23,10 @@
+ #include <asm-generic/gpio.h>
+ #include <linux/delay.h>
+ 
++#ifndef CCM_MMC_CTRL_MODE_SEL_NEW
++#define CCM_MMC_CTRL_MODE_SEL_NEW	0
++#endif
++
+ struct sunxi_mmc_plat {
+ 	struct mmc_config cfg;
+ 	struct mmc mmc;
+@@ -102,13 +106,10 @@ static int mmc_resource_init(int sdc_no)
+ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
+ {
+ 	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
+-	bool new_mode = true;
++	bool new_mode = IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE);
+ 	bool calibrate = false;
+ 	u32 val = 0;
+ 
+-	if (!IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))
+-		new_mode = false;
+-
+ 	/* A83T support new mode only on eMMC */
+ 	if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
+ 		new_mode = false;
+@@ -176,12 +177,8 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
+ 	}
+ 
+ 	if (new_mode) {
+-#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
+-#ifdef CONFIG_MMC_SUNXI_HAS_MODE_SWITCH
+-		val = CCM_MMC_CTRL_MODE_SEL_NEW;
+-#endif
++		val |= CCM_MMC_CTRL_MODE_SEL_NEW;
+ 		setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
+-#endif
+ 	} else if (!calibrate) {
+ 		/*
+ 		 * Use hardcoded delay values if controller doesn't support
+-- 
+2.31.1
+

temp/u-boot-pinephone/0005-mmc-sunxi-Enable-new-timing-mode-on-all-new-SoCs.patch

+From 5f2f7a0ed7346c3369cd22348c372892e903c60e Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Wed, 5 May 2021 10:04:41 +0100
+Subject: [PATCH 05/29] mmc: sunxi: Enable "new timing mode" on all new SoCs
+
+All SoCs since the Allwinner A64 (H5, H6, R40, H616) feature to so
+called "new timing mode", so enable this in Kconfig for those SoCs.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ arch/arm/mach-sunxi/Kconfig | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
+index 8e9012dbbf..e22a9c9103 100644
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -152,6 +152,7 @@ config SUN50I_GEN_H6
+ 	bool
+ 	select FIT
+ 	select SPL_LOAD_FIT
++	select MMC_SUNXI_HAS_NEW_MODE
+ 	select SUPPORT_SPL
+ 	---help---
+ 	Select this for sunxi SoCs which have H6 like peripherals, clocks
+@@ -297,6 +298,7 @@ config MACH_SUN8I_R40
+ 	select CPU_V7_HAS_VIRT
+ 	select ARCH_SUPPORT_PSCI
+ 	select SUNXI_GEN_SUN6I
++	select MMC_SUNXI_HAS_NEW_MODE
+ 	select SUPPORT_SPL
+ 	select SUNXI_DRAM_DW
+ 	select SUNXI_DRAM_DW_32BIT
+@@ -346,6 +348,7 @@ config MACH_SUN50I_H5
+ 	bool "sun50i (Allwinner H5)"
+ 	select ARM64
+ 	select MACH_SUNXI_H3_H5
++	select MMC_SUNXI_HAS_NEW_MODE
+ 	select FIT
+ 	select SPL_LOAD_FIT
+ 
+-- 
+2.31.1
+

temp/u-boot-pinephone/0006-mmc-sunxi-Cleanup-and-fix-self-calibration-code.patch

+From 0c12222a222529e46589eb2ea147d0e62ee4b838 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Wed, 5 May 2021 10:06:24 +0100
+Subject: [PATCH 06/29] mmc: sunxi: Cleanup and fix self-calibration code
+
+Newer SoCs have a self calibration feature, which avoids us writing hard
+coded phase delay values into the controller.
+
+Consolidate the code by avoiding unnecessary #ifdefs, and also enabling
+the feature for all those newer SoCs.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/mmc/sunxi_mmc.c | 27 +++++++++++++++++++--------
+ 1 file changed, 19 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
+index 33cedb4edb..a30fd8fbdb 100644
+--- a/drivers/mmc/sunxi_mmc.c
++++ b/drivers/mmc/sunxi_mmc.c
+@@ -103,21 +103,29 @@ static int mmc_resource_init(int sdc_no)
+ }
+ #endif
+ 
++/*
++ * All A64 and later MMC controllers feature auto-calibration. This would
++ * normally be detected via the compatible string, but we need something
++ * which works in the SPL as well.
++ */
++static bool sunxi_mmc_can_calibrate(void)
++{
++	return IS_ENABLED(CONFIG_MACH_SUN50I) ||
++	       IS_ENABLED(CONFIG_MACH_SUN50I_H5) ||
++	       IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
++	       IS_ENABLED(CONFIG_MACH_SUN8I_R40);
++}
++
+ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
+ {
+ 	unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
+ 	bool new_mode = IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE);
+-	bool calibrate = false;
+ 	u32 val = 0;
+ 
+ 	/* A83T support new mode only on eMMC */
+ 	if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
+ 		new_mode = false;
+ 
+-#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_SUN50I_GEN_H6)
+-	calibrate = true;
+-#endif
+-
+ 	if (hz <= 24000000) {
+ 		pll = CCM_MMC_CTRL_OSCM24;
+ 		pll_hz = 24000000;
+@@ -179,7 +187,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
+ 	if (new_mode) {
+ 		val |= CCM_MMC_CTRL_MODE_SEL_NEW;
+ 		setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
+-	} else if (!calibrate) {
++	}
++
++	if (!sunxi_mmc_can_calibrate()) {
+ 		/*
+ 		 * Use hardcoded delay values if controller doesn't support
+ 		 * calibration
+@@ -237,14 +247,15 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
+ 	rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
+ 	writel(rval, &priv->reg->clkcr);
+ 
+-#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_SUN50I_GEN_H6)
++#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+ 	/* A64 supports calibration of delays on MMC controller and we
+ 	 * have to set delay of zero before starting calibration.
+ 	 * Allwinner BSP driver sets a delay only in the case of
+ 	 * using HS400 which is not supported by mainline U-Boot or
+ 	 * Linux at the moment
+ 	 */
+-	writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
++	if (sunxi_mmc_can_calibrate())
++		writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
+ #endif
+ 
+ 	/* Re-enable Clock */
+-- 
+2.31.1
+

temp/u-boot-pinephone/0007-mmc-sunxi-Increase-MMIO-FIFO-read-performance.patch

+From 570ba1826f2962f63168e9b65aa5620956234901 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Wed, 5 May 2021 11:33:40 +0100
+Subject: [PATCH 07/29] mmc: sunxi: Increase MMIO FIFO read performance
+
+To avoid the complexity of DMA operations (with chained descriptors), we
+use repeated MMIO reads and writes to the SD_FIFO_REG, which allows us
+to drain or fill the MMC data buffer FIFO very easily.
+
+However those MMIO accesses are somewhat costly, so this limits our MMC
+performance, to around 20MB/s on most SoCs, but down to 10MB/s on others
+(H6, partly due to the lower AHB1 frequency).
+
+As it turns out we read the FIFO status register after *every* word we
+read or write, which effectively doubles the number of MMIO accesses,
+thus effectively more than halving our performance.
+
+To avoid this overhead, we can make use of the FIFO level bits, which are
+in the very same FIFO status registers.
+So for a read request, we now can collect as many words as the FIFO
+level originally indicated, and only then need to update the status
+register.
+
+We don't know for sure the size of the FIFO (and it seems to differ
+across SoCs anyway), so writing is more fragile, which is why we still
+use the old method for that. If we find a minimum FIFO size available on
+all SoCs, we could use that, in a later optimisation.
+
+This patch increases the eMMC read speed on a Pine64-LTS from about
+21MB/s to 43 MB/s. SD card reads increase slightly from about 20MB/s to
+23MB/s, which is the practical limit for a 3.3V SD card anyway.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ arch/arm/include/asm/arch-sunxi/mmc.h |  1 +
+ drivers/mmc/sunxi_mmc.c               | 39 +++++++++++++++++++++------
+ 2 files changed, 32 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
+index 340e25b04d..5daacf10eb 100644
+--- a/arch/arm/include/asm/arch-sunxi/mmc.h
++++ b/arch/arm/include/asm/arch-sunxi/mmc.h
+@@ -119,6 +119,7 @@ struct sunxi_mmc {
+ #define SUNXI_MMC_STATUS_CARD_PRESENT		(0x1 << 8)
+ #define SUNXI_MMC_STATUS_CARD_DATA_BUSY		(0x1 << 9)
+ #define SUNXI_MMC_STATUS_DATA_FSM_BUSY		(0x1 << 10)
++#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg)	(((reg) >> 17) & 0x3fff)
+ 
+ #define SUNXI_MMC_NTSR_MODE_SEL_NEW		(0x1 << 31)
+ 
+diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
+index a30fd8fbdb..ce085c69f5 100644
+--- a/drivers/mmc/sunxi_mmc.c
++++ b/drivers/mmc/sunxi_mmc.c
+@@ -311,8 +311,9 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
+ 					      SUNXI_MMC_STATUS_FIFO_FULL;
+ 	unsigned i;
+ 	unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
+-	unsigned byte_cnt = data->blocksize * data->blocks;
+-	unsigned timeout_msecs = byte_cnt >> 8;
++	unsigned word_cnt = (data->blocksize * data->blocks) >> 2;
++	unsigned timeout_msecs = word_cnt >> 6;
++	uint32_t status;
+ 	unsigned long  start;
+ 
+ 	if (timeout_msecs < 2000)
+@@ -323,16 +324,38 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
+ 
+ 	start = get_timer(0);
+ 
+-	for (i = 0; i < (byte_cnt >> 2); i++) {
+-		while (readl(&priv->reg->status) & status_bit) {
++	for (i = 0; i < word_cnt;) {
++		unsigned int in_fifo;
++
++		while ((status = readl(&priv->reg->status)) & status_bit) {
+ 			if (get_timer(start) > timeout_msecs)
+ 				return -1;
+ 		}
+ 
+-		if (reading)
+-			buff[i] = readl(&priv->reg->fifo);
+-		else
+-			writel(buff[i], &priv->reg->fifo);
++		/*
++		 * For writing we do not easily know the FIFO size, so have
++		 * to check the FIFO status after every word written.
++		 * TODO: For optimisation we could work out a minimum FIFO
++		 * size across all SoCs, and use that together with the current
++		 * fill level to write chunks for words.
++		 */
++		if (!reading) {
++			writel(buff[i++], &priv->reg->fifo);
++			continue;
++		}
++
++		/*
++		 * The status register holds the current FIFO level, so we
++		 * can be sure to collect as many words from the FIFO
++		 * register without checking the status register after every
++		 * read. That saves half of the costly MMIO reads, effectively
++		 * doubling the read performance.
++		 */
++		for (in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status);
++		     in_fifo > 0;
++		     in_fifo--)
++			buff[i++] = readl_relaxed(&priv->reg->fifo);
++		dmb();
+ 	}
+ 
+ 	return 0;
+-- 
+2.31.1
+