drm/msm/dpu: populate has_active_ctls in the catalog

Set the has_active_ctls for all the platforms which need this bit.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

@@ -14,6 +14,7 @@ static const struct dpu_caps sm8150_dpu_caps = {
 	.has_dim_layer = true,
 	.has_idle_pc = true,
 	.has_3d_merge = true,
+	.has_active_ctls = true,
 	.max_linewidth = 4096,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 	.max_hdeci_exp = MAX_HORZ_DECIMATION,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

@@ -14,6 +14,7 @@ static const struct dpu_caps sc8180x_dpu_caps = {
 	.has_dim_layer = true,
 	.has_idle_pc = true,
 	.has_3d_merge = true,
+	.has_active_ctls = true,
 	.max_linewidth = 4096,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 	.max_hdeci_exp = MAX_HORZ_DECIMATION,

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

@@ -14,6 +14,7 @@ static const struct dpu_caps sm8250_dpu_caps = {
 	.has_dim_layer = true,
 	.has_idle_pc = true,
 	.has_3d_merge = true,
+	.has_active_ctls = true,
 	.max_linewidth = 4096,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h

@@ -12,6 +12,7 @@ static const struct dpu_caps sc7180_dpu_caps = {
 	.max_mixer_blendstages = 0x9,
 	.has_dim_layer = true,
 	.has_idle_pc = true,
+	.has_active_ctls = true,
 	.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h

@@ -12,6 +12,7 @@ static const struct dpu_caps sm6115_dpu_caps = {
 	.max_mixer_blendstages = 0x4,
 	.has_dim_layer = true,
 	.has_idle_pc = true,
+	.has_active_ctls = true,
 	.max_linewidth = 2160,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h

@@ -12,6 +12,7 @@ static const struct dpu_caps qcm2290_dpu_caps = {
 	.max_mixer_blendstages = 0x4,
 	.has_dim_layer = true,
 	.has_idle_pc = true,
+	.has_active_ctls = true,
 	.max_linewidth = 2160,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

@@ -14,6 +14,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
 	.has_dim_layer = true,
 	.has_idle_pc = true,
 	.has_3d_merge = true,
+	.has_active_ctls = true,
 	.max_linewidth = 4096,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h

@@ -12,6 +12,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
 	.max_mixer_blendstages = 0x7,
 	.has_dim_layer = true,
 	.has_idle_pc = true,
+	.has_active_ctls = true,
 	.max_linewidth = 2400,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

@@ -14,6 +14,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
 	.has_dim_layer = true,
 	.has_idle_pc = true,
 	.has_3d_merge = true,
+	.has_active_ctls = true,
 	.max_linewidth = 5120,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

@@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
 	.has_dim_layer = true,
 	.has_idle_pc = true,
 	.has_3d_merge = true,
+	.has_active_ctls = true,
 	.max_linewidth = 5120,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };

drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

@@ -14,6 +14,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
 	.has_dim_layer = true,
 	.has_idle_pc = true,
 	.has_3d_merge = true,
+	.has_active_ctls = true,
 	.max_linewidth = 5120,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };