community/linux-google-veyron: upgrade to 6.6.74 (MR 6201)

Upgrading from the old LTS (6.1.y) to the latest LTS (6.6.y) version.
Kept most of the defaults, except where the current/previous config dictated another logical decision.

device/community/linux-google-veyron/APKBUILD

-# Maintainer: Jenneron <jenneron@protonmail.com>
+# Maintainer: Daniel Fancsali <fancsali@gmail.com>
+# Contributor: Jenneron <jenneron@protonmail.com>
 pkgname=linux-google-veyron
-pkgver=6.1.39
-pkgrel=7
+pkgver=6.6.74
+pkgrel=0
 pkgdesc="Mainline kernel for Google Veyron devices"
 arch="armv7"
 _carch="arm"
@@ -67,11 +68,11 @@ package() {
 }
 
 sha512sums="
-20d468ae89b57dda82d7c7b814c3d8b1b510e1623775b09a8a0b0a8a0431461e0a1d2df2bfa01f3102932c8eef91405546898b50ec3e6f30015098bb39722b41  linux-6.1.39.tar.xz
-8bc68908003e06c082f8ae3668bec3cfae9993186a0319d6b30d0c04575ee21478d9dc978eecb45d644e673e9eda3a1fe95fd35e98c0fb53e035e50f6057e9f0  config-google-veyron.armv7
-2912c675c1e07f7e91e2edcaa82738643907ed46614e4b871565930ff4ffece468d47db7905c2c081f936c020ea78db4a9d9f33b76c110125a0e68a1bd57f9fd  veyron.better_clock_selection_logic_and_dts_rate_list.patch
-b16da0e0b1da9f074a773300e954aa5e0da6c2113e20c0b594a7a4875e9addb10efcf5be694467fb00cd8d7c2e3cc83e6d7aac618047775dc0bb354245cf7c35  veyron.dts_allow_dedicating_npll_to_vop.patch
-b7bda162526abdb61c0223f1aac31893526d3d1d21d79ebd3e707be8d9b5dc464f6b4fa20b74444c44fda987352728433913f6f50b9b860c2621d11ae2306e1b  veyron.dts_do_dedicate_npll_to_vop.patch
+2a278f4b3d04ec922c4647e3e772dba98d5d615c74f93fea5414784db638212767861c0b8094d2efef79a2da208e2a54d5686b0252f82771e0b6e130a94e167a  linux-6.6.74.tar.xz
+aefe482c64b21bd7c83900cf5f685411966b7e7d9558826616081d305dcb2207adcad70646ce6e8063e24e5dabfdff0eef06a5d81754164e8f88c23ad19d25fd  config-google-veyron.armv7
+48debab56aa7e655ea7d8af6da5fa83065939f23471d3366958c924bd54f0cb8aa20f104b6d14e6b531b67e8c9320342aaf211a19c6e890105fe0302f6cd4c8a  veyron.better_clock_selection_logic_and_dts_rate_list.patch
+cec81f88da19dc928c54780bf1d39efdf23dee481bc1a3a81cb17f506328103221ef47ee020f5e5b393f20fc20242937698cb733aa376e5d79a75b98c486e513  veyron.dts_allow_dedicating_npll_to_vop.patch
+f4336cc18991a01a7d532610758c640d633d1f7ac05e42c229da418eeed109c67c721d6ed5eea593d36178fb8b420dcbd2c0759876358081c669919192330cec  veyron.dts_do_dedicate_npll_to_vop.patch
 67f49d49457eed7ae2de4582d53602743dc9c785720527d713e9b14a027a4716c755cf56e5188641cb69b35c5a561f298fa4cf2b37751696768e76e534139f40  veyron.ignore-gpt-ignoreme.patch
 30e78435b3ef7a1e2ca304297f3bb446e12acd416158707b98b4e38aa31871acac24a6671317bae752a25732534e3f273cd9ab5bf909d920b4b277a69aa11da2  veyron.support_dedicating_npll_to_vop.patch
 "

device/community/linux-google-veyron/veyron.better_clock_selection_logic_and_dts_rate_list.patch

@@ -49,7 +49,7 @@ index c14f88893868..cb7a302497a5 100644
  static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
  {
  	struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
-@@ -89,118 +94,132 @@ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
+@@ -89,126 +94,132 @@ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
  	return container_of(rkencoder, struct rockchip_hdmi, encoder);
  }
  
@@ -194,11 +194,13 @@ index c14f88893868..cb7a302497a5 100644
 -			{ 0x0051, 0x0003},
 -			{ 0x214c, 0x0003},
 -			{ 0x4064, 0x0003}
+-		},
+-	}, {
 +	},  {
-+		340000000, {
-+			{ 0x0040, 0x0003 },
-+			{ 0x3b4c, 0x0003 },
-+			{ 0x5a64, 0x0003 },
+ 		340000000, {
+ 			{ 0x0040, 0x0003 },
+ 			{ 0x3b4c, 0x0003 },
+ 			{ 0x5a64, 0x0003 },
  		},
 -	}, {
 +	},  {
@@ -234,10 +236,11 @@ index c14f88893868..cb7a302497a5 100644
 -		83500000,  { 0x0028, 0x0038, 0x0038 },
 -	}, {
 -		146250000, { 0x0038, 0x0038, 0x0038 },
-+		600000000,  { 0x0000, 0x0000, 0x0000 },
- 	}, {
+-	}, {
 -		148500000, { 0x0000, 0x0038, 0x0038 },
 -	}, {
+ 		600000000, { 0x0000, 0x0000, 0x0000 },
+ 	}, {
 -		~0UL,      { 0x0000, 0x0000, 0x0000},
 +		~0UL,       { 0x0000, 0x0000, 0x0000},
  	}
@@ -263,7 +266,7 @@ index c14f88893868..cb7a302497a5 100644
  
  	hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
  	if (IS_ERR(hdmi->regmap)) {
-@@ -237,27 +256,55 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
+@@ -237,39 +256,51 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
  	if (IS_ERR(hdmi->avdd_1v8))
  		return PTR_ERR(hdmi->avdd_1v8);
  
@@ -291,23 +294,25 @@ index c14f88893868..cb7a302497a5 100644
  }
  
  static enum drm_mode_status
--dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
+-dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
 -			    const struct drm_display_info *info,
 +dw_hdmi_rockchip_encoder_mode_valid(struct drm_encoder *encoder,
  			    const struct drm_display_mode *mode)
  {
--	const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
+-	struct rockchip_hdmi *hdmi = data;
 +	struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
+-	const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
  	int pclk = mode->clock * 1000;
--	bool valid = false;
+-	bool exact_match = hdmi->plat_data->phy_force_vendor;
 +	int num_rates = hdmi->rates_cnt;
  	int i;
  
--	for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
--		if (pclk == mpll_cfg[i].mpixelclock) {
--			valid = true;
--			break;
--		}
+-	if (hdmi->ref_clk) {
+-		int rpclk = clk_round_rate(hdmi->ref_clk, pclk);
+-
+-		if (abs(rpclk - pclk) > pclk / 1000)
+-			return MODE_NOCLOCK;
+-	}
 +	/*
 +	 * Pixel clocks we support are always < 2GHz and so fit in an
 +	 * int.  We should make sure source rate does too so we don't get
@@ -315,20 +320,27 @@ index c14f88893868..cb7a302497a5 100644
 +	 */
 +	if (mode->clock > INT_MAX / 1000)
 +		return MODE_BAD;
-+
+ 
+-	for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
+-		/*
+-		 * For vendor specific phys force an exact match of the pixelclock
+-		 * to preserve the original behaviour of the driver.
+-		 */
+-		if (exact_match && pclk == mpll_cfg[i].mpixelclock)
+-			return MODE_OK;
+-		/*
+-		 * The Synopsys phy can work with pixelclocks up to the value given
+-		 * in the corresponding mpll_cfg entry.
+-		 */
+-		if (!exact_match && pclk <= mpll_cfg[i].mpixelclock)
 +	for (i = 0; i < num_rates; i++) {
 +		int slop = CLK_SLOP(pclk);
 +
 +		if ((pclk >= hdmi->rates[i] - slop) &&
 +		    (pclk <= hdmi->rates[i] + slop))
-+			return MODE_OK;
+ 			return MODE_OK;
  	}
  
--	return (valid) ? MODE_OK : MODE_BAD;
-+	return MODE_BAD;
- }
- 
- static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
 @@ -269,7 +316,39 @@ dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
  				    const struct drm_display_mode *mode,
  				    struct drm_display_mode *adj_mode)

device/community/linux-google-veyron/veyron.dts_allow_dedicating_npll_to_vop.patch

@@ -14,8 +14,8 @@ Signed-off-by: Urja Rannikko <urjaman@gmail.com>
 
 diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
 index aaaa61875701d..e8cb4dc8c27da 100644
---- a/arch/arm/boot/dts/rk3288.dtsi
-+++ b/arch/arm/boot/dts/rk3288.dtsi
+--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
 @@ -865,12 +865,14 @@
  		rockchip,grf = <&grf>;
  		#clock-cells = <1>;

device/community/linux-google-veyron/veyron.dts_do_dedicate_npll_to_vop.patch

@@ -16,8 +16,8 @@ Signed-off-by: Urja Rannikko <urjaman@gmail.com>
 
 diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
 index 05112c25176d3..4d972bd6741c1 100644
---- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
-+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
+--- a/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi
++++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi
 @@ -83,6 +83,68 @@
  	};
  };